[U-Boot] [PATCH v6 0/5] iMX6 SabreSD SPL Support
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Changes (v2): Merged the SPL support into the main board file Remove the compilation warmings
Changes (v3): Removed sp and gd Use imx_ddr_size to set the ram_size
Changes (v4): Add a separate board configuration file to enable SPL (mx6sabresd_spl_defconfig).
Mapped DCD data to mx6_mmdc_calibration, mx6dq_iomux_grp_regs, mx6dq_iomux_ddr_regs and mx6_ddr3_cfg data structures.
Read 11 and 12 bits of BOOT_CFG register to actually determine the active mmc port.
Changes (v5): Use the default CONFIG_SPL_STACK Add a macro #ifndef for CONFIG_SYS_TEXT_BASE to avoid compilation warning.
Changes (v6): Use board_mmc_init for spl mmc initialization instead of adding spl_board_mmc_init function
John Tobias (5): imx6: add spl config for mx6sabresd imx6: add data configuration file for SPL kconfig: imx6: add SUPPORT_SPL imx6: add spl in the header file imx6: SPL support for iMX6 SabreSD
arch/arm/Kconfig | 1 + board/freescale/mx6sabresd/mx6sabresd.c | 186 +++++++++++++++++++++++++- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 ++++++++ configs/mx6sabresd_spl_defconfig | 5 + include/configs/mx6sabre_common.h | 2 + include/configs/mx6sabresd.h | 6 + 6 files changed, 256 insertions(+), 2 deletions(-) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg create mode 100644 configs/mx6sabresd_spl_defconfig
add a build configuration file for mx6sabresd with spl support
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- configs/mx6sabresd_spl_defconfig | 5 +++++ 1 file changed, 5 insertions(+) create mode 100644 configs/mx6sabresd_spl_defconfig
diff --git a/configs/mx6sabresd_spl_defconfig b/configs/mx6sabresd_spl_defconfig new file mode 100644 index 0000000..b7b26df --- /dev/null +++ b/configs/mx6sabresd_spl_defconfig @@ -0,0 +1,5 @@ +CONFIG_SPL=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6sabresd_spl.cfg,SPL,MX6Q" ++S:CONFIG_ARM=y ++S:CONFIG_TARGET_MX6SABRESD=y +
It's a trim version of mx6q_4x_mt41j128.cfg. It just removed the related settings for DDR
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- board/freescale/mx6sabresd/mx6sabresd_spl.cfg | 58 +++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 board/freescale/mx6sabresd/mx6sabresd_spl.cfg
diff --git a/board/freescale/mx6sabresd/mx6sabresd_spl.cfg b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg new file mode 100644 index 0000000..2bf4817 --- /dev/null +++ b/board/freescale/mx6sabresd/mx6sabresd_spl.cfg @@ -0,0 +1,58 @@ +/* + * Copyright (C) 2011 Freescale Semiconductor, Inc. + * Jason Liu r64343@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Refer doc/README.imximage for more details about how-to configure + * and create imximage boot image + * + * The syntax is taken as close as possible with the kwbimage + */ + +/* image version */ +IMAGE_VERSION 2 + +/* + * Boot Device : one of + * spi, sd (the board has no nand neither onenand) + */ +BOOT_FROM sd + +/* + * Device Configuration Data (DCD) + * + * Each entry must have the format: + * Addr-type Address Value + * + * where: + * Addr-type register length (1,2 or 4 bytes) + * Address absolute address of the register + * value value to be stored in the register + */ + +/* set the default clock gate to save power */ +DATA 4 0x020c4068 0x00C03F3F +DATA 4 0x020c406c 0x0030FC03 +DATA 4 0x020c4070 0x0FFFC000 +DATA 4 0x020c4074 0x3FF00000 +DATA 4 0x020c4078 0x00FFF300 +DATA 4 0x020c407c 0x0F0000C3 +DATA 4 0x020c4080 0x000003FF + +/* enable AXI cache for VDOA/VPU/IPU */ +DATA 4 0x020e0010 0xF00000CF +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +DATA 4 0x020e0018 0x007F007F +DATA 4 0x020e001c 0x007F007F + +/* + * Setup CCM_CCOSR register as follows: + * + * cko1_en = 1 --> CKO1 enabled + * cko1_div = 111 --> divide by 8 + * cko1_sel = 1011 --> ahb_clk_root + * + * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz + */ +DATA 4 0x020c4060 0x000000fb
add SUPPORT_SPL feature for iMX6 SabreSD. It need to use mx6sabresd_spl_defconfig to compile it.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 22eb2d5..ab0d284 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -609,6 +609,7 @@ config TARGET_MX6QSABREAUTO config TARGET_MX6SABRESD bool "Support mx6sabresd" select CPU_V7 + select SUPPORT_SPL
config TARGET_MX6SLEVK bool "Support mx6slevk"
add the spl info in the header file. Also, added a macro statement in m6sabre_common.h to avoid compiler warning.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- include/configs/mx6sabre_common.h | 2 ++ include/configs/mx6sabresd.h | 6 ++++++ 2 files changed, 8 insertions(+)
diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index c81e9e9..e4d0d14 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -95,7 +95,9 @@ #define CONFIG_BOOTDELAY 1
#define CONFIG_LOADADDR 0x12000000 +#ifndef CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_TEXT_BASE 0x17800000 +#endif
#ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 938030d..a346542 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -12,6 +12,12 @@ #include <asm/arch/imx-regs.h> #include <asm/imx-common/gpio.h>
+#ifdef CONFIG_SPL +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#include "imx6_spl.h" +#endif + #define CONFIG_MACH_TYPE 3980 #define CONFIG_MXC_UART_BASE UART1_BASE #define CONFIG_CONSOLE_DEV "ttymxc0"
This patch will enable the support for SPL on iMX6 SabreSD. It tested on SD2 and SD3 mmc port.
It uses mx6dq_dram_iocfg and mx6_dram_cfg for ddr configuration.
Signed-off-by: John Tobias john.tobias.ph@gmail.com --- board/freescale/mx6sabresd/mx6sabresd.c | 186 +++++++++++++++++++++++++++++++- 1 file changed, 184 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 3d81fff..b1d259d 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -27,8 +27,12 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <asm/arch/mx6-ddr.h> + DECLARE_GLOBAL_DATA_PTR;
+#define BOOT_CFG 0x020D8004 + #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -55,8 +59,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); - + gd->ram_size = imx_ddr_size(); return 0; }
@@ -253,6 +256,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_init(bd_t *bis) { +#ifndef CONFIG_SPL_BUILD s32 status = 0; int i;
@@ -293,6 +297,43 @@ int board_mmc_init(bd_t *bis) }
return status; +#else + unsigned reg = readl(BOOT_CFG) >> 11; + /* + * Upon reading BOOT_CFG register the following map is done: + * Bit 11 and 12 of BOOT_CFG register can determine the current + * mmc port + * 0x1 SD1 + * 0x2 SD2 + * 0x3 SD4 + */ + + switch (reg & 0x3) { + case 0x1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + case 0x3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + break; + } + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #endif
@@ -607,3 +648,144 @@ int checkboard(void) puts("Board: MX6-SabreSD\n"); return 0; } + +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#include <libfdt.h> + +const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdba2 = 0x00000000, + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = { + .grp_ddr_type = 0x000C0000, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_addds = 0x00000030, + .grp_ctlds = 0x00000030, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x001F001F, + .p0_mpwldectrl1 = 0x001F001F, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + .p0_mpdgctrl0 = 0x434B0350, + .p0_mpdgctrl1 = 0x034C0359, + .p1_mpdgctrl0 = 0x434B0350, + .p1_mpdgctrl1 = 0x03650348, + .p0_mprddlctl = 0x4436383B, + .p1_mprddlctl = 0x39393341, + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254A36, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 64, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * This section require the differentiation + * between iMX6 Sabre Families. + * But for now, it will configure only for + * SabreSD. + */ +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = mem_ddr.width/32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 2, + .cs1_mirror = 0, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} +#endif
Hi John,
On Wed, Nov 12, 2014 at 3:14 PM, John Tobias john.tobias.ph@gmail.com wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Thanks for working on this of for your patience.
It worked fine here:
Tested-by: Fabio Estevam fabio.estevam@freescale.com Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Hi Fabio,
Thanks for the info.
Regards,
john
On Wed, Nov 12, 2014 at 10:19 AM, Fabio Estevam festevam@gmail.com wrote:
Hi John,
On Wed, Nov 12, 2014 at 3:14 PM, John Tobias john.tobias.ph@gmail.com wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Thanks for working on this of for your patience.
It worked fine here:
Tested-by: Fabio Estevam fabio.estevam@freescale.com Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Hi John,
On Wed, Nov 12, 2014 at 4:19 PM, Fabio Estevam festevam@gmail.com wrote:
Hi John,
On Wed, Nov 12, 2014 at 3:14 PM, John Tobias john.tobias.ph@gmail.com wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Thanks for working on this of for your patience.
It worked fine here:
Tested-by: Fabio Estevam fabio.estevam@freescale.com Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Actually, I noticed that the SPL version detects 2GB of RAM instead of 1GB.
Here is a fix for this:
--- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -741,7 +741,7 @@ static void spl_dram_init(void) /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */ - .ncs = 2, + .ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
On sabresd only CS0 is used to select all the four DDR3 chips.
Thanks
Hi Fabio,
Thanks for catching it.
Regards,
john
On Wed, Nov 12, 2014 at 1:14 PM, Fabio Estevam festevam@gmail.com wrote:
Hi John,
On Wed, Nov 12, 2014 at 4:19 PM, Fabio Estevam festevam@gmail.com wrote:
Hi John,
On Wed, Nov 12, 2014 at 3:14 PM, John Tobias john.tobias.ph@gmail.com wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images. You should run the two commands below to store it in your SD or eMMC.
sudo dd if=SPL of=/dev/xxx bs=1K seek=1; sync sudo dd if=u-boot.img of=/dev/xxx bs=1K seek=69
Thanks for working on this of for your patience.
It worked fine here:
Tested-by: Fabio Estevam fabio.estevam@freescale.com Reviewed-by: Fabio Estevam fabio.estevam@freescale.com
Actually, I noticed that the SPL version detects 2GB of RAM instead of 1GB.
Here is a fix for this:
--- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -741,7 +741,7 @@ static void spl_dram_init(void) /* config for full 4GB range so that get_mem_size() works */ .cs_density = 32, /* 32Gb per CS */ /* single chip select */
.ncs = 2,
.ncs = 1, .cs1_mirror = 0, .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */On sabresd only CS0 is used to select all the four DDR3 chips.
Thanks
Hi John,
On 11/12/2014 07:14 PM, John Tobias wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images.
Is it still possible to build a regular, non-SPL image for the SabreSD?
Regards, Nikolay
On Wed, Nov 12, 2014 at 6:42 PM, Nikolay Dimitrov picmaster@mail.bg wrote:
Hi John,
On 11/12/2014 07:14 PM, John Tobias wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images.
Is it still possible to build a regular, non-SPL image for the SabreSD?
Yes, it still works and I have tested it too.
make mx6qsabresd_config make
will generate the non-SPL u-boot.imx binary.
Hi Fabio,
On 11/12/2014 10:45 PM, Fabio Estevam wrote:
On Wed, Nov 12, 2014 at 6:42 PM, Nikolay Dimitrov picmaster@mail.bg wrote:
Hi John,
On 11/12/2014 07:14 PM, John Tobias wrote:
This patch is for SPL support for iMX6 SabreSD. The said patches has been tested to work on SD2 and SD3 port of the said board.
After applying the following patches, it will produces SPL and u-boot.img binary images.
Is it still possible to build a regular, non-SPL image for the SabreSD?
Yes, it still works and I have tested it too.
make mx6qsabresd_config make
will generate the non-SPL u-boot.imx binary.
Thanks. This is great, as the non-SPL version is much easier to upload via OTG. At least I don't know a way to boot the SPL+complete loader through OTG.
Regards, Nikolay
participants (3)
-
Fabio Estevam -
John Tobias -
Nikolay Dimitrov