From: Tien Fong Chee tien.fong.chee@intel.com

These are interface for users to customize some settings in DDR self-refresh configuration according to their design requirement.

Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)

diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi index 6c1d25fa05..f7f594238a 100644 --- a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi +++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi @@ -13,6 +13,12 @@ i2c0 = &i2c1; };

+ fs_loader0: fs-loader { + u-boot,dm-pre-reloc; + compatible = "u-boot,fs-loader"; + sfconfig = <0 0 100000000 3>; + }; + memory { /* <<<<<<< HEAD @@ -41,6 +47,13 @@ }; };

+&sdr { + intel,ddrcal-qspi-offset = "0x7000000"; + intel,ddrcal-ddr-offset = "0x100000"; + firmware-loader = <&fs_loader0>; + u-boot,dm-pre-reloc; +}; + &flash0 { compatible = "jedec,spi-nor"; spi-tx-bus-width = <4>;