[U-Boot] [PATCH v2 0/6] board: ti: am43xx: Enable hardware leveling
The series adds the support for hardware leveling. This needs the kernel to be patched with hardware leveling support and the kernel support is already in linux-next:
https://patchwork.kernel.org/project/linux-omap/list/?series=100273
Match recommended values from EMIF Tools app note: http://www.ti.com/lit/an/sprac70/sprac70.pdf
The patch series is tested for AM437x-gp-evm DS0 and RTC+DRR mode on linux-next in kernel.
Changes in v2:
* Fixed am335x build issue.
Tested on AM437x-gp-evm for rtc+ddr mode and DS0 Tested on am335x-evm and beaglebone black for DS0 and rtcwake from DS0 Compile tested omap3 and omap4 defconfigs as well.
Brad Griffis (6): arm: mach-omap2: am33xx: ddr: programming of EXT_PHY_CTRL1 and EXT_PHY_CTRL1_SHADOW arm: mach-omap2: am33xx: ddr: Add 1ms delay to avoid L3 error arm: mach-omap2: am33xx: Enable HW Leveling in the rtc+ddr path arm: mach-omap2: am33xx: ddr: update value for ext_phy_ctrl_36 board: ti: am43xx: Enable hardware leveling arm: mach-omap2: am33xx: Disable EMIF_DEVOFF immediately before hw leveling
arch/arm/mach-omap2/am33xx/board.c | 31 +++++++++++++++++++++++++--- arch/arm/mach-omap2/am33xx/ddr.c | 33 ++++++++++++++++++++++++++---- board/ti/am43xx/board.c | 2 +- 3 files changed, 58 insertions(+), 8 deletions(-)
From: Brad Griffis bgriffis@ti.com
Adjust DQS skew in case where invert_clkout=1 is used. Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/mach-omap2/am33xx/ddr.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index be6f4d72cc..816d4e8e05 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -256,8 +256,16 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) * Enable hardware leveling on the EMIF. For details about these * magic values please see the EMIF registers section of the TRM. */ - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); - writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + if (regs->emif_ddr_phy_ctlr_1 & 0x00040000) { + /* PHY_INVERT_CLKOUT = 1 */ + writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x00040100, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + } else { + /* PHY_INVERT_CLKOUT = 0 */ + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1); + writel(0x08020080, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_1_shdw); + } + writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_22_shdw); writel(0x00600020, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_23);
On Mon, Apr 29, 2019 at 09:59:28AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
Adjust DQS skew in case where invert_clkout=1 is used. Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
From: Brad Griffis bgriffis@ti.com
Add 1ms delay to avoid L3 timeout error during suspend resume.
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/mach-omap2/am33xx/ddr.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 816d4e8e05..5d947a68c3 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -138,6 +138,9 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) /* Enable read leveling */ writel(0x80000000, &emif_reg[nr]->emif_rd_wr_lvl_ctl);
+ /* Wait 1ms because of L3 timeout error */ + udelay(1000); + /* * Enable full read and write leveling. Wait for read and write * leveling bit to clear RDWRLVLFULL_START bit 31
On Mon, Apr 29, 2019 at 09:59:29AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
Add 1ms delay to avoid L3 timeout error during suspend resume.
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
From: Brad Griffis bgriffis@ti.com
Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register.
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/mach-omap2/am33xx/board.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 62158a9592..fe7b8e1e55 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -38,6 +38,14 @@ #include <asm/omap_musb.h> #include <asm/davinci_rtc.h>
+#define AM43XX_EMIF_BASE 0x4C000000 +#define AM43XX_SDRAM_CONFIG_OFFSET 0x8 +#define AM43XX_SDRAM_TYPE_MASK 0xE0000000 +#define AM43XX_SDRAM_TYPE_SHIFT 29 +#define AM43XX_SDRAM_TYPE_DDR3 3 +#define AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET 0xDC +#define AM43XX_RDWRLVLFULL_START 0x80000000 + DECLARE_GLOBAL_DATA_PTR;
int dram_init(void) @@ -435,7 +443,7 @@ static void rtc_only(void) struct prm_device_inst *prm_device = (struct prm_device_inst *)PRM_DEVICE_INST;
- u32 scratch1; + u32 scratch1, sdrc; void (*resume_func)(void);
scratch1 = readl(&rtc->scratch1); @@ -476,6 +484,26 @@ static void rtc_only(void) /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ writel(0, &prm_device->emif_ctrl);
+ /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */ + /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */ + sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET); + + sdrc &= AM43XX_SDRAM_TYPE_MASK; + sdrc >>= AM43XX_SDRAM_TYPE_SHIFT; + + if (sdrc == AM43XX_SDRAM_TYPE_DDR3) { + writel(AM43XX_RDWRLVLFULL_START, + AM43XX_EMIF_BASE + + AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); + mdelay(1); + +am43xx_wait: + sdrc = readl(AM43XX_EMIF_BASE + + AM43XX_READ_WRITE_LEVELING_CTRL_OFFSET); + if (sdrc == AM43XX_RDWRLVLFULL_START) + goto am43xx_wait; + } + resume_func = (void *)readl(&rtc->scratch0); if (resume_func) resume_func();
On Mon, Apr 29, 2019 at 09:59:30AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
Enable HW leveling in RTC+DDR path. The mandate is to enable HW leveling bit and then wait for 1 ms before accessing any register.
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
From: Brad Griffis bgriffis@ti.com
In case of RTC+DDR resume, need to restore EMIF context before initiating hardware leveling.
Signed-off-by: Brad Griffis bgriffis@ti.com [j-keerthy@ti.com Fixed the am335x build issues] Signed-off-by: Keerthy j-keerthy@ti.com ---
Changes in v2:
* Added the am43xx specific changes under #ifdef
arch/arm/mach-omap2/am33xx/board.c | 3 --- arch/arm/mach-omap2/am33xx/ddr.c | 14 ++++++++++++++ 2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index fe7b8e1e55..5507348981 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -481,9 +481,6 @@ static void rtc_only(void) rtc_only_prcm_init(); sdram_init();
- /* Disable EMIF_DEVOFF for normal operation and to exit self-refresh */ - writel(0, &prm_device->emif_ctrl); - /* Check EMIF4D_SDRAM_CONFIG[31:29] SDRAM_TYPE */ /* Only perform leveling if SDRAM_TYPE = 3 (DDR3) */ sdrc = readl(AM43XX_EMIF_BASE + AM43XX_SDRAM_CONFIG_OFFSET); diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index 5d947a68c3..c70b6fe31b 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -80,6 +80,11 @@ static void configure_mr(int nr, u32 cs) */ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) { +#ifdef CONFIG_AM43XX + struct prm_device_inst *prm_device = + (struct prm_device_inst *)PRM_DEVICE_INST; +#endif + writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl); writel(0xA0, &emif_reg[nr]->emif_pwr_mgmt_ctrl_shdw); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); @@ -126,6 +131,15 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw);
+#ifdef CONFIG_AM43XX + /* + * Disable EMIF_DEVOFF + * -> Cold Boot: This is just rewriting the default register value. + * -> RTC Resume: Must disable DEVOFF before leveling. + */ + writel(0, &prm_device->emif_ctrl); +#endif + /* Perform hardware leveling for DDR3 */ if (emif_sdram_type(regs->sdram_config) == EMIF_SDRAM_TYPE_DDR3) { writel(readl(&emif_reg[nr]->emif_ddr_ext_phy_ctrl_36) |
On Mon, Apr 29, 2019 at 09:59:31AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
In case of RTC+DDR resume, need to restore EMIF context before initiating hardware leveling.
Signed-off-by: Brad Griffis bgriffis@ti.com [j-keerthy@ti.com Fixed the am335x build issues] Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
From: Brad Griffis bgriffis@ti.com
for suspend/resume robustness
update value for ext_phy_ctrl_36 for suspend/resume robustness with hardware leveling enabled.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com --- arch/arm/mach-omap2/am33xx/ddr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index c70b6fe31b..3fd1d086ff 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -311,8 +311,8 @@ static void ext_phy_settings_hwlvl(const struct emif_regs *regs, int nr) writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_34_shdw); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35); writel(0x00000000, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_35_shdw); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); - writel(0x000000FF, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36); + writel(0x00000077, &emif_reg[nr]->emif_ddr_ext_phy_ctrl_36_shdw);
/* * Sequence to ensure that the PHY is again in a known state after
On Mon, Apr 29, 2019 at 09:59:32AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
for suspend/resume robustness
update value for ext_phy_ctrl_36 for suspend/resume robustness with hardware leveling enabled.
Match recommended values from EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
From: Brad Griffis bgriffis@ti.com
Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable PHY_INVERT_CLKOUT to enable Hardware leveling for am437x as recommended by EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com --- board/ti/am43xx/board.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/ti/am43xx/board.c b/board/ti/am43xx/board.c index 536c5b88ed..d29a22cf05 100644 --- a/board/ti/am43xx/board.c +++ b/board/ti/am43xx/board.c @@ -244,7 +244,7 @@ const struct emif_regs ddr3_emif_regs_400Mhz_production = { .read_idle_ctrl = 0x00050000, .zq_config = 0x50074BE4, .temp_alert_config = 0x0, - .emif_ddr_phy_ctlr_1 = 0x0E004008, + .emif_ddr_phy_ctlr_1 = 0x00048008, .emif_ddr_ext_phy_ctrl_1 = 0x08020080, .emif_ddr_ext_phy_ctrl_2 = 0x00000066, .emif_ddr_ext_phy_ctrl_3 = 0x00000091,
On Mon, Apr 29, 2019 at 09:59:33AM +0530, Keerthy wrote:
From: Brad Griffis bgriffis@ti.com
Remove the RDLVL_MASK, RDLVLGATE_MASK, WRLVL_MASK & enable PHY_INVERT_CLKOUT to enable Hardware leveling for am437x as recommended by EMIF Tools app note:
http://www.ti.com/lit/an/sprac70/sprac70.pdf
Signed-off-by: Brad Griffis bgriffis@ti.com Signed-off-by: Keerthy j-keerthy@ti.com
Applied to u-boot/master, thanks!
participants (2)
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Keerthy -
Tom Rini