[U-Boot] [PATCH 1/3] add support for arm926ejs-based pollux CPU
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com --- arch/arm/cpu/arm926ejs/pollux/Makefile | 51 ++++++++ arch/arm/cpu/arm926ejs/pollux/reset.S | 49 ++++++++ arch/arm/cpu/arm926ejs/pollux/timer.c | 190 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-pollux/clkpwr.h | 83 +++++++++++++ arch/arm/include/asm/arch-pollux/gpio.h | 143 ++++++++++++++++++++++ arch/arm/include/asm/arch-pollux/reg.h | 39 ++++++ arch/arm/include/asm/arch-pollux/timer.h | 59 +++++++++ arch/arm/include/asm/arch-pollux/uart.h | 105 ++++++++++++++++ 8 files changed, 719 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/pollux/Makefile create mode 100644 arch/arm/cpu/arm926ejs/pollux/reset.S create mode 100644 arch/arm/cpu/arm926ejs/pollux/timer.c create mode 100644 arch/arm/include/asm/arch-pollux/clkpwr.h create mode 100644 arch/arm/include/asm/arch-pollux/gpio.h create mode 100644 arch/arm/include/asm/arch-pollux/reg.h create mode 100644 arch/arm/include/asm/arch-pollux/timer.h create mode 100644 arch/arm/include/asm/arch-pollux/uart.h
diff --git a/arch/arm/cpu/arm926ejs/pollux/Makefile b/arch/arm/cpu/arm926ejs/pollux/Makefile new file mode 100644 index 0000000..32803ff --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/Makefile @@ -0,0 +1,51 @@ +# (C) Copyright 2010 cozybit, Inc +# Brian Cavagnolo brian@cozybit.com +# +# Derived from versatile cpu support: +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(SOC).a + +COBJS = timer.o +SOBJS = reset.o + +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/arch/arm/cpu/arm926ejs/pollux/reset.S b/arch/arm/cpu/arm926ejs/pollux/reset.S new file mode 100644 index 0000000..a66a89f --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/reset.S @@ -0,0 +1,49 @@ +/* (C) Copyright 2010 cozybit, Inc + * Brian Cavagnolo brian@cozybit.com + * + * Derived from versatile cpu support: + * + * armboot - Startup Code for ARM926EJS CPU-core + * + * Copyright (c) 2003 Texas Instruments + * + * ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------ + * + * Copyright (c) 2001 Marius Gröger mag@sysgo.de + * Copyright (c) 2002 Alex Züpke azu@sysgo.de + * Copyright (c) 2002 Gary Jennejohn garyj@denx.de + * Copyright (c) 2003 Richard Woodruff r-woodruff2@ti.com + * Copyright (c) 2003 Kshitij kshitij@ti.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + .align 5 +.globl reset_cpu +reset_cpu: + ldr r1, rstctl1 /* get clkm1 reset ctl */ + mov r3, #0x0 + strh r3, [r1] /* clear it */ + mov r3, #0x8 + strh r3, [r1] /* force dsp+arm reset */ +_loop_forever: + b _loop_forever + +rstctl1: + .word 0xfffece10 diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c b/arch/arm/cpu/arm926ejs/pollux/timer.c new file mode 100644 index 0000000..fc6c699 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/timer.c @@ -0,0 +1,190 @@ +/* (C) Copyright 2010 cozybit, Inc + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc + * + * Derived from versatile cpu support: + * + * (C) Copyright 2003 + * Texas Instruments <www.ti.com> + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger mgroeger@sysgo.de + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Alex Zuepke azu@sysgo.de + * + * (C) Copyright 2002-2004 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2004 + * Philippe Robin, ARM Ltd. philippe.robin@arm.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/reg.h> +#include <asm/arch/timer.h> + +#ifndef CONFIG_SYS_TIMERBASE +#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE" +#endif +#define TIMERBASE CONFIG_SYS_TIMERBASE + +#define TIMER_LOAD_VAL 0xffffffff + +static ulong inline read_timer(void) +{ + REG32(TIMERBASE + TMRCONTROL) |= (1<<LDCNT); + return REG32(TIMERBASE + TMRMATCH); +} + +static ulong timestamp; +static ulong lastdec; + +int timer_init (void) +{ + REG32(TIMERBASE + TMRCLKENB) = (1<<TCLKMODE)|(1<<TCLKGENENB); + REG32(TIMERBASE + TMRCOUNT) = 0; + REG32(TIMERBASE + TMRMATCH) = TIMER_LOAD_VAL; + REG32(TIMERBASE + TMRCONTROL) |= (1<<RUN); + + /* init the timestamp and lastdec value */ + reset_timer_masked(); + + return 0; +} + +/* + * timer without interrupts + */ + +void reset_timer (void) +{ + reset_timer_masked(); +} + +ulong get_timer (ulong base) +{ + return get_timer_masked() - base; +} + +void set_timer (ulong t) +{ + timestamp = t; +} + +/* delay x useconds AND perserve advance timstamp value */ +void __udelay (unsigned long usec) +{ + ulong tmo, tmp; + + if(usec >= 1000){ /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + }else{ /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + tmp = get_timer (0); /* get current timestamp */ + if( (tmo + tmp + 1) < tmp ) /* if setting this fordward will roll time stamp */ + reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastdec value */ + else + tmo += tmp; /* else, set advancing stamp wake up time */ + + while (get_timer_masked () < tmo)/* loop till event */ + /*NOP*/; +} + +void reset_timer_masked (void) +{ + /* reset time */ + lastdec = read_timer(); /* capure current decrementer value time */ + timestamp = 0; /* start "advancing" time stamp from 0 */ +} + +ulong get_timer_masked (void) +{ + ulong now = read_timer(); /* current tick value */ + + if (lastdec >= now) { /* normal mode (non roll) */ + /* normal mode */ + timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */ + } else { /* we have overflow of the count down timer */ + /* nts = ts + ld + (TLV - now) + * ts=old stamp, ld=time that passed before passing through -1 + * (TLV-now) amount of time after passing though -1 + * nts = new "advancing time stamp"...it could also roll and cause problems. + */ + timestamp += lastdec + TIMER_LOAD_VAL - now; + } + lastdec = now; + + return timestamp; +} + +/* waits specified delay value and resets timestamp */ +void udelay_masked (unsigned long usec) +{ + ulong tmo; + ulong endtime; + signed long diff; + + if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ + tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ + tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */ + tmo /= 1000; /* finish normalize. */ + } else { /* else small number, don't kill it prior to HZ multiply */ + tmo = usec * CONFIG_SYS_HZ; + tmo /= (1000*1000); + } + + endtime = get_timer_masked () + tmo; + + do { + ulong now = get_timer_masked (); + diff = endtime - now; + } while (diff >= 0); +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk (void) +{ + ulong tbclk; + + tbclk = CONFIG_SYS_HZ; + return tbclk; +} diff --git a/arch/arm/include/asm/arch-pollux/clkpwr.h b/arch/arm/include/asm/arch-pollux/clkpwr.h new file mode 100644 index 0000000..d6e97d2 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/clkpwr.h @@ -0,0 +1,83 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CLKPWR_H__ +#define __CLKPWR_H__ + +/* Clock and Power Control Registers */ +#define CLKPWR_BASE 0xC000F000 +#define CLKMODEREG (CLKPWR_BASE + 0x000) +#define PLLSETREG0 (CLKPWR_BASE + 0x004) +#define PLLSETREG1 (CLKPWR_BASE + 0x008) +#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040) +#define RTCWAKEUPENB (CLKPWR_BASE + 0x044) +#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048) +#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C) +#define GPIOPEND (CLKPWR_BASE + 0x050) +#define INTPENDSPAD (CLKPWR_BASE + 0x058) +#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C) +#define INTENB (CLKPWR_BASE + 0x060) +#define PWRMODE (CLKPWR_BASE + 0x07C) +#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100) +#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104) +#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108) +#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C) +#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110) +#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114) +#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118) + +/* Clock Mode Register (CLKMODEREG) */ +#define PLLPWDN1 30 +#define CLKSELBCLK 24 +#define CLKDIV1BCLK 20 +#define CLKDIV2CPU0 6 +#define CLKSELCPU0 4 +#define CLKDIVCPU0 0 + +/* PLL0/PLL1 Setting Register (PLLSETREG0/PLLSETREG1) */ +#define PDIV 18 +#define MDIV 8 +#define SDIV 0 + +/* convenience macro for setting PLL */ +#define PLL_REG(m, p, s) \ + (((unsigned int)(m) << MDIV) | \ + ((unsigned int)(p) << PDIV) | \ + ((unsigned int)(s) << SDIV)) + +/* Power Mode Control Register (PWRMODE) */ +#define CHGPLL 15 +#define GPIOSWRSTENB 13 +#define SWRST 12 +#define LASTPWRMODE 4 +#define CURPWRMODE 0 + +/* Interrupt Pending & Scratch Pad Register (INTPENDSPAD) */ +#define BATFW 14 +#define GPIORESETW 13 +#define WATCHDOGRSTW 12 +#define POWERONRSTW 11 + +#endif /* __CLKPWR_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/gpio.h b/arch/arm/include/asm/arch-pollux/gpio.h new file mode 100644 index 0000000..f6ddd1b --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/gpio.h @@ -0,0 +1,143 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __GPIO_H__ +#define __GPIO_H__ + +/* GPIO registers */ +#define GPIO_BASE 0xC000A000 + +#define GPIOAOUT (GPIO_BASE + 0x00) +#define GPIOAOUTENB (GPIO_BASE + 0x04) +#define GPIOADETMODE0 (GPIO_BASE + 0x08) +#define GPIOADETMODE1 (GPIO_BASE + 0x0C) +#define GPIOAINTENB (GPIO_BASE + 0x10) +#define GPIOADET (GPIO_BASE + 0x14) +#define GPIOAPAD (GPIO_BASE + 0x18) +#define GPIOAPUENB (GPIO_BASE + 0x1C) +#define GPIOAALTFN0 (GPIO_BASE + 0x20) +#define GPIOAALTFN1 (GPIO_BASE + 0x24) + +#define GPIOBOUT (GPIO_BASE + 0x40) +#define GPIOBOUTENB (GPIO_BASE + 0x44) +#define GPIOBDETMODE0 (GPIO_BASE + 0x48) +#define GPIOBDETMODE1 (GPIO_BASE + 0x4C) +#define GPIOBINTENB (GPIO_BASE + 0x50) +#define GPIOBDET (GPIO_BASE + 0x54) +#define GPIOBPAD (GPIO_BASE + 0x58) +#define GPIOBPUENB (GPIO_BASE + 0x5C) +#define GPIOBALTFN0 (GPIO_BASE + 0x60) +#define GPIOBALTFN1 (GPIO_BASE + 0x64) + +#define GPIOCOUT (GPIO_BASE + 0x80) +#define GPIOCOUTENB (GPIO_BASE + 0x84) +#define GPIOCDETMODE0 (GPIO_BASE + 0x88) +#define GPIOCDETMODE1 (GPIO_BASE + 0x8C) +#define GPIOCINTENB (GPIO_BASE + 0x90) +#define GPIOCDET (GPIO_BASE + 0x94) +#define GPIOCPAD (GPIO_BASE + 0x98) +#define GPIOCPUENB (GPIO_BASE + 0x9C) +#define GPIOCALTFN0 (GPIO_BASE + 0xA0) +#define GPIOCALTFN1 (GPIO_BASE + 0xA4) + +/* GPIO Alive Registers */ +#define GPIO_ALIVE_BASE 0xC0019000 +#define ALIVEPWRGATEREG (GPIO_ALIVE_BASE + 0x00) +#define ALIVEGPIORSTREG (GPIO_ALIVE_BASE + 0x04) +#define ALIVEGPIOSETREG (GPIO_ALIVE_BASE + 0x08) +#define ALIVEGPIOREADREG (GPIO_ALIVE_BASE + 0x0C) +#define ALIVESCRATCHRSTREG (GPIO_ALIVE_BASE + 0x10) +#define ALIVESCRATCHSETREG (GPIO_ALIVE_BASE + 0x14) +#define ALIVESCRATCHREADREG (GPIO_ALIVE_BASE + 0x18) + +/* Alive GPIO Gate Register (ALIVEGPIOGATEREG) */ +#define NPOWERGATING 0 + +/* Alive GPIO Register bit names + * same for ALIVEGPIORSTREG, ALIVEGPIOSETREG and ALIVEGPIOREADREG + */ +#define VDDPWRONSET 7 + +/* Alive GPIO Read Register (ALIVEGPIOREADREG) */ +#define VDDPWRTOGGLE 8 + +/* Current settings */ +#define GPIO_CURRENT_BASE 0xC000F100 +#define GPIOAPADSTRENGTH_L (GPIO_CURRENT_BASE + 0x00) +#define GPIOAPADSTRENGTH_H (GPIO_CURRENT_BASE + 0x04) +#define GPIOAPBDSTRENGTH_L (GPIO_CURRENT_BASE + 0x08) +#define GPIOAPBDSTRENGTH_H (GPIO_CURRENT_BASE + 0x0C) +#define GPIOAPCDSTRENGTH_L (GPIO_CURRENT_BASE + 0x10) +#define GPIOAPCDSTRENGTH_H (GPIO_CURRENT_BASE + 0x14) + +/* Convenience macros for generating pin configurations for ALTFNn registers */ +#define ALTFN0_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2)) +#define ALTFN0_PIN_MASK(pin) ALTFN0_PIN_CFG(pin, 0x3) +#define ALTFN1_PIN_CFG(pin, cfg) ((cfg)<<((pin)*2-32)) +#define ALTFN1_PIN_MASK(pin) ALTFN1_PIN_CFG(pin, 0x3) + + +enum gpio_port { + GPIO_PORT_A = 0, + GPIO_PORT_B, + GPIO_PORT_C, + GPIO_PORT_ALV, +}; + +/* Each pin can take one of three different functions */ +enum gpio_function { + GPIO_GPIOFN = 0, + GPIO_ALT1, + GPIO_ALT2, + GPIO_RESERVED, +}; + +/* Each port has 32 pins */ +enum gpio_pin { + GPIO_PIN0 = 0, GPIO_PIN1, GPIO_PIN2, GPIO_PIN3, GPIO_PIN4, GPIO_PIN5, + GPIO_PIN6, GPIO_PIN7, GPIO_PIN8, GPIO_PIN9, GPIO_PIN10, GPIO_PIN11, + GPIO_PIN12, GPIO_PIN13, GPIO_PIN14, GPIO_PIN15, GPIO_PIN16, GPIO_PIN17, + GPIO_PIN18, GPIO_PIN19, GPIO_PIN20, GPIO_PIN21, GPIO_PIN22, GPIO_PIN23, + GPIO_PIN24, GPIO_PIN25, GPIO_PIN26, GPIO_PIN27, GPIO_PIN28, GPIO_PIN29, + GPIO_PIN30, GPIO_PIN31, +}; + +/* Each pin can interrupt on one of four different events */ +enum gpio_interrupt_mode { + GPIO_IMODE_LOW_LEVEL = 0, + GPIO_IMODE_HIGH_LEVEL = 1, + GPIO_IMODE_FALLING_EDGE = 2, + GPIO_IMODE_RISING_EDGE = 3, +}; + +/* Each pin can drive with configurable current */ +enum gpio_current { + GPIO_CURRENT_2MA = 0, + GPIO_CURRENT_4MA = 1, + GPIO_CURRENT_6MA = 2, + GPIO_CURRENT_8MA = 3, +}; + +#endif /* __GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/reg.h b/arch/arm/include/asm/arch-pollux/reg.h new file mode 100644 index 0000000..fba6216 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/reg.h @@ -0,0 +1,39 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __REG_H__ +#define __REG_H__ + +/* register access and manipulation helper macros */ +#define REG8(addr) (*((volatile unsigned char *)(addr))) +#define REG16(addr) (*((volatile unsigned short *)(addr))) +#define REG32(addr) (*((volatile unsigned long *)(addr))) + +#define BIT_SET(v,b) ((v) |= (1<<(b))) +#define BIT_CLR(v,b) ((v) &= ~(1<<(b))) +#define IS_SET(v,b) ((v) & (1<<(b))) +#define IS_CLR(v,b) !((v) & (1<<(b))) + +#endif /* __REG_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/timer.h b/arch/arm/include/asm/arch-pollux/timer.h new file mode 100644 index 0000000..35a3363 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/timer.h @@ -0,0 +1,59 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __TIMER_H__ +#define __TIMER_H__ + +/* Timer base addresses */ +#define TIMER0_BASE 0xC0001800 +#define TIMER1_BASE 0xC0001880 +#define TIMER2_BASE 0xC0001900 +#define TIMER3_BASE 0xC0001980 +#define TIMER4_BASE 0xC0001A00 + +/* Timer register offsets */ +#define TMRCOUNT 0x00 +#define TMRMATCH 0x04 +#define TMRCONTROL 0x08 +#define TMRCLKENB 0x40 +#define TMRCLKGEN 0x44 + +/* Timer Control Register n (TMRCONTROLn) */ +#define LDCNT 6 +#define INTPEND 5 +#define TINTENB 4 +#define RUN 3 +#define WDENB 2 +#define SETCLK 0 + +/* Timer Clock Generation Enable Register n (TMRCLKENBn) */ +#define TCLKMODE 3 +#define TCLKGENENB 2 + +/* Timer Clock Generation Control Register n (TMRCLKGENn) */ +#define TCLKDIV 4 +#define TCLKSRCSEL 1 + +#endif /* __TIMER_H__ */ diff --git a/arch/arm/include/asm/arch-pollux/uart.h b/arch/arm/include/asm/arch-pollux/uart.h new file mode 100644 index 0000000..2b69a01 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/uart.h @@ -0,0 +1,105 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __UART_H__ +#define __UART_H__ + +/* UART base addresses */ +#define UART0_BASE 0xC0016000 +#define UART1_BASE 0xC0016080 +#define UART2_BASE 0xC0016800 +#define UART3_BASE 0xC0016880 + +/* UART register offsets */ +#define LCON 0x00 +#define UCON 0x02 +#define FCON 0x04 +#define MCON 0x06 +#define TRSTATUS 0x08 +#define ESTATUS 0x0A +#define FSTATUS 0x0C +#define MSTATUS 0x0E +#define THB 0x10 +#define RHB 0x12 +#define BRD 0x14 +#define TIMEOUTREG 0x16 +#define INTSTATUSREG 0x18 +#define UARTCLKENB 0x40 +#define UARTCLKGEN 0x44 + +/* UART register bit definitions */ + +/* LCON Register */ +#define SYNC_PENDCLR 7 +#define SIR_MODE 6 +#define PARITY_MODE 3 +#define STOPBIT 2 +#define WORD_LEN 0 + +/* UCON Register */ +#define TX_INT 9 +#define RX_INT 8 +#define RX_TIMEOUT 7 +#define RX_ERRSTATUS 6 +#define LOOPBACK_MODE 5 +#define SEND_BREAK 4 +#define TRANS_MODE 2 +#define RECEIVE_MODE 0 + +/* FCON Register */ +#define TX_FIFO_TRIGGER 6 +#define RX_FIFO_TRIGGER 4 +#define TX_FIFO_RESET 2 +#define RX_FIFO_RESET 1 +#define FIFO_EN 0 + +/* MCON Register */ +#define HALF_CH_ENB 7 +#define SCRXENB 6 +#define SCTXENB 5 +#define AFC 4 +#define DTR_ACTIVE 1 +#define RTS_ACTIVE 0 + +/* FSTATUS Register */ +#define RX_FIFO_ERROR 10 +#define TX_FIFO_FULL 9 +#define RX_FIFO_FULL 8 +#define TX_FIFO_COUNT 4 +#define RX_FIFO_COUNT 0 + +/* TRSTATUS */ +#define TRANSMITTER_EMPTY 2 +#define TRANSMIT_BUFFER_EMPTY 1 +#define RECEIVE_BUFFER_DATA_READY 0 + +/* UARTCLKENB */ +#define UARTCLKGENENB 2 + +/* UARTCLKGEN */ +#define UARTCLKDIV 4 +#define UARTCLKSRCSEL 1 + +#endif /* __UART_H__ */
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com --- drivers/serial/Makefile | 1 + drivers/serial/serial_pollux.c | 116 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_pollux.c
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile index c731bfb..87efd15 100644 --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -56,6 +56,7 @@ COBJS-$(CONFIG_S3C44B0_SERIAL) += serial_s3c44b0.o COBJS-$(CONFIG_XILINX_UARTLITE) += serial_xuartlite.o COBJS-$(CONFIG_SCIF_CONSOLE) += serial_sh.o COBJS-$(CONFIG_USB_TTY) += usbtty.o +COBJS-$(CONFIG_POLLUX_SERIAL) += serial_pollux.o
COBJS := $(sort $(COBJS-y)) SRCS := $(COBJS:.o=.c) diff --git a/drivers/serial/serial_pollux.c b/drivers/serial/serial_pollux.c new file mode 100644 index 0000000..62229dd --- /dev/null +++ b/drivers/serial/serial_pollux.c @@ -0,0 +1,116 @@ +/* (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/reg.h> +#include <asm/arch/uart.h> + +#ifndef CONFIG_CONSOLE_UART_BASE +#error "Please define CONFIG_CONSOLE_UART_BASE to a suitable UARTx_BASE" +#endif +#define UART_BASE CONFIG_CONSOLE_UART_BASE + +DECLARE_GLOBAL_DATA_PTR; + +#define DEFAULT_BRD 1 +void serial_setbrg (void) +{ + int baudrate, brd; + + if ((baudrate = gd->baudrate) <= 0) + baudrate = CONFIG_BAUDRATE; + + /* we expect that the board-specific code set up the clock source such + * that a BRD of 1 corresponds to a baudrate of 115200 bps. We use + * this fact to calculate the BRD for any baudrate. We add one bit of + * precision to the division so we can round to the best BRD. + */ + brd = ((((115200 << 1)*(DEFAULT_BRD + 1)/baudrate) + 1) >> 1) - 1; + REG16(UART_BASE + BRD) = brd; +} + +int serial_init (void) +{ + /* expect that board-specific init has setup clock source */ + + /* disable UART clock */ + REG32(UART_BASE + UARTCLKENB) &= ~(1<<UARTCLKGENENB); + + /* clear IRQ pending, set 8 bit word length */ + REG16(UART_BASE + LCON) = (1<<SYNC_PENDCLR)|(3<<WORD_LEN); + + /* enable polling/IRQ transmit and receive */ + REG16(UART_BASE + UCON) = (1<<TRANS_MODE)|(1<<RECEIVE_MODE); + + /* reset the FIFOs */ + REG16(UART_BASE + FCON) = + (1<<TX_FIFO_RESET)|(1<<RX_FIFO_RESET); + + /* enable TX */ + REG16(UART_BASE + MCON) = (1<<SCRXENB); + + /* set the baud rate */ + serial_setbrg(); + + /* enable UART clock */ + REG32(UART_BASE + UARTCLKENB) |= (1<<UARTCLKGENENB); + + return 0; +} + +void serial_putc (const char c) +{ + u16 status, ready_mask; + + ready_mask = (1<<TRANSMITTER_EMPTY)|(1<<TRANSMIT_BUFFER_EMPTY); + if(c == '\n') + serial_putc('\r'); + + while(1) { /* wait for transmitter to be ready */ + status = REG16(UART_BASE + TRSTATUS); + if(status & ready_mask) + break; + } + /* transmit */ + REG8(UART_BASE + THB) = c; +} + +void serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int serial_tstc (void) +{ + return (REG16(UART_BASE + FSTATUS) & 0xF); +} + +int serial_getc (void) +{ + while(!serial_tstc()); + return REG16(UART_BASE + RHB); +}
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com --- Makefile | 7 +++ board/didj/Makefile | 54 ++++++++++++++++++++++++ board/didj/config.mk | 1 + board/didj/didj.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/didj.h | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 240 insertions(+), 0 deletions(-) create mode 100644 board/didj/Makefile create mode 100644 board/didj/config.mk create mode 100644 board/didj/didj.c create mode 100644 include/configs/didj.h
diff --git a/Makefile b/Makefile index c26e491..04d47a6 100644 --- a/Makefile +++ b/Makefile @@ -3120,6 +3120,13 @@ voiceblue_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm925t voiceblue
######################################################################### +# pollux Systems +######################################################################### + +didj_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs didj NULL pollux + +######################################################################### ## S3C44B0 Systems #########################################################################
diff --git a/board/didj/Makefile b/board/didj/Makefile new file mode 100644 index 0000000..d320e80 --- /dev/null +++ b/board/didj/Makefile @@ -0,0 +1,54 @@ +# (C) Copyright 2010 cozybit, Inc. +# Brian Cavagnolo brian@cozybit.com +# +# Derived from versatile/Makefile: +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := didj.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/didj/config.mk b/board/didj/config.mk new file mode 100644 index 0000000..245816f --- /dev/null +++ b/board/didj/config.mk @@ -0,0 +1 @@ +TEXT_BASE = $(CONFIG_TEXT_BASE) diff --git a/board/didj/didj.c b/board/didj/didj.c new file mode 100644 index 0000000..35ba49b --- /dev/null +++ b/board/didj/didj.c @@ -0,0 +1,107 @@ +/* + * (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo, brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Andrey Yurovsky" yurovsky@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/arch/clkpwr.h> +#include <asm/arch/reg.h> +#include <asm/arch/gpio.h> +#include <asm/arch/timer.h> +#include <asm/arch/uart.h> + +#if defined(CONFIG_SHOW_BOOT_PROGRESS) +void show_boot_progress(int progress) +{ + printf("Boot reached stage %d\n", progress); +} +#endif + +/* Desired PLL1 frequency for SDRAM and UART */ +#define PLL1_FREQ 147000000 + +/* UART clock divider calculated such that the default BRD of 1 corresponds to + * a baud rate of 115200bps. This is required by the serial driver. Note that + * we calculate the divider below with an extra bit of precision to ensure that + * we round to the most suitable divider value. + */ +#define DEFAULT_BRD 1 +#define UARTDIV ((((PLL1_FREQ<<1)/(115200*(DEFAULT_BRD + 1)*16)) + 1)>>1) + +int board_init (void) +{ + + unsigned long tmp; + + icache_enable(); + + /* Didj uses PLL0 for the CPU clock at 393216000 Hz */ + REG32(PLLSETREG0) = PLL_REG(801, 55, 0); + /* PLL1 (bus clock) 147000000 Hz */ + REG32(PLLSETREG1) = PLL_REG(196, 9, 2); + + /* set bus and cpu clock source and dividers */ + tmp = REG32(CLKMODEREG); + tmp &= ~((0x3<<CLKSELCPU0)| + (0xF<<CLKDIVCPU0)| + (0xF<<CLKDIV2CPU0)| + (0x3<<CLKSELBCLK)| + (0xF<<CLKDIV1BCLK)); + tmp |= ((0<<CLKSELCPU0)| + (0<<CLKDIVCPU0)| + (2<<CLKDIV2CPU0)| + (0<<CLKSELBCLK)| + (2<<CLKDIV1BCLK)); + REG32(CLKMODEREG) = tmp; + + /* apply settings */ + BIT_SET(REG32(PWRMODE), CHGPLL); + + /* wait for PLLs to stabalize */ + while(IS_SET(REG32(PWRMODE), CHGPLL)); + + /* timer runs on PLL0 divided down by 256 */ + REG32(CONFIG_SYS_TIMERBASE + TMRCLKGEN) |= + ((256-1)<<TCLKDIV)|(0<<TCLKSRCSEL); + + /* UART0 pins can either be a UART or GPIO. We want UART. For this we + * must configure GPIOA, pin 8 to be the UART TX, which is it's + * alternative function. + */ + tmp = REG32(GPIOAALTFN0); + tmp &= ~(ALTFN0_PIN_MASK(8)); + tmp |= ALTFN0_PIN_CFG(8, GPIO_ALT1); + REG32(GPIOAALTFN0) = tmp; + + /* UART0 runs on PLL1. */ + REG32(UART0_BASE + UARTCLKGEN) = + ((1<<UARTCLKSRCSEL)|((UARTDIV - 1)<<UARTCLKDIV)); + + return 0; +} + +int dram_init (void) +{ + return 0; +} diff --git a/include/configs/didj.h b/include/configs/didj.h new file mode 100644 index 0000000..848e99d --- /dev/null +++ b/include/configs/didj.h @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2010 cozybit, Inc. + * Brian Cavagnolo brian@cozybit.com + * + * (C) Copyright 2007 Leapfrog, Inc. + * Kosta Demirev, kdemirev@yahoo.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/uart.h> +#include <asm/arch/timer.h> + +#define CONFIG_ARM926EJS + +/* didj has minimal support for now, so turn lots of stuff off */ +#define CONFIG_SYS_NO_FLASH +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SKIP_LOWLEVEL_INIT + +/* memory layout */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x02000000 +#define CONFIG_SYS_GBL_DATA_SIZE 128 +#define CONFIG_ENV_SIZE 8192 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024) +#define CONFIG_STACKSIZE (128 * 1024) +#define CONFIG_TEXT_BASE 0x00100000 +#define CONFIG_SYS_LOAD_ADDR 0x00200000 + +/* timer and clock set up */ +#define CONFIG_SYS_HZ (384000000/256) +#define CONFIG_SYS_TIMERBASE TIMER0_BASE + +/* serial port configuration */ +#define CONFIG_POLLUX_SERIAL +#define CONFIG_CONSOLE_UART_BASE UART0_BASE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* console/printing setup */ +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 + +/* SUBJECT TO AUDIT */ + +#define CONFIG_PL011_CLOCK 24000000 + +#endif /* __CONFIG_H */
Dear Brian Cavagnolo,
In message 1275417750-10020-3-git-send-email-brian@cozybit.com you wrote:
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com
You should probably be a bit more verbose. I guess few people understand what a "pollux-based leapfrog didj" might be.
Makefile | 7 +++ board/didj/Makefile | 54 ++++++++++++++++++++++++ board/didj/config.mk | 1 + board/didj/didj.c | 107 ++++++++++++++++++++++++++++++++++++++++++++++++ include/configs/didj.h | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 240 insertions(+), 0 deletions(-) create mode 100644 board/didj/Makefile create mode 100644 board/didj/config.mk create mode 100644 board/didj/didj.c create mode 100644 include/configs/didj.h
Entries to MAKEALL and MAINTAINERS missing.
diff --git a/Makefile b/Makefile index c26e491..04d47a6 100644 --- a/Makefile +++ b/Makefile @@ -3120,6 +3120,13 @@ voiceblue_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm925t voiceblue
######################################################################### +# pollux Systems +#########################################################################
+didj_config : unconfig
- @$(MKCONFIG) $(@:_config=) arm arm926ejs didj NULL pollux
Please keep lists sorted.
...
+#define UARTDIV ((((PLL1_FREQ<<1)/(115200*(DEFAULT_BRD + 1)*16)) + 1)>>1)
Line too long, please fix globally.
+int board_init (void) +{
- unsigned long tmp;
- icache_enable();
- /* Didj uses PLL0 for the CPU clock at 393216000 Hz */
- REG32(PLLSETREG0) = PLL_REG(801, 55, 0);
- /* PLL1 (bus clock) 147000000 Hz */
- REG32(PLLSETREG1) = PLL_REG(196, 9, 2);
NAK. Please use C structs with proper I/O accessors instead.
- /* UART0 pins can either be a UART or GPIO. We want UART. For this we
* must configure GPIOA, pin 8 to be the UART TX, which is it's* alternative function.*/
Incorrect multiline comment style. please fix globally.
Best regards,
Wolfgang Denk
Dear Brian Cavagnolo,
In message 1275417750-10020-2-git-send-email-brian@cozybit.com you wrote:
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com
drivers/serial/Makefile | 1 + drivers/serial/serial_pollux.c | 116 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_pollux.c
Please see previous comments about using C structs with I/O accessors, coding style etc.
General question: do we really need a new UART driver, or can this be generalized with other drivers?
Best regards,
Wolfgang Denk
On Tue, Jun 1, 2010 at 3:42 PM, Wolfgang Denk wd@denx.de wrote:
Dear Brian Cavagnolo,
In message 1275417750-10020-2-git-send-email-brian@cozybit.com you wrote:
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com
drivers/serial/Makefile | 1 + drivers/serial/serial_pollux.c | 116 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 117 insertions(+), 0 deletions(-) create mode 100644 drivers/serial/serial_pollux.c
Please see previous comments about using C structs with I/O accessors, coding style etc.
Understood.
General question: do we really need a new UART driver, or can this be generalized with other drivers?
The s3c44b0 serial hardware is quite similar to that of the pollux. There are some quirks (e.g., the pollux's registers are 16 bits and the s3c44b0's are 32), but I think there are some reasonable ways to address that. I'll use that driver in v2.
Thanks, Brian
Dear Brian Cavagnolo,
In message 1275417750-10020-1-git-send-email-brian@cozybit.com you wrote:
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com
Please be a bit more verbose - who is manufacturing this pollux thingy, who will be maintaining the code, etc.
arch/arm/cpu/arm926ejs/pollux/Makefile | 51 ++++++++ arch/arm/cpu/arm926ejs/pollux/reset.S | 49 ++++++++ arch/arm/cpu/arm926ejs/pollux/timer.c | 190 +++++++++++++++++++++++++++++
Why exactly do we need a new directory for it?
--- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/reset.S @@ -0,0 +1,49 @@
...
- .align 5
+.globl reset_cpu +reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
- b _loop_forever
+rstctl1:
- .word 0xfffece10
This seems identical to /arm/cpu/arm926ejs/omap/reset.S and arch/arm/cpu/arm926ejs/versatile/reset.S to me. Why do we need a 3rd copy of the same code?
Please factor out common code.
diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c b/arch/arm/cpu/arm926ejs/pollux/timer.c new file mode 100644 index 0000000..fc6c699 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/timer.c
...
+#ifndef CONFIG_SYS_TIMERBASE +#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE" +#endif +#define TIMERBASE CONFIG_SYS_TIMERBASE
+#define TIMER_LOAD_VAL 0xffffffff
+static ulong inline read_timer(void) +{
- REG32(TIMERBASE + TMRCONTROL) |= (1<<LDCNT);
- return REG32(TIMERBASE + TMRMATCH);
+}
We don;t allow register accesses through base address + offset any more. Please declare porper C structs and use proper I/O accessors. Please fix globally.
- if (lastdec >= now) { /* normal mode (non roll) */
/* normal mode */timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
LIne too long. Please fix globally.
- } else { /* we have overflow of the count down timer */
/* nts = ts + ld + (TLV - now)* ts=old stamp, ld=time that passed before passing through -1* (TLV-now) amount of time after passing though -1* nts = new "advancing time stamp"...it could also roll and cause problems.*/
Incorrect multiline comment style. Please fix globally.
+/* Clock and Power Control Registers */ +#define CLKPWR_BASE 0xC000F000 +#define CLKMODEREG (CLKPWR_BASE + 0x000) +#define PLLSETREG0 (CLKPWR_BASE + 0x004) +#define PLLSETREG1 (CLKPWR_BASE + 0x008) +#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040) +#define RTCWAKEUPENB (CLKPWR_BASE + 0x044) +#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048) +#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C) +#define GPIOPEND (CLKPWR_BASE + 0x050) +#define INTPENDSPAD (CLKPWR_BASE + 0x058) +#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C) +#define INTENB (CLKPWR_BASE + 0x060) +#define PWRMODE (CLKPWR_BASE + 0x07C) +#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100) +#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104) +#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108) +#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C) +#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110) +#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114) +#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118)
NAK! See above - please declare proper C structs instead.
diff --git a/arch/arm/include/asm/arch-pollux/gpio.h b/arch/arm/include/asm/arch-pollux/gpio.h new file mode 100644 index 0000000..f6ddd1b --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/gpio.h
...
+/* GPIO registers */ +#define GPIO_BASE 0xC000A000
+#define GPIOAOUT (GPIO_BASE + 0x00) +#define GPIOAOUTENB (GPIO_BASE + 0x04) +#define GPIOADETMODE0 (GPIO_BASE + 0x08) +#define GPIOADETMODE1 (GPIO_BASE + 0x0C) +#define GPIOAINTENB (GPIO_BASE + 0x10) +#define GPIOADET (GPIO_BASE + 0x14) +#define GPIOAPAD (GPIO_BASE + 0x18) +#define GPIOAPUENB (GPIO_BASE + 0x1C) +#define GPIOAALTFN0 (GPIO_BASE + 0x20) +#define GPIOAALTFN1 (GPIO_BASE + 0x24)
NAK again.
diff --git a/arch/arm/include/asm/arch-pollux/reg.h b/arch/arm/include/asm/arch-pollux/reg.h new file mode 100644 index 0000000..fba6216 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/reg.h
...
+/* register access and manipulation helper macros */ +#define REG8(addr) (*((volatile unsigned char *)(addr))) +#define REG16(addr) (*((volatile unsigned short *)(addr))) +#define REG32(addr) (*((volatile unsigned long *)(addr)))
NAK again! Please use proper I/O accessors instead.
+/* UART register offsets */ +#define LCON 0x00 +#define UCON 0x02 +#define FCON 0x04 +#define MCON 0x06 +#define TRSTATUS 0x08 +#define ESTATUS 0x0A +#define FSTATUS 0x0C +#define MSTATUS 0x0E +#define THB 0x10 +#define RHB 0x12 +#define BRD 0x14 +#define TIMEOUTREG 0x16 +#define INTSTATUSREG 0x18 +#define UARTCLKENB 0x40 +#define UARTCLKGEN 0x44
Is this really such a new UART that we need new code for it?
Best regards,
Wolfgang Denk
On Tue, Jun 1, 2010 at 3:38 PM, Wolfgang Denk wd@denx.de wrote:
Dear Brian Cavagnolo,
In message 1275417750-10020-1-git-send-email-brian@cozybit.com you wrote:
Signed-off-by: Brian Cavagnolo brian@cozybit.com Signed-off-by: Andrey Yurovsky yurovsky@gmail.com
Please be a bit more verbose - who is manufacturing this pollux thingy, who will be maintaining the code, etc.
arch/arm/cpu/arm926ejs/pollux/Makefile | 51 ++++++++ arch/arm/cpu/arm926ejs/pollux/reset.S | 49 ++++++++ arch/arm/cpu/arm926ejs/pollux/timer.c | 190 +++++++++++++++++++++++++++++
Why exactly do we need a new directory for it?
This appears to be the convention in the source tree and it seems straightforward and clean. Is there a different preferred way to add new CPUs?
I understand your other comments.
Thanks, Brian
--- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/reset.S @@ -0,0 +1,49 @@
...
- .align 5
+.globl reset_cpu +reset_cpu:
- ldr r1, rstctl1 /* get clkm1 reset ctl */
- mov r3, #0x0
- strh r3, [r1] /* clear it */
- mov r3, #0x8
- strh r3, [r1] /* force dsp+arm reset */
+_loop_forever:
- b _loop_forever
+rstctl1:
- .word 0xfffece10
This seems identical to /arm/cpu/arm926ejs/omap/reset.S and arch/arm/cpu/arm926ejs/versatile/reset.S to me. Why do we need a 3rd copy of the same code?
Please factor out common code.
diff --git a/arch/arm/cpu/arm926ejs/pollux/timer.c b/arch/arm/cpu/arm926ejs/pollux/timer.c new file mode 100644 index 0000000..fc6c699 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/pollux/timer.c
...
+#ifndef CONFIG_SYS_TIMERBASE +#error "Please define CONFIG_SYS_TIMERBASE to a suitable TIMERx_BASE" +#endif +#define TIMERBASE CONFIG_SYS_TIMERBASE
+#define TIMER_LOAD_VAL 0xffffffff
+static ulong inline read_timer(void) +{
- REG32(TIMERBASE + TMRCONTROL) |= (1<<LDCNT);
- return REG32(TIMERBASE + TMRMATCH);
+}
We don;t allow register accesses through base address + offset any more. Please declare porper C structs and use proper I/O accessors. Please fix globally.
- if (lastdec >= now) { /* normal mode (non roll) */
- /* normal mode */
- timestamp += lastdec - now; /* move stamp fordward with absoulte diff ticks */
LIne too long. Please fix globally.
- } else { /* we have overflow of the count down timer */
- /* nts = ts + ld + (TLV - now)
- * ts=old stamp, ld=time that passed before passing through -1
- * (TLV-now) amount of time after passing though -1
- * nts = new "advancing time stamp"...it could also roll and cause problems.
- */
Incorrect multiline comment style. Please fix globally.
+/* Clock and Power Control Registers */ +#define CLKPWR_BASE 0xC000F000 +#define CLKMODEREG (CLKPWR_BASE + 0x000) +#define PLLSETREG0 (CLKPWR_BASE + 0x004) +#define PLLSETREG1 (CLKPWR_BASE + 0x008) +#define GPIOWAKEUPENB (CLKPWR_BASE + 0x040) +#define RTCWAKEUPENB (CLKPWR_BASE + 0x044) +#define GPIOWAKEUPRISEENB (CLKPWR_BASE + 0x048) +#define GPIOWAKEUPFALLENB (CLKPWR_BASE + 0x04C) +#define GPIOPEND (CLKPWR_BASE + 0x050) +#define INTPENDSPAD (CLKPWR_BASE + 0x058) +#define PWRRSTSTATUS (CLKPWR_BASE + 0x05C) +#define INTENB (CLKPWR_BASE + 0x060) +#define PWRMODE (CLKPWR_BASE + 0x07C) +#define PADSTRENGTHGPIOAL (CLKPWR_BASE + 0x100) +#define PADSTRENGTHGPIOAH (CLKPWR_BASE + 0x104) +#define PADSTRENGTHGPIOBL (CLKPWR_BASE + 0x108) +#define PADSTRENGTHGPIOBH (CLKPWR_BASE + 0x10C) +#define PADSTRENGTHGPIOCL (CLKPWR_BASE + 0x110) +#define PADSTRENGTHGPIOCH (CLKPWR_BASE + 0x114) +#define PADSTRENGTHBUS (CLKPWR_BASE + 0x118)
NAK! See above - please declare proper C structs instead.
diff --git a/arch/arm/include/asm/arch-pollux/gpio.h b/arch/arm/include/asm/arch-pollux/gpio.h new file mode 100644 index 0000000..f6ddd1b --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/gpio.h
...
+/* GPIO registers */ +#define GPIO_BASE 0xC000A000
+#define GPIOAOUT (GPIO_BASE + 0x00) +#define GPIOAOUTENB (GPIO_BASE + 0x04) +#define GPIOADETMODE0 (GPIO_BASE + 0x08) +#define GPIOADETMODE1 (GPIO_BASE + 0x0C) +#define GPIOAINTENB (GPIO_BASE + 0x10) +#define GPIOADET (GPIO_BASE + 0x14) +#define GPIOAPAD (GPIO_BASE + 0x18) +#define GPIOAPUENB (GPIO_BASE + 0x1C) +#define GPIOAALTFN0 (GPIO_BASE + 0x20) +#define GPIOAALTFN1 (GPIO_BASE + 0x24)
NAK again.
diff --git a/arch/arm/include/asm/arch-pollux/reg.h b/arch/arm/include/asm/arch-pollux/reg.h new file mode 100644 index 0000000..fba6216 --- /dev/null +++ b/arch/arm/include/asm/arch-pollux/reg.h
...
+/* register access and manipulation helper macros */ +#define REG8(addr) (*((volatile unsigned char *)(addr))) +#define REG16(addr) (*((volatile unsigned short *)(addr))) +#define REG32(addr) (*((volatile unsigned long *)(addr)))
NAK again! Please use proper I/O accessors instead.
+/* UART register offsets */ +#define LCON 0x00 +#define UCON 0x02 +#define FCON 0x04 +#define MCON 0x06 +#define TRSTATUS 0x08 +#define ESTATUS 0x0A +#define FSTATUS 0x0C +#define MSTATUS 0x0E +#define THB 0x10 +#define RHB 0x12 +#define BRD 0x14 +#define TIMEOUTREG 0x16 +#define INTSTATUSREG 0x18 +#define UARTCLKENB 0x40 +#define UARTCLKGEN 0x44
Is this really such a new UART that we need new code for it?
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de How much net work could a network work, if a network could net work?
participants (2)
-
Brian Cavagnolo -
Wolfgang Denk