On LD4 SoC or later, the pin-mux registers are 8bit wide, while 4bit wide on sLD3 SoC. Support it for the sLD3 pinctrl driver.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 20 ++++++++------------ drivers/pinctrl/uniphier/pinctrl-uniphier.h | 5 +++-- 2 files changed, 11 insertions(+), 14 deletions(-)

diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index f2fe313..51144b8 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -105,8 +105,10 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, int muxval) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); - unsigned mux_bits, reg_stride, reg, reg_end, shift, mask; - bool load_pinctrl; + unsigned reg, reg_end, shift, mask; + unsigned mux_bits = 8; + unsigned reg_stride = 4; + bool load_pinctrl = false; u32 tmp;

/* some pins need input-enabling */ @@ -115,24 +117,18 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, if (muxval < 0) return; /* dedicated pin; nothing to do for pin-mux */

+ if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_MUX_4BIT) + mux_bits = 4; + if (priv->socdata->caps & UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE) { /* * Mode offset bit * Normal 4 * n shift+3:shift * Debug 4 * n shift+7:shift+4 */ - mux_bits = 4; + mux_bits /= 2; reg_stride = 8; load_pinctrl = true; - } else { - /* - * Mode offset bit - * Normal 8 * n shift+3:shift - * Debug 8 * n + 4 shift+3:shift - */ - mux_bits = 8; - reg_stride = 4; - load_pinctrl = false; }

reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 76ea1be..5c3db2a 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -67,8 +67,9 @@ struct uniphier_pinctrl_socdata { const char * const *functions; int functions_count; unsigned caps; -#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(1) -#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(0) +#define UNIPHIER_PINCTRL_CAPS_PERPIN_IECTRL BIT(2) +#define UNIPHIER_PINCTRL_CAPS_DBGMUX_SEPARATE BIT(1) +#define UNIPHIER_PINCTRL_CAPS_MUX_4BIT BIT(0) };

#define UNIPHIER_PINCTRL_PIN(a, b) \

DT-side updates to make pinctrl on sLD3 SoC really available.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/dts/uniphier-ph1-sld3-ref.dts | 8 ++++++++ arch/arm/dts/uniphier-ph1-sld3.dtsi | 35 ++++++++++++++++++++++++++++++++++ 2 files changed, 43 insertions(+)

diff --git a/arch/arm/dts/uniphier-ph1-sld3-ref.dts b/arch/arm/dts/uniphier-ph1-sld3-ref.dts index 0863588..f3e76b3 100644 --- a/arch/arm/dts/uniphier-ph1-sld3-ref.dts +++ b/arch/arm/dts/uniphier-ph1-sld3-ref.dts @@ -93,3 +93,11 @@ &emmc { u-boot,dm-pre-reloc; }; + +&pinctrl_uart0 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_emmc { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/uniphier-ph1-sld3.dtsi b/arch/arm/dts/uniphier-ph1-sld3.dtsi index 6a95541..d8c44b7 100644 --- a/arch/arm/dts/uniphier-ph1-sld3.dtsi +++ b/arch/arm/dts/uniphier-ph1-sld3.dtsi @@ -90,6 +90,8 @@ status = "disabled"; reg = <0x54006800 0x40>; interrupts = <0 33 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -99,6 +101,8 @@ status = "disabled"; reg = <0x54006900 0x40>; interrupts = <0 35 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -108,6 +112,8 @@ status = "disabled"; reg = <0x54006a00 0x40>; interrupts = <0 37 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; clocks = <&uart_clk>; clock-frequency = <36864000>; }; @@ -231,6 +237,8 @@ #address-cells = <1>; #size-cells = <0>; interrupts = <0 41 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; clocks = <&iobus_clk>; clock-frequency = <100000>; }; @@ -304,6 +312,9 @@ status = "disabled"; reg = <0x5a400000 0x200>; interrupts = <0 78 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_emmc>; + pinctrl-1 = <&pinctrl_emmc_1v8>; clocks = <&mio 1>; bus-width = <8>; non-removable; @@ -314,6 +325,9 @@ status = "disabled"; reg = <0x5a500000 0x200>; interrupts = <0 76 4>; + pinctrl-names = "default", "1.8v"; + pinctrl-0 = <&pinctrl_sd>; + pinctrl-1 = <&pinctrl_sd_1v8>; clocks = <&mio 0>; bus-width = <4>; }; @@ -323,6 +337,8 @@ status = "disabled"; reg = <0x5a800100 0x100>; interrupts = <0 80 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb0>; clocks = <&mio 3>, <&mio 6>; };

@@ -331,6 +347,8 @@ status = "disabled"; reg = <0x5a810100 0x100>; interrupts = <0 81 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1>; clocks = <&mio 4>, <&mio 6>; };

@@ -339,6 +357,8 @@ status = "disabled"; reg = <0x5a820100 0x100>; interrupts = <0 82 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2>; clocks = <&mio 5>, <&mio 6>; };

@@ -347,9 +367,22 @@ status = "disabled"; reg = <0x5a830100 0x100>; interrupts = <0 83 4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3>; clocks = <&mio 7>, <&mio 6>; };

+ soc-glue@5f800000 { + compatible = "simple-mfd", "syscon"; + reg = <0x5f800000 0x2000>; + u-boot,dm-pre-reloc; + + pinctrl: pinctrl { + compatible = "socionext,uniphier-sld3-pinctrl"; + u-boot,dm-pre-reloc; + }; + }; + aidet@f1830000 { compatible = "simple-mfd", "syscon"; reg = <0xf1830000 0x200>; @@ -370,3 +403,5 @@ }; }; }; + +/include/ "uniphier-pinctrl.dtsi"

This is enabled by default for all the supported boot modes.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c | 2 -- 1 file changed, 2 deletions(-)

diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c index 6c5d58f..22c07fb 100644 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c +++ b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-sld3.c @@ -22,7 +22,5 @@ int uniphier_sld3_early_pin_init(const struct uniphier_board_data *bd) sg_set_pinsel(102, 2, 4, 4); /* TXD2 */ #endif

- sg_set_pinsel(99, 1, 4, 4); /* GPIO26 -> EA24 */ - return 0; }

The NAND subsystem has not supported the Driver Model yet, but the NAND pin-mux data are already in the pinctrl drivers. Use them by calling pinctrl_generic_set_state() directly.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/Makefile | 1 + arch/arm/mach-uniphier/board_init.c | 24 ++++++++++++----- arch/arm/mach-uniphier/init.h | 8 +----- arch/arm/mach-uniphier/pinctrl-glue.c | 32 +++++++++++++++++++++++ arch/arm/mach-uniphier/pinctrl/Makefile | 7 ----- arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c | 19 -------------- arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c | 35 ------------------------- arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c | 35 ------------------------- arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c | 37 --------------------------- arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c | 37 --------------------------- arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c | 35 ------------------------- arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c | 20 --------------- arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c | 35 ------------------------- 13 files changed, 51 insertions(+), 274 deletions(-) create mode 100644 arch/arm/mach-uniphier/pinctrl-glue.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c delete mode 100644 arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 1fe5199..af56d6f 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -23,6 +23,7 @@ obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ obj-y += dram/ +obj-y += pinctrl-glue.o

obj-$(CONFIG_MICRO_SUPPORT_CARD) += micro-support-card.o obj-$(CONFIG_DEBUG_UART_UNIPHIER) += debug-uart/ diff --git a/arch/arm/mach-uniphier/board_init.c b/arch/arm/mach-uniphier/board_init.c index 6bf35ee..228092c 100644 --- a/arch/arm/mach-uniphier/board_init.c +++ b/arch/arm/mach-uniphier/board_init.c @@ -47,6 +47,14 @@ static void uniphier_setup_xirq(void) writel(tmp, 0x55000090); }

+static void uniphier_nand_pin_init(bool cs2) +{ +#ifdef CONFIG_NAND_DENALI + if (uniphier_pin_init(cs2 ? "nand2cs_grp" : "nand_grp")) + pr_err("failed to init NAND pins\n"); +#endif +} + int board_init(void) { led_puts("U0"); @@ -54,55 +62,56 @@ int board_init(void) switch (uniphier_get_soc_type()) { #if defined(CONFIG_ARCH_UNIPHIER_SLD3) case SOC_UNIPHIER_SLD3: - uniphier_sld3_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD4) case SOC_UNIPHIER_LD4: - uniphier_ld4_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO4) case SOC_UNIPHIER_PRO4: - uniphier_pro4_pin_init(); + uniphier_nand_pin_init(false); led_puts("U1"); uniphier_pro4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_SLD8) case SOC_UNIPHIER_SLD8: - uniphier_sld8_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_ld4_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PRO5) case SOC_UNIPHIER_PRO5: - uniphier_pro5_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pro5_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_PXS2) case SOC_UNIPHIER_PXS2: - uniphier_pxs2_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pxs2_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD6B) case SOC_UNIPHIER_LD6B: - uniphier_ld6b_pin_init(); + uniphier_nand_pin_init(true); led_puts("U1"); uniphier_pxs2_clk_init(); break; #endif #if defined(CONFIG_ARCH_UNIPHIER_LD11) case SOC_UNIPHIER_LD11: + uniphier_nand_pin_init(false); uniphier_ld20_pin_init(); led_puts("U1"); uniphier_ld11_clk_init(); @@ -110,6 +119,7 @@ int board_init(void) #endif #if defined(CONFIG_ARCH_UNIPHIER_LD20) case SOC_UNIPHIER_LD20: + uniphier_nand_pin_init(false); uniphier_ld20_pin_init(); led_puts("U1"); uniphier_ld20_clk_init(); diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 6b20784..27b9a38 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -103,13 +103,6 @@ int uniphier_pxs2_umc_init(const struct uniphier_board_data *bd); int uniphier_ld20_umc_init(const struct uniphier_board_data *bd); int uniphier_ld11_umc_init(const struct uniphier_board_data *bd);

-void uniphier_sld3_pin_init(void); -void uniphier_ld4_pin_init(void); -void uniphier_pro4_pin_init(void); -void uniphier_sld8_pin_init(void); -void uniphier_pro5_pin_init(void); -void uniphier_pxs2_pin_init(void); -void uniphier_ld6b_pin_init(void); void uniphier_ld20_pin_init(void);

void uniphier_ld4_clk_init(void); @@ -119,6 +112,7 @@ void uniphier_pxs2_clk_init(void); void uniphier_ld11_clk_init(void); void uniphier_ld20_clk_init(void);

+int uniphier_pin_init(const char *pinconfig_name); void uniphier_smp_kick_all_cpus(void); void cci500_init(int nr_slaves);

diff --git a/arch/arm/mach-uniphier/pinctrl-glue.c b/arch/arm/mach-uniphier/pinctrl-glue.c new file mode 100644 index 0000000..48549e3 --- /dev/null +++ b/arch/arm/mach-uniphier/pinctrl-glue.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2016 Socionext Inc. + * Author: Masahiro Yamada yamada.masahiro@socionext.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <linux/err.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <dm/uclass.h> + +#include "init.h" + +int uniphier_pin_init(const char *pinconfig_name) +{ + struct udevice *pctldev, *config, *next; + int ret; + + ret = uclass_first_device(UCLASS_PINCTRL, &pctldev); + if (ret) + return ret; + + device_foreach_child_safe(config, next, pctldev) { + if (strcmp(config->name, pinconfig_name)) + continue; + + return pinctrl_generic_set_state(pctldev, config); + } + + return -ENODEV; +} diff --git a/arch/arm/mach-uniphier/pinctrl/Makefile b/arch/arm/mach-uniphier/pinctrl/Makefile index 7f4d9f7..4ee9553 100644 --- a/arch/arm/mach-uniphier/pinctrl/Makefile +++ b/arch/arm/mach-uniphier/pinctrl/Makefile @@ -2,12 +2,5 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pinctrl-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pinctrl-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pinctrl-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pinctrl-sld8.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += pinctrl-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += pinctrl-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += pinctrl-ld6b.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += pinctrl-ld20.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c index ec4c414..e1cb90a 100644 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c +++ b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld20.c @@ -13,25 +13,6 @@ void uniphier_ld20_pin_init(void) { /* Comment format: PAD Name -> Function Name */

-#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(3, 0, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(4, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(5, 0, 8, 4); /* NFRYBY0 -> NFRYBY0 */ - sg_set_pinsel(6, 0, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(7, 0, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(8, 0, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(9, 0, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(10, 0, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(11, 0, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(12, 0, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(13, 0, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(14, 0, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(15, 0, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(16, 0, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(17, 0, 8, 4); /* NFD7 -> NFD7 */ - sg_set_iectrl_range(3, 17); -#endif - sg_set_pinsel(149, 14, 8, 4); /* XIRQ0 -> XIRQ0 */ sg_set_iectrl(149); sg_set_pinsel(153, 14, 8, 4); /* XIRQ4 -> XIRQ4 */ diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c deleted file mode 100644 index 7ff85b6..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld4.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_ld4_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(158, 0, 8, 4); /* XNFRE -> XNFRE_GB */ - sg_set_pinsel(159, 0, 8, 4); /* XNFWE -> XNFWE_GB */ - sg_set_pinsel(160, 0, 8, 4); /* XFALE -> NFALE_GB */ - sg_set_pinsel(161, 0, 8, 4); /* XFCLE -> NFCLE_GB */ - sg_set_pinsel(162, 0, 8, 4); /* XNFWP -> XFNWP_GB */ - sg_set_pinsel(163, 0, 8, 4); /* XNFCE0 -> XNFCE0_GB */ - sg_set_pinsel(164, 0, 8, 4); /* NANDRYBY0 -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* MMCCLK -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* MMCCMD -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* MMCDAT0 -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* MMCDAT1 -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* MMCDAT2 -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* MMCDAT3 -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* MMCDAT4 -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* MMCDAT5 -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* MMCDAT6 -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* MMCDAT7 -> NFD7_GB */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c deleted file mode 100644 index f3b7115..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-ld6b.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_ld6b_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(30, 0, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(31, 0, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(32, 0, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(33, 0, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(34, 0, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(35, 0, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(36, 0, 8, 4); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(37, 0, 8, 4); /* XNFCE1 -> NRYBY1 */ - sg_set_pinsel(38, 0, 8, 4); /* NRYBY1 -> XNFCE1 */ - sg_set_pinsel(39, 0, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(40, 0, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(41, 0, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(42, 0, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(43, 0, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(44, 0, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(45, 0, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(46, 0, 8, 4); /* NFD7 -> NFD7 */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c deleted file mode 100644 index 871d3ef..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro4.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pro4_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(40, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(41, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(42, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(43, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(44, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(45, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(46, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(47, 0, 4, 8); /* NFD7 -> NFD7 */ - sg_set_pinsel(48, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(49, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(50, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(51, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(52, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(53, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(54, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - /* sg_set_pinsel(131, 1, 4, 8); */ /* RXD2 -> NRYBY1 */ - /* sg_set_pinsel(132, 1, 4, 8); */ /* TXD2 -> XNFCE1 */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c deleted file mode 100644 index 58dff18..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pro5.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pro5_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(19, 0, 4, 8); /* XNFRE -> XNFRE */ - sg_set_pinsel(20, 0, 4, 8); /* XNFWE -> XNFWE */ - sg_set_pinsel(21, 0, 4, 8); /* NFALE -> NFALE */ - sg_set_pinsel(22, 0, 4, 8); /* NFCLE -> NFCLE */ - sg_set_pinsel(23, 0, 4, 8); /* XNFWP -> XNFWP */ - sg_set_pinsel(24, 0, 4, 8); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(25, 0, 4, 8); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(26, 0, 4, 8); /* XNFCE1 -> XNFCE1 */ - sg_set_pinsel(27, 0, 4, 8); /* NRYBY1 -> NRYBY1 */ - sg_set_pinsel(28, 0, 4, 8); /* NFD0 -> NFD0 */ - sg_set_pinsel(29, 0, 4, 8); /* NFD1 -> NFD1 */ - sg_set_pinsel(30, 0, 4, 8); /* NFD2 -> NFD2 */ - sg_set_pinsel(31, 0, 4, 8); /* NFD3 -> NFD3 */ - sg_set_pinsel(32, 0, 4, 8); /* NFD4 -> NFD4 */ - sg_set_pinsel(33, 0, 4, 8); /* NFD5 -> NFD5 */ - sg_set_pinsel(34, 0, 4, 8); /* NFD6 -> NFD6 */ - sg_set_pinsel(35, 0, 4, 8); /* NFD7 -> NFD7 */ -#endif - - writel(1, SG_LOADPINCTRL); -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c deleted file mode 100644 index fc59205..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-pxs2.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_pxs2_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(30, 8, 8, 4); /* XNFRE -> XNFRE */ - sg_set_pinsel(31, 8, 8, 4); /* XNFWE -> XNFWE */ - sg_set_pinsel(32, 8, 8, 4); /* NFALE -> NFALE */ - sg_set_pinsel(33, 8, 8, 4); /* NFCLE -> NFCLE */ - sg_set_pinsel(34, 8, 8, 4); /* XNFWP -> XNFWP */ - sg_set_pinsel(35, 8, 8, 4); /* XNFCE0 -> XNFCE0 */ - sg_set_pinsel(36, 8, 8, 4); /* NRYBY0 -> NRYBY0 */ - sg_set_pinsel(37, 8, 8, 4); /* XNFCE1 -> NRYBY1 */ - sg_set_pinsel(38, 8, 8, 4); /* NRYBY1 -> XNFCE1 */ - sg_set_pinsel(39, 8, 8, 4); /* NFD0 -> NFD0 */ - sg_set_pinsel(40, 8, 8, 4); /* NFD1 -> NFD1 */ - sg_set_pinsel(41, 8, 8, 4); /* NFD2 -> NFD2 */ - sg_set_pinsel(42, 8, 8, 4); /* NFD3 -> NFD3 */ - sg_set_pinsel(43, 8, 8, 4); /* NFD4 -> NFD4 */ - sg_set_pinsel(44, 8, 8, 4); /* NFD5 -> NFD5 */ - sg_set_pinsel(45, 8, 8, 4); /* NFD6 -> NFD6 */ - sg_set_pinsel(46, 8, 8, 4); /* NFD7 -> NFD7 */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c deleted file mode 100644 index 16563f9..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld3.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_sld3_pin_init(void) -{ -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(38, 1, 4, 4); /* NFALE_GB, NFCLE_GB */ - sg_set_pinsel(39, 1, 4, 4); /* XNFRYBY0_GB */ - sg_set_pinsel(40, 1, 4, 4); /* XNFCE0_GB, XNFRE_GB, XNFWE_GB, XNFWP_GB */ - sg_set_pinsel(41, 1, 4, 4); /* XNFRYBY1_GB, XNFCE1_GB */ - sg_set_pinsel(58, 1, 4, 4); /* NFD[0-3]_GB */ - sg_set_pinsel(59, 1, 4, 4); /* NFD[4-7]_GB */ -#endif -} diff --git a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c b/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c deleted file mode 100644 index 1c97c8b..0000000 --- a/arch/arm/mach-uniphier/pinctrl/pinctrl-sld8.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2011-2015 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <linux/io.h> - -#include "../init.h" -#include "../sg-regs.h" - -void uniphier_sld8_pin_init(void) -{ - /* Comment format: PAD Name -> Function Name */ - -#ifdef CONFIG_NAND_DENALI - sg_set_pinsel(15, 0, 8, 4); /* XNFRE_GB -> XNFRE_GB */ - sg_set_pinsel(16, 0, 8, 4); /* XNFWE_GB -> XNFWE_GB */ - sg_set_pinsel(17, 0, 8, 4); /* XFALE_GB -> NFALE_GB */ - sg_set_pinsel(18, 0, 8, 4); /* XFCLE_GB -> NFCLE_GB */ - sg_set_pinsel(19, 0, 8, 4); /* XNFWP_GB -> XFNWP_GB */ - sg_set_pinsel(20, 0, 8, 4); /* XNFCE0_GB -> XNFCE0_GB */ - sg_set_pinsel(21, 0, 8, 4); /* NANDRYBY0_GB -> NANDRYBY0_GB */ - sg_set_pinsel(22, 0, 8, 4); /* XFNCE1_GB -> XFNCE1_GB */ - sg_set_pinsel(23, 0, 8, 4); /* NANDRYBY1_GB -> NANDRYBY1_GB */ - sg_set_pinsel(24, 0, 8, 4); /* NFD0_GB -> NFD0_GB */ - sg_set_pinsel(25, 0, 8, 4); /* NFD1_GB -> NFD1_GB */ - sg_set_pinsel(26, 0, 8, 4); /* NFD2_GB -> NFD2_GB */ - sg_set_pinsel(27, 0, 8, 4); /* NFD3_GB -> NFD3_GB */ - sg_set_pinsel(28, 0, 8, 4); /* NFD4_GB -> NFD4_GB */ - sg_set_pinsel(29, 0, 8, 4); /* NFD5_GB -> NFD5_GB */ - sg_set_pinsel(30, 0, 8, 4); /* NFD6_GB -> NFD6_GB */ - sg_set_pinsel(31, 0, 8, 4); /* NFD7_GB -> NFD7_GB */ -#endif -}

Use the pin-mux data in the pinctrl drivers by directly calling pinctrl_generic_set_state().

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/Makefile | 2 +- arch/arm/mach-uniphier/early-pinctrl/Makefile | 6 ---- .../early-pinctrl/early-pinctrl-ld20.c | 32 ---------------------- arch/arm/mach-uniphier/init.h | 2 -- arch/arm/mach-uniphier/init/init-ld11.c | 2 +- arch/arm/mach-uniphier/init/init-ld20.c | 2 +- 6 files changed, 3 insertions(+), 43 deletions(-) delete mode 100644 arch/arm/mach-uniphier/early-pinctrl/Makefile delete mode 100644 arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index af56d6f..df6888f 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -4,7 +4,7 @@

ifdef CONFIG_SPL_BUILD

-obj-y += init/ bcu/ memconf/ pll/ early-clk/ early-pinctrl/ +obj-y += init/ bcu/ memconf/ pll/ early-clk/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/

else diff --git a/arch/arm/mach-uniphier/early-pinctrl/Makefile b/arch/arm/mach-uniphier/early-pinctrl/Makefile deleted file mode 100644 index 84040c6..0000000 --- a/arch/arm/mach-uniphier/early-pinctrl/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-pinctrl-ld20.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-pinctrl-ld20.o diff --git a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c b/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c deleted file mode 100644 index 537deaf..0000000 --- a/arch/arm/mach-uniphier/early-pinctrl/early-pinctrl-ld20.c +++ /dev/null @@ -1,32 +0,0 @@ -/* - * Copyright (C) 2016 Masahiro Yamada yamada.masahiro@socionext.com - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "../init.h" -#include "../sg-regs.h" - -int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd) -{ - /* Comment format: PAD Name -> Function Name */ - sg_set_pinsel(0, 0, 8, 4); /* XECS1 -> XECS1 */ - sg_set_pinsel(1, 0, 8, 4); /* ERXW -> ERXW */ - sg_set_pinsel(2, 0, 8, 4); /* XERWE1 -> XERWE1 */ - sg_set_pinsel(6, 2, 8, 4); /* XNFRE -> XERWE0 */ - sg_set_pinsel(7, 2, 8, 4); /* XNFWE -> ES0 */ - sg_set_pinsel(8, 2, 8, 4); /* NFALE -> ES1 */ - sg_set_pinsel(9, 2, 8, 4); /* NFCLE -> ES2 */ - sg_set_pinsel(10, 2, 8, 4); /* NFD0 -> ED0 */ - sg_set_pinsel(11, 2, 8, 4); /* NFD1 -> ED1 */ - sg_set_pinsel(12, 2, 8, 4); /* NFD2 -> ED2 */ - sg_set_pinsel(13, 2, 8, 4); /* NFD3 -> ED3 */ - sg_set_pinsel(14, 2, 8, 4); /* NFD4 -> ED4 */ - sg_set_pinsel(15, 2, 8, 4); /* NFD5 -> ED5 */ - sg_set_pinsel(16, 2, 8, 4); /* NFD6 -> ED6 */ - sg_set_pinsel(17, 2, 8, 4); /* NFD7 -> ED7 */ - sg_set_iectrl_range(0, 2); - sg_set_iectrl_range(6, 17); - - return 0; -} diff --git a/arch/arm/mach-uniphier/init.h b/arch/arm/mach-uniphier/init.h index 27b9a38..bc524a1 100644 --- a/arch/arm/mach-uniphier/init.h +++ b/arch/arm/mach-uniphier/init.h @@ -94,8 +94,6 @@ int uniphier_pxs2_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld11_early_clk_init(const struct uniphier_board_data *bd); int uniphier_ld20_early_clk_init(const struct uniphier_board_data *bd);

-int uniphier_ld20_early_pin_init(const struct uniphier_board_data *bd); - int uniphier_ld4_umc_init(const struct uniphier_board_data *bd); int uniphier_pro4_umc_init(const struct uniphier_board_data *bd); int uniphier_sld8_umc_init(const struct uniphier_board_data *bd); diff --git a/arch/arm/mach-uniphier/init/init-ld11.c b/arch/arm/mach-uniphier/init/init-ld11.c index de2dc62..758df8d 100644 --- a/arch/arm/mach-uniphier/init/init-ld11.c +++ b/arch/arm/mach-uniphier/init/init-ld11.c @@ -15,7 +15,7 @@ int uniphier_ld11_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_ld20_early_pin_init(bd); + uniphier_pin_init("system_bus_grp");

support_card_reset();

diff --git a/arch/arm/mach-uniphier/init/init-ld20.c b/arch/arm/mach-uniphier/init/init-ld20.c index 7f66053..f23ca09 100644 --- a/arch/arm/mach-uniphier/init/init-ld20.c +++ b/arch/arm/mach-uniphier/init/init-ld20.c @@ -14,7 +14,7 @@ int uniphier_ld20_init(const struct uniphier_board_data *bd) { uniphier_sbc_init_savepin(bd); uniphier_pxs2_sbc_init(bd); - uniphier_ld20_early_pin_init(bd); + uniphier_pin_init("system_bus_grp");

support_card_reset();

Basically, this should not be configured by users.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/pll/pll-init-sld8.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/pll/pll-init-sld8.c index b26106e..8b6a67c 100644 --- a/arch/arm/mach-uniphier/pll/pll-init-sld8.c +++ b/arch/arm/mach-uniphier/pll/pll-init-sld8.c @@ -36,7 +36,7 @@ static void dpll_init(void) */ tmp = readl(SC_DPLLCTRL); tmp &= ~0x3ff07fff; -#ifdef CONFIG_DPLL_SSC_RATE_1PER +#ifdef DPLL_SSC_RATE_1PER tmp |= 0x084018bf; #else tmp |= 0x084031a6;

Now PLLs for DRAM controller are initialized in SPL, and the others in U-Boot proper. Setting up all of them in a single directory will be helpful when we want to share code between SPL and U-Boot proper.

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/Makefile | 5 ++--- arch/arm/mach-uniphier/clk/Makefile | 16 ++++++++++++++++ .../mach-uniphier/{pll/pll-init-ld4.c => clk/dpll-ld4.c} | 0 .../{pll/pll-init-pro4.c => clk/dpll-pro4.c} | 0 .../{pll/pll-init-sld3.c => clk/dpll-sld3.c} | 0 .../{pll/pll-init-sld8.c => clk/dpll-sld8.c} | 0 .../mach-uniphier/{early-clk => clk}/early-clk-ld11.c | 0 .../mach-uniphier/{early-clk => clk}/early-clk-ld20.c | 0 .../arm/mach-uniphier/{early-clk => clk}/early-clk-ld4.c | 0 .../mach-uniphier/{early-clk => clk}/early-clk-pro5.c | 0 .../mach-uniphier/{early-clk => clk}/early-clk-pxs2.c | 0 arch/arm/mach-uniphier/early-clk/Makefile | 13 ------------- arch/arm/mach-uniphier/pll/Makefile | 8 -------- 13 files changed, 18 insertions(+), 24 deletions(-) rename arch/arm/mach-uniphier/{pll/pll-init-ld4.c => clk/dpll-ld4.c} (100%) rename arch/arm/mach-uniphier/{pll/pll-init-pro4.c => clk/dpll-pro4.c} (100%) rename arch/arm/mach-uniphier/{pll/pll-init-sld3.c => clk/dpll-sld3.c} (100%) rename arch/arm/mach-uniphier/{pll/pll-init-sld8.c => clk/dpll-sld8.c} (100%) rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld11.c (100%) rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld20.c (100%) rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-ld4.c (100%) rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-pro5.c (100%) rename arch/arm/mach-uniphier/{early-clk => clk}/early-clk-pxs2.c (100%) delete mode 100644 arch/arm/mach-uniphier/early-clk/Makefile delete mode 100644 arch/arm/mach-uniphier/pll/Makefile

diff --git a/arch/arm/mach-uniphier/Makefile b/arch/arm/mach-uniphier/Makefile index 548cfe7..ae78548 100644 --- a/arch/arm/mach-uniphier/Makefile +++ b/arch/arm/mach-uniphier/Makefile @@ -4,7 +4,7 @@

ifdef CONFIG_SPL_BUILD

-obj-y += init/ bcu/ memconf/ pll/ early-clk/ +obj-y += init/ bcu/ memconf/ obj-$(CONFIG_MICRO_SUPPORT_CARD) += sbc/

else @@ -15,13 +15,12 @@ obj-y += board_init.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-y += reset.o

-obj-y += clk/ - endif

obj-y += boards.o obj-y += soc_info.o obj-y += boot-mode/ +obj-y += clk/ obj-y += dram/ obj-y += pinctrl-glue.o

diff --git a/arch/arm/mach-uniphier/clk/Makefile b/arch/arm/mach-uniphier/clk/Makefile index b722781..233e659 100644 --- a/arch/arm/mach-uniphier/clk/Makefile +++ b/arch/arm/mach-uniphier/clk/Makefile @@ -2,6 +2,20 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifdef CONFIG_SPL_BUILD + +obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o dpll-sld3.o +obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o dpll-ld4.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o dpll-pro4.o +obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o dpll-sld8.o +obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o +obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o +obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o +obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o + +else + obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += clk-ld4.o pll-sld3.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o @@ -11,3 +25,5 @@ obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-pxs2.o obj-$(CONFIG_ARCH_UNIPHIER_LD11) += clk-ld11.o obj-$(CONFIG_ARCH_UNIPHIER_LD20) += clk-ld20.o + +endif diff --git a/arch/arm/mach-uniphier/pll/pll-init-ld4.c b/arch/arm/mach-uniphier/clk/dpll-ld4.c similarity index 100% rename from arch/arm/mach-uniphier/pll/pll-init-ld4.c rename to arch/arm/mach-uniphier/clk/dpll-ld4.c diff --git a/arch/arm/mach-uniphier/pll/pll-init-pro4.c b/arch/arm/mach-uniphier/clk/dpll-pro4.c similarity index 100% rename from arch/arm/mach-uniphier/pll/pll-init-pro4.c rename to arch/arm/mach-uniphier/clk/dpll-pro4.c diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld3.c b/arch/arm/mach-uniphier/clk/dpll-sld3.c similarity index 100% rename from arch/arm/mach-uniphier/pll/pll-init-sld3.c rename to arch/arm/mach-uniphier/clk/dpll-sld3.c diff --git a/arch/arm/mach-uniphier/pll/pll-init-sld8.c b/arch/arm/mach-uniphier/clk/dpll-sld8.c similarity index 100% rename from arch/arm/mach-uniphier/pll/pll-init-sld8.c rename to arch/arm/mach-uniphier/clk/dpll-sld8.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld11.c b/arch/arm/mach-uniphier/clk/early-clk-ld11.c similarity index 100% rename from arch/arm/mach-uniphier/early-clk/early-clk-ld11.c rename to arch/arm/mach-uniphier/clk/early-clk-ld11.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld20.c b/arch/arm/mach-uniphier/clk/early-clk-ld20.c similarity index 100% rename from arch/arm/mach-uniphier/early-clk/early-clk-ld20.c rename to arch/arm/mach-uniphier/clk/early-clk-ld20.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-ld4.c b/arch/arm/mach-uniphier/clk/early-clk-ld4.c similarity index 100% rename from arch/arm/mach-uniphier/early-clk/early-clk-ld4.c rename to arch/arm/mach-uniphier/clk/early-clk-ld4.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pro5.c b/arch/arm/mach-uniphier/clk/early-clk-pro5.c similarity index 100% rename from arch/arm/mach-uniphier/early-clk/early-clk-pro5.c rename to arch/arm/mach-uniphier/clk/early-clk-pro5.c diff --git a/arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c b/arch/arm/mach-uniphier/clk/early-clk-pxs2.c similarity index 100% rename from arch/arm/mach-uniphier/early-clk/early-clk-pxs2.c rename to arch/arm/mach-uniphier/clk/early-clk-pxs2.c diff --git a/arch/arm/mach-uniphier/early-clk/Makefile b/arch/arm/mach-uniphier/early-clk/Makefile deleted file mode 100644 index 755a361..0000000 --- a/arch/arm/mach-uniphier/early-clk/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += early-clk-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += early-clk-pro5.o -obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += early-clk-pxs2.o -obj-$(CONFIG_ARCH_UNIPHIER_LD11) += early-clk-ld11.o -obj-$(CONFIG_ARCH_UNIPHIER_LD20) += early-clk-ld20.o diff --git a/arch/arm/mach-uniphier/pll/Makefile b/arch/arm/mach-uniphier/pll/Makefile deleted file mode 100644 index db22ba4..0000000 --- a/arch/arm/mach-uniphier/pll/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-$(CONFIG_ARCH_UNIPHIER_SLD3) += pll-init-sld3.o -obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-init-ld4.o -obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += pll-init-pro4.o -obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-init-sld8.o

Import the latest version from the Diag software.

- Support LD21 SoC (including DDR chips in the package) - Per-board granule adjustment for both reference and TV boards - Misc cleanups

Signed-off-by: Masahiro Yamada yamada.masahiro@socionext.com ---

arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h | 76 +++-- arch/arm/mach-uniphier/dram/umc-ld20.c | 431 +++++++++++++++++++++++-- 2 files changed, 445 insertions(+), 62 deletions(-)

diff --git a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h index b1b4cb0..b385a15 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-ld20-regs.h @@ -5,37 +5,49 @@ #ifndef _DDRPHY_LD20_REGS_H #define _DDRPHY_LD20_REGS_H

-#define PHY_SCL_DATA_0 0x00000104 -#define PHY_SCL_DATA_1 0x00000108 -#define PHY_SCL_LATENCY 0x0000010C -#define PHY_SCL_START 0x00000100 -#define PHY_SCL_CONFIG_1 0x00000118 -#define PHY_SCL_CONFIG_2 0x0000011C -#define PHY_PAD_CTRL 0x00000120 -#define PHY_DLL_RECALIB 0x00000124 -#define PHY_DLL_ADRCTRL 0x00000128 -#define PHY_LANE_SEL 0x0000012C -#define PHY_DLL_TRIM_1 0x00000130 -#define PHY_DLL_TRIM_2 0x00000134 -#define PHY_DLL_TRIM_3 0x00000138 -#define PHY_SCL_MAIN_CLK_DELTA 0x00000140 -#define PHY_WRLVL_AUTOINC_TRIM 0x0000014C -#define PHY_WRLVL_DYN_ODT 0x00000150 -#define PHY_WRLVL_ON_OFF 0x00000154 -#define PHY_UNQ_ANALOG_DLL_1 0x0000015C -#define PHY_DLL_INCR_TRIM_1 0x00000164 -#define PHY_DLL_INCR_TRIM_3 0x00000168 -#define PHY_SCL_CONFIG_3 0x0000016C -#define PHY_UNIQUIFY_TSMC_IO_1 0x00000170 -#define PHY_SCL_START_ADDR 0x00000188 -#define PHY_DSCL_CNT 0x0000019C -#define PHY_DLL_TRIM_CLK 0x000001A4 -#define PHY_DYNAMIC_BIT_LVL 0x000001AC -#define PHY_SCL_WINDOW_TRIM 0x000001B4 -#define PHY_DISABLE_GATING_FOR_SCL 0x000001B8 -#define PHY_SCL_CONFIG_4 0x000001BC -#define PHY_DYNAMIC_WRITE_BIT_LVL 0x000001C0 -#define PHY_VREF_TRAINING 0x000001C8 -#define PHY_SCL_GATE_TIMING 0x000001E0 +#define PHY_REG_SHIFT 2 + +#define PHY_SCL_START (0x40 << (PHY_REG_SHIFT)) +#define PHY_SCL_DATA_0 (0x41 << (PHY_REG_SHIFT)) +#define PHY_SCL_DATA_1 (0x42 << (PHY_REG_SHIFT)) +#define PHY_SCL_LATENCY (0x43 << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_1 (0x46 << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_2 (0x47 << (PHY_REG_SHIFT)) +#define PHY_PAD_CTRL (0x48 << (PHY_REG_SHIFT)) +#define PHY_DLL_RECALIB (0x49 << (PHY_REG_SHIFT)) +#define PHY_DLL_ADRCTRL (0x4A << (PHY_REG_SHIFT)) +#define PHY_LANE_SEL (0x4B << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_1 (0x4C << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_2 (0x4D << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_3 (0x4E << (PHY_REG_SHIFT)) +#define PHY_SCL_MAIN_CLK_DELTA (0x50 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_AUTOINC_TRIM (0x53 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_DYN_ODT (0x54 << (PHY_REG_SHIFT)) +#define PHY_WRLVL_ON_OFF (0x55 << (PHY_REG_SHIFT)) +#define PHY_UNQ_ANALOG_DLL_1 (0x57 << (PHY_REG_SHIFT)) +#define PHY_UNQ_ANALOG_DLL_2 (0x58 << (PHY_REG_SHIFT)) +#define PHY_DLL_INCR_TRIM_1 (0x59 << (PHY_REG_SHIFT)) +#define PHY_DLL_INCR_TRIM_3 (0x5A << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_3 (0x5B << (PHY_REG_SHIFT)) +#define PHY_UNIQUIFY_TSMC_IO_1 (0x5C << (PHY_REG_SHIFT)) +#define PHY_SCL_START_ADDR (0x62 << (PHY_REG_SHIFT)) +#define PHY_IP_DQ_DQS_BITWISE_TRIM (0x65 << (PHY_REG_SHIFT)) +#define PHY_DSCL_CNT (0x67 << (PHY_REG_SHIFT)) +#define PHY_OP_DQ_DM_DQS_BITWISE_TRIM (0x68 << (PHY_REG_SHIFT)) +#define PHY_DLL_TRIM_CLK (0x69 << (PHY_REG_SHIFT)) +#define PHY_DYNAMIC_BIT_LVL (0x6B << (PHY_REG_SHIFT)) +#define PHY_SCL_WINDOW_TRIM (0x6D << (PHY_REG_SHIFT)) +#define PHY_DISABLE_GATING_FOR_SCL (0x6E << (PHY_REG_SHIFT)) +#define PHY_SCL_CONFIG_4 (0x6F << (PHY_REG_SHIFT)) +#define PHY_DYNAMIC_WRITE_BIT_LVL (0x70 << (PHY_REG_SHIFT)) +#define PHY_VREF_TRAINING (0x72 << (PHY_REG_SHIFT)) +#define PHY_SCL_GATE_TIMING (0x78 << (PHY_REG_SHIFT)) + +/* MASK */ +#define MSK_OP_DQ_DM_DQS_BITWISE_TRIM 0x0000007F +#define MSK_IP_DQ_DQS_BITWISE_TRIM 0x0000007F +#define MSK_OVERRIDE 0x00000080 + +#define PHY_BITLVL_DLY_WIDTH 6

#endif /* _DDRPHY_LD20_REGS_H */ diff --git a/arch/arm/mach-uniphier/dram/umc-ld20.c b/arch/arm/mach-uniphier/dram/umc-ld20.c index 186a398..1fdd119 100644 --- a/arch/arm/mach-uniphier/dram/umc-ld20.c +++ b/arch/arm/mach-uniphier/dram/umc-ld20.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2016 Socionext Inc. * - * based on commit f7a4c9efe333fb1536efa86f9e96dc0ee109fedd of Diag + * based on commit a3c28918e86ad57127cf07bf8b32950cab20c03c of Diag * * SPDX-License-Identifier: GPL-2.0+ */ @@ -18,6 +18,7 @@ #include "umc64-regs.h"

#define DRAM_CH_NR 3 +#define CONFIG_DDR_FREQ 1866

enum dram_freq { DRAM_FREQ_1866M, @@ -30,6 +31,268 @@ enum dram_size { DRAM_SZ_NR, };

+enum dram_board { /* board type */ + DRAM_BOARD_LD20_REF, /* LD20 reference */ + DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */ + DRAM_BOARD_LD21_REF, /* LD21 reference */ + DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */ + DRAM_BOARD_NR, +}; + +#define MSK_PHY_LANE_SEL 0x000000FF +#define MSK_BIT_SEL 0x00000F00 +#define MSK_DLL_MAS_DLY 0xFF000000 +#define MSK_MAS_DLY 0x7F000000 +#define MSK_DLLS_TRIM_CLK 0x000000FF + +#define PHY_DLL_MAS_DLY_WIDTH 8 +#define PHY_SLV_DLY_WIDTH 6 + +static void ddrphy_maskwritel(u32 data, u32 mask, void *addr) +{ + u32 value; + + value = (readl(addr) & ~mask) | (data & mask); + writel(value, addr); +} + +static u32 ddrphy_maskreadl(u32 mask, void *addr) +{ + return readl(addr) & mask; +} + +/* set phy_lane_sel.phy_lane_sel */ +static void ddrphy_set_phy_lane_sel(int val, void __iomem *phy_base) +{ + ddrphy_maskwritel(val, MSK_PHY_LANE_SEL, phy_base + PHY_LANE_SEL); +} + +/* set phy_lane_sel.bit_sel */ +static void ddrphy_set_bit_sel(int bit, void __iomem *phy_base) +{ + ddrphy_maskwritel(bit << 8, MSK_BIT_SEL, phy_base + PHY_LANE_SEL); +} + +/* Calculating step for PUB-byte */ +static int ddrphy_hpstep(int delay, void __iomem *phy_base) +{ + int mdl, freq; + + freq = CONFIG_DDR_FREQ; /* FIXME */ + mdl = ddrphy_maskreadl(MSK_DLL_MAS_DLY, phy_base + PHY_DLL_ADRCTRL) >> 24; + + return DIV_ROUND_CLOSEST(freq * delay * mdl, 2 * 1000000); +} + +static void ddrphy_set_dll_trim_clk(int delay_ckoffset, void __iomem *phy_base) +{ + u8 ck_step; /* ckoffset_step for clock */ + u32 ck_step_all; + + /* CK-Offset */ + if (delay_ckoffset >= 0) { + /* shift + direction */ + ck_step = min(ddrphy_hpstep(delay_ckoffset, phy_base), 127); + ck_step_all = ((0x1<<(PHY_SLV_DLY_WIDTH + 1))|ck_step); + } else{ + /* shift - direction */ + ck_step = min(ddrphy_hpstep(-1*delay_ckoffset, phy_base), 127); + ck_step_all = ck_step; + } + + ddrphy_set_phy_lane_sel(0, phy_base); + ddrphy_maskwritel(ck_step_all, MSK_DLLS_TRIM_CLK, phy_base + PHY_DLL_TRIM_CLK); +} + +static void ddrphy_set_dll_recalib(int delay_qoffset, u32 recalib_cnt, + u8 disable_recalib, u8 ctr_start_val, + void __iomem *phy_base) +{ + u8 dlls_trim_adrctrl_ma, incr_dly_adrctrl_ma; /* qoffset_step and flag for inc/dec */ + u32 recalib_all; /* all fields of register dll_recalib */ + + /* Q-Offset */ + if (delay_qoffset >= 0) { + dlls_trim_adrctrl_ma = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); + incr_dly_adrctrl_ma = 0x1; + } else { + dlls_trim_adrctrl_ma = min(ddrphy_hpstep(-1*delay_qoffset, phy_base), 63); + incr_dly_adrctrl_ma = 0x0; + } + + recalib_all = ((ctr_start_val & 0xf) << 28) | + (incr_dly_adrctrl_ma << 27) | + ((disable_recalib & 0x1) << 26) | + ((recalib_cnt & 0x3ffff) << 8) | + (dlls_trim_adrctrl_ma & 0x3f); + + /* write value for all bits other than bit[7:6] */ + ddrphy_maskwritel(recalib_all, ~0xc0, phy_base + PHY_DLL_RECALIB); +} + +static void ddrphy_set_dll_adrctrl(int delay_qoffset, u8 override_adrctrl, + void __iomem *phy_base) +{ + u8 dlls_trim_adrctrl, incr_dly_adrctrl; /* qoffset_step for clock */ + u32 adrctrl_all; + + if (delay_qoffset >= 0) { + dlls_trim_adrctrl = min(ddrphy_hpstep(delay_qoffset, phy_base), 63); + incr_dly_adrctrl = 0x1; + } else { + dlls_trim_adrctrl = min(ddrphy_hpstep(-delay_qoffset, phy_base), 63); + incr_dly_adrctrl = 0x0; + } + + adrctrl_all = (incr_dly_adrctrl << 9) | + ((override_adrctrl & 0x1) << 8) | + dlls_trim_adrctrl; + + ddrphy_maskwritel(adrctrl_all, 0x33f, phy_base + PHY_DLL_ADRCTRL); +} + +/* dio */ +static int dio_adrctrl_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268-262, 268-263, 268-378}, /* LD20 reference */ + {268-262, 268-263, 268-378}, /* LD20 TV */ + {268-212, 268-268, 0}, /* LD21 reference */ + {268-212, 268-268, 0}, /* LD21 TV */ +}; +static int dio_dlltrimclk_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268, 268, 268}, /* LD20 reference */ + {268, 268, 268}, /* LD20 TV */ + {268, 268+252, 0}, /* LD21 reference */ + {268, 268+202, 0}, /* LD21 TV */ +}; +static int dio_dllrecalib_0[DRAM_BOARD_NR][DRAM_CH_NR] = { + {268-378, 268-263, 268-378}, /* LD20 reference */ + {268-378, 268-263, 268-378}, /* LD20 TV */ + {268-212, 268-536, 0}, /* LD21 reference */ + {268-212, 268-536, 0}, /* LD21 TV */ +}; + +static u32 dio_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = { + {0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */ + {0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */ + {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 reference */ + {0x50BB40B4, 0x50B840B1, 0x50BB40B1}, /* LD21 TV */ +}; + +static u32 dio_scl_gate_timing[DRAM_CH_NR] = {0x00000140, 0x00000180, 0x00000140}; + +static int dio_op_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { + { /* LD20 reference */ + { + 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + }, + { + 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + }, + { + 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + }, + }, + { /* LD20 TV */ + { + 2, 1, 0, 1, 2, 1, 1, 1, 2, 1, 1, 2, 1, 1, 1, 1, + 1, 2, 1, 1, 1, 2, 1, 1, 2, 2, 0, 1, 1, 2, 2, 1, + }, + { + 1, 1, 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 0, 0, 1, 1, 0, 0, 0, 1, 1, 1, 2, 1, 2, 1, + }, + { + 2, 2, 0, 2, 1, 1, 2, 1, 1, 1, 0, 1, 1, -1, 1, 1, + 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 0, 2, 2, 1, 2, + }, + }, + { /* LD21 reference */ + { + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, + }, + { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, + { /* LD21 TV */ + { + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 0, 2, + 1, 1, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 1, 0, 0, 1, + }, + { 1, 0, 2, 1, 1, 1, 1, 0, 1, 0, 0, 1, 0, 1, 0, 0, + 1, 0, 1, 0, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 0, 0, + }, + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, +}; +static int dio_ip_dq_shift_val[DRAM_BOARD_NR][DRAM_CH_NR][32] = { + { /* LD20 reference */ + { + 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + }, + { + 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + }, + { + 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + }, + }, + { /* LD20 TV */ + { + 3, 3, 3, 2, 3, 2, 0, 2, 2, 3, 3, 1, 2, 2, 2, 2, + 2, 2, 2, 2, 0, 1, 1, 1, 2, 2, 2, 2, 3, 0, 2, 2, + }, + { + 2, 2, 1, 1, -1, 1, 1, 1, 2, 0, 2, 2, 2, 1, 0, 2, + 2, 1, 2, 1, 0, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, + }, + { + 2, 2, 3, 2, 1, 2, 2, 2, 2, 3, 4, 2, 3, 4, 3, 3, + 2, 2, 1, 2, 1, 1, 1, 1, 2, 2, 2, 2, 1, 2, 2, 1, + }, + }, + { /* LD21 reference */ + { + 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, + }, + { + 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + }, + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, + { /* LD21 TV */ + { + 2, 2, 2, 2, 1, 2, 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, + 2, 1, 2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 1, 2, 2, 2, + }, + { + 3, 4, 4, 1, 0, 1, 1, 1, 1, 2, 1, 2, 2, 3, 3, 2, + 1, 0, 2, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 1, 0, 1, + }, + { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + }, + }, +}; + /* umc */ static u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11}; static u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC}; @@ -37,15 +300,24 @@ static u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF}; static u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114}; static u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};

-static u32 umc_memconf0a[DRAM_FREQ_NR] = {0x00000801}; -static u32 umc_memconf0b[DRAM_FREQ_NR] = {0x00000130}; -static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00033803}; - +static u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000601, 0x00000801}, /* 1866 MHz */ +}; +static u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00000120, 0x00000130}, /* 1866 MHz */ +}; +static u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = { + /* 256MB 512MB */ + {0x00033603, 0x00033803}, /* 1866 MHz */ +}; static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20}; static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08}; static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04}; static u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = { - {0x0049071D, 0x0078071D}, + /* 256MB 512MB */ + {0x0049071D, 0x0078071D}, /* 1866 MHz */ };

static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000610}; @@ -61,12 +333,22 @@ static u32 umc_directbusctrla[DRAM_CH_NR] = { 0x00000000, 0x00000001, 0x00000001 };

+/* polling function for PHY Init Complete */ +static void ddrphy_init_complete(void __iomem *dc_base) +{ + /* Wait for PHY Init Complete */ + while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) + cpu_relax(); +} + /* DDR PHY */ -static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) +static void ddrphy_init(void __iomem *phy_base, void __iomem *dc_base, + enum dram_freq freq, enum dram_board board, int ch) { - writel(0x00000001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); - while ((readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) + writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1); + while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1))) cpu_relax(); + writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);

writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3); writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1); @@ -84,14 +366,14 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) writel(0x0000000a, phy_base + PHY_DLL_TRIM_3); writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM); writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1); - writel(0x50bb40b1, phy_base + PHY_PAD_CTRL); + writel(dio_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL); writel(0x00000070, phy_base + PHY_VREF_TRAINING); writel(0x01000075, phy_base + PHY_SCL_CONFIG_1); writel(0x00000501, phy_base + PHY_SCL_CONFIG_2); writel(0x00000000, phy_base + PHY_SCL_CONFIG_3); writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); writel(0x00000000, phy_base + PHY_SCL_CONFIG_4); - writel(0x000000a0, phy_base + PHY_SCL_GATE_TIMING); + writel(dio_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING); writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT); writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF); writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL); @@ -99,30 +381,96 @@ static void ddrphy_init(void __iomem *phy_base, enum dram_freq freq) writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK); writel(0xa800100d, phy_base + PHY_DLL_RECALIB); writel(0x00005076, phy_base + PHY_SCL_LATENCY); + + ddrphy_init_complete(dc_base); + + ddrphy_set_dll_adrctrl(dio_adrctrl_0[board][ch], 0, phy_base); + ddrphy_set_dll_trim_clk(dio_dlltrimclk_0[board][ch], phy_base); + ddrphy_set_dll_recalib(dio_dllrecalib_0[board][ch], 0x10, 0, 0xa, + phy_base); +} + +static void ddrphy_shift_dq(u32 reg_mask, u32 reg_addr, int shift_val, + void __iomem *phy_base) +{ + u32 reg_val; + int dq_val; + + reg_val = ddrphy_maskreadl(reg_mask, phy_base + reg_addr) & 0x7f; + dq_val = reg_val & 0x3f; + + if ((reg_val & 0x40) == 0x00) + dq_val = -1 * dq_val; + + /* value shift*/ + dq_val = dq_val + shift_val; + + if (dq_val >= 0) + reg_val = 0x40 + (dq_val & 0x3f); + else + reg_val = ((-1 * dq_val) & 0x3f); + + ddrphy_maskwritel(reg_val, reg_mask, phy_base + reg_addr); }

-static int ddrphy_training(void __iomem *phy_base) +static void ddrphy_shift(void __iomem *phy_base, enum dram_board board, int ch) +{ + u32 dx, bit; + + /* set override = 1 */ + ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, + phy_base + PHY_OP_DQ_DM_DQS_BITWISE_TRIM); + ddrphy_maskwritel(MSK_OVERRIDE, MSK_OVERRIDE, + phy_base + PHY_IP_DQ_DQS_BITWISE_TRIM); + + for (dx = 0; dx < 4; dx++) { + /* set byte to PHY_LANE_SEL.phy_lane_sel= dx * (PHY_BITLVL_DLY_WIDTH+1) */ + ddrphy_set_phy_lane_sel(dx * (PHY_BITLVL_DLY_WIDTH + 1), + phy_base); + + for (bit = 0; bit < 8; bit++) { + ddrphy_set_bit_sel(bit, phy_base); + + /* shift write reg value*/ + ddrphy_shift_dq(MSK_OP_DQ_DM_DQS_BITWISE_TRIM, + PHY_OP_DQ_DM_DQS_BITWISE_TRIM, + dio_op_dq_shift_val[board][ch][dx * 8 + bit], + phy_base); + /* shift read reg value */ + ddrphy_shift_dq(MSK_IP_DQ_DQS_BITWISE_TRIM, + PHY_IP_DQ_DQS_BITWISE_TRIM, + dio_ip_dq_shift_val[board][ch][dx * 8 + bit], + phy_base); + } + + } + ddrphy_set_phy_lane_sel(0, phy_base); + ddrphy_set_bit_sel(0, phy_base); +} + +static int ddrphy_training(void __iomem *phy_base, enum dram_board board, + int ch) { writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM); writel(0x00010000, phy_base + PHY_DLL_TRIM_2); writel(0x50000000, phy_base + PHY_SCL_START);

- while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax();

writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL); writel(0xff00ff00, phy_base + PHY_SCL_DATA_0); writel(0xff00ff00, phy_base + PHY_SCL_DATA_1); - writel(0x00080000, phy_base + PHY_SCL_START_ADDR); + writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR); writel(0x11000000, phy_base + PHY_SCL_START);

- while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax();

- writel(0x00000000, phy_base + PHY_SCL_START_ADDR); + writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR); writel(0x30500000, phy_base + PHY_SCL_START);

- while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax();

writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL); @@ -131,16 +479,22 @@ static int ddrphy_training(void __iomem *phy_base) writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1); writel(0x11000000, phy_base + PHY_SCL_START);

- while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax();

writel(0x34000000, phy_base + PHY_SCL_START);

- while ((readl(phy_base + PHY_SCL_START) & BIT(28))) + while (readl(phy_base + PHY_SCL_START) & BIT(28)) cpu_relax();

writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);

+ writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL); + writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL); + writel(0x011BD0C4, phy_base + PHY_DSCL_CNT); + + /* shift ip_dq, op_dq trim */ + ddrphy_shift(phy_base, board, ch); return 0; }

@@ -164,10 +518,6 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, return -EINVAL; }

- /* Wait for PHY Init Complete */ - while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0))) - cpu_relax(); - writel(0x00000001, dc_base + UMC_DFICSOVRRD); writel(0x00000000, dc_base + UMC_DFITURNOFF);

@@ -180,9 +530,9 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, writel(umc_drmmr2[freq], dc_base + UMC_DRMMR2); writel(0x00000000, dc_base + UMC_DRMMR3);

- writel(umc_memconf0a[freq], dc_base + UMC_MEMCONF0A); - writel(umc_memconf0b[freq], dc_base + UMC_MEMCONF0B); - writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH); + writel(umc_memconf0a[freq][size_e], dc_base + UMC_MEMCONF0A); + writel(umc_memconf0b[freq][size_e], dc_base + UMC_MEMCONF0B); + writel(umc_memconfch[freq][size_e], dc_base + UMC_MEMCONFCH); writel(0x00000008, dc_base + UMC_MEMMAPSET);

writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA); @@ -227,7 +577,8 @@ static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq, }

static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, - enum dram_freq freq, unsigned long size, int ch) + enum dram_freq freq, enum dram_board board, + unsigned long size, int ch) { void __iomem *dc_base = umc_ch_base + 0x00011000; void __iomem *phy_base = phy_ch_base; @@ -240,13 +591,13 @@ static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base, writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST, dc_base + UMC_DIOCTLA);

- ddrphy_init(phy_base, freq); + ddrphy_init(phy_base, dc_base, freq, board, ch);

ret = umc_dc_init(dc_base, freq, size, ch); if (ret) return ret;

- ret = ddrphy_training(phy_base); + ret = ddrphy_training(phy_base, board, ch); if (ret) return ret;

@@ -274,6 +625,7 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) void __iomem *umc_ch_base = (void __iomem *)0x5b800000; void __iomem *phy_ch_base = (void __iomem *)0x6e200000; enum dram_freq freq; + enum dram_board board; int ch, ret;

switch (bd->dram_freq) { @@ -285,11 +637,30 @@ int uniphier_ld20_umc_init(const struct uniphier_board_data *bd) return -EINVAL; }

+ switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) { + case UNIPHIER_BD_BOARD_LD20_REF: + board = DRAM_BOARD_LD20_REF; + break; + case UNIPHIER_BD_BOARD_LD20_GLOBAL: + board = DRAM_BOARD_LD20_GLOBAL; + break; + case UNIPHIER_BD_BOARD_LD21_REF: + board = DRAM_BOARD_LD21_REF; + break; + case UNIPHIER_BD_BOARD_LD21_GLOBAL: + board = DRAM_BOARD_LD21_GLOBAL; + break; + default: + pr_err("unsupported board type %d\n", + UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)); + return -EINVAL; + } + for (ch = 0; ch < bd->dram_nr_ch; ch++) { unsigned long size = bd->dram_ch[ch].size; unsigned int width = bd->dram_ch[ch].width;

- ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, + ret = umc_ch_init(umc_ch_base, phy_ch_base, freq, board, size / (width / 16), ch); if (ret) { pr_err("failed to initialize UMC ch%d\n", ch);