[U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v5: - No change. Changes in v4: - No change. Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA). Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA.
drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..4b33fae 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@ * eSPI controller driver. * * Copyright 2010-2011 Freescale Semiconductor, Inc. + * Copyright 2019 NXP * Author: Mingkai Hu (Mingkai.hu@freescale.com) + * Chuanhua Han (chuanhua.han@nxp.com) */
#include <common.h> - #include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h>
struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi; + u32 speed_hz; + unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout; @@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL
+/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000 + #define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32
@@ -62,116 +72,27 @@ struct fsl_spi_slave {
#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) -{ - struct fsl_spi_slave *fsl; - sys_info_t sysinfo; - unsigned long spibrg = 0; - unsigned long spi_freq = 0; - unsigned char pm = 0; - - if (!spi_cs_is_valid(bus, cs)) - return NULL; - - fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); - if (!fsl) - return NULL; - - fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); - fsl->mode = mode; - fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; - - /* Set eSPI BRG clock source */ - get_sys_info(&sysinfo); - spibrg = sysinfo.freq_systembus / 2; - fsl->div16 = 0; - if ((spibrg / max_hz) > 32) { - fsl->div16 = ESPI_CSMODE_DIV16; - pm = spibrg / (max_hz * 16 * 2); - if (pm > 16) { - pm = 16; - debug("Requested speed is too low: %d Hz, %ld Hz " - "is used.\n", max_hz, spibrg / (32 * 16)); - } - } else - pm = spibrg / (max_hz * 2); - if (pm) - pm--; - fsl->pm = pm; - - if (fsl->div16) - spi_freq = spibrg / ((pm + 1) * 2 * 16); - else - spi_freq = spibrg / ((pm + 1) * 2); - - /* set tx_timeout to 10 times of one espi FIFO entry go out */ - fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT - * 10), spi_freq); - - return &fsl->slave; -} - -void spi_free_slave(struct spi_slave *slave) -{ - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - free(fsl); -} - -int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi; - unsigned char pm = fsl->pm; - unsigned int cs = slave->cs; - unsigned int mode = fsl->mode; - unsigned int div16 = fsl->div16; - int i; - - debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs); - - /* Enable eSPI interface */ - out_be32(&espi->mode, ESPI_MODE_RXTHR(3) - | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); - - out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ - out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ - - /* Init CS mode interface */ - for (i = 0; i < ESPI_MAX_CS_NUM; i++) - out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); - - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & - ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 - | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK - | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); - - /* Set eSPI BRG clock source */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_PM(pm) | div16); - - /* Set eSPI mode */ - if (mode & SPI_CPHA) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CP_BEGIN_EDGCLK); - if (mode & SPI_CPOL) - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_CI_INACTIVEHIGH); - - /* Character bit order: msb first */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_REV_MSB_FIRST); - - /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ - out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) - | ESPI_CSMODE_LEN(7)); + unsigned int com = 0; + size_t data_len = fsl->data_len;
- return 0; + com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); + com |= ESPI_COM_CS(cs); + com |= ESPI_COM_TRANLEN(data_len - 1); + out_be32(&espi->com, com); }
-void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) { + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + ccsr_espi_t *espi = fsl->espi;
+ /* clear the RXCNT and TXCNT */ + out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); + out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); }
static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); }
-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, + unsigned int bytes) { ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; }
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, - void *data_in, unsigned long flags) +void espi_release_bus(struct fsl_spi_slave *fsl) { - struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + /* Disable the SPI hardware */ + out_be32(&fsl->espi->mode, + in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); +} + +int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen, + const void *data_out, void *data_in, unsigned long flags) +{ + struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL; @@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN: - cmd_len = fsl->cmd_len = data_len; + cmd_len = data_len; + fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) { - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len); @@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len; - spi_cs_activate(slave); + fsl_spi_cs_activate(slave, cs);
/* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -347,37 +277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } } - spi_cs_deactivate(slave); + fsl_spi_cs_deactivate(slave); }
free(buffer); return 0; }
+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{ + ccsr_espi_t *espi = fsl->espi; + unsigned char pm = fsl->pm; + unsigned int mode = fsl->mode; + unsigned int div16 = fsl->div16; + int i; + + /* Enable eSPI interface */ + out_be32(&espi->mode, ESPI_MODE_RXTHR(3) + | ESPI_MODE_TXTHR(4) | ESPI_MODE_EN); + + out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */ + out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts */ + + /* Init CS mode interface */ + for (i = 0; i < ESPI_MAX_CS_NUM; i++) + out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL); + + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) & + ~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16 + | ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK + | ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF))); + + /* Set eSPI BRG clock source */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_PM(pm) | div16); + + /* Set eSPI mode */ + if (mode & SPI_CPHA) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (mode & SPI_CPOL) + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); + + /* Character bit order: msb first */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_REV_MSB_FIRST); + + /* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */ + out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) + | ESPI_CSMODE_LEN(7)); +} + +void espi_setup_slave(struct fsl_spi_slave *fsl) +{ + unsigned int max_hz; + sys_info_t sysinfo; + unsigned long spibrg = 0; + unsigned long spi_freq = 0; + unsigned char pm = 0; + + max_hz = fsl->speed_hz; + + get_sys_info(&sysinfo); + spibrg = sysinfo.freq_systembus / 2; + fsl->div16 = 0; + if ((spibrg / max_hz) > 32) { + fsl->div16 = ESPI_CSMODE_DIV16; + pm = spibrg / (max_hz * 16 * 2); + if (pm > 16) { + pm = 16; + debug("max_hz is too low: %d Hz, %ld Hz is used.\n", + max_hz, spibrg / (32 * 16)); + } + } else { + pm = spibrg / (max_hz * 2); + } + if (pm) + pm--; + fsl->pm = pm; + + if (fsl->div16) + spi_freq = spibrg / ((pm + 1) * 2 * 16); + else + spi_freq = spibrg / ((pm + 1) * 2); + + /* set tx_timeout to 10 times of one espi FIFO entry go out */ + fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT + * 10), spi_freq);/* Set eSPI BRG clock source */ +} + +#ifndef CONFIG_DM_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; }
-void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, + unsigned int max_hz, unsigned int mode) +{ + struct fsl_spi_slave *fsl; + + if (!spi_cs_is_valid(bus, cs)) + return NULL; + + fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs); + if (!fsl) + return NULL; + + fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->mode = mode; + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = max_hz; + + espi_setup_slave(fsl); + + return &fsl->slave; +} + +void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi; - unsigned int com = 0; - size_t data_len = fsl->data_len;
- com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF)); - com |= ESPI_COM_CS(slave->cs); - com |= ESPI_COM_TRANLEN(data_len - 1); - out_be32(&espi->com, com); + free(fsl); }
-void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); - ccsr_espi_t *espi = fsl->espi;
- /* clear the RXCNT and TXCNT */ - out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN)); - out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN); + espi_claim_bus(fsl, slave->cs); + + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); + + espi_release_bus(fsl); +} + +int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, + void *din, unsigned long flags) +{ + struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave; + + return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); +} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{ + espi_setup_slave(fsl); + + /* Set eSPI BRG clock source */ + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_PM(fsl->pm) | fsl->div16); +} + +static void __espi_set_mode(struct fsl_spi_slave *fsl) +{ + /* Set eSPI mode */ + if (fsl->mode & SPI_CPHA) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CP_BEGIN_EDGCLK); + if (fsl->mode & SPI_CPOL) + out_be32(&fsl->espi->csmode[fsl->cs], + in_be32(&fsl->espi->csmode[fsl->cs]) + | ESPI_CSMODE_CI_INACTIVEHIGH); +} + +static int fsl_espi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_claim_bus(fsl, fsl->cs); + + return 0; +} + +static int fsl_espi_release_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + espi_release_bus(fsl); + + return 0; +} + +static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, unsigned long flags) +{ + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); +} + +static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s speed %u\n", __func__, speed); + fsl->speed_hz = speed; + + __espi_set_speed(fsl); + + return 0; +} + +static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{ + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s mode %u\n", __func__, mode); + fsl->mode = mode; + + __espi_set_mode(fsl); + + return 0; } + +static int fsl_espi_child_pre_probe(struct udevice *dev) +{ + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev); + struct udevice *bus = dev->parent; + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + debug("%s cs %u\n", __func__, slave_plat->cs); + fsl->cs = slave_plat->cs; + + return 0; +} + +static int fsl_espi_probe(struct udevice *bus) +{ + struct fsl_espi_platdata *plat = dev_get_platdata(bus); + struct fsl_spi_slave *fsl = dev_get_priv(bus); + + fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr); + fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; + fsl->speed_hz = plat->speed_hz; + + debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); + + return 0; +} + +static const struct dm_spi_ops fsl_espi_ops = { + .claim_bus = fsl_espi_claim_bus, + .release_bus = fsl_espi_release_bus, + .xfer = fsl_espi_xfer, + .set_speed = fsl_espi_set_speed, + .set_mode = fsl_espi_set_mode, +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{ + fdt_addr_t addr; + struct fsl_espi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + + addr = dev_read_addr(bus); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + plat->regs_addr = lower_32_bits(addr); + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + FSL_ESPI_DEFAULT_SCK_FREQ); + + debug("ESPI: regs=%p, max-frequency=%d\n", + &plat->regs_addr, plat->speed_hz); + + return 0; +} + +static const struct udevice_id fsl_espi_ids[] = { + { .compatible = "fsl,mpc8536-espi" }, + { } +}; +#endif + +U_BOOT_DRIVER(fsl_espi) = { + .name = "fsl_espi", + .id = UCLASS_SPI, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = fsl_espi_ids, + .ofdata_to_platdata = fsl_espi_ofdata_to_platdata, +#endif + .ops = &fsl_espi_ops, + .platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata), + .priv_auto_alloc_size = sizeof(struct fsl_spi_slave), + .probe = fsl_espi_probe, + .child_pre_probe = fsl_espi_child_pre_probe, +}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2019 NXP + */ + +#ifndef __fsl_espi_h +#define __fsl_espi_h + +struct fsl_espi_platdata { + uint flags; + uint speed_hz; + uint num_chipselect; + fdt_addr_t regs_addr; +}; + +#endif /* __fsl_espi_h */
On Tue, 2019-08-20 at 06:59 +0000, Xiaowei Bao wrote:
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This board does not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
These are not the only problems with this driver it is borken for anything but loading small amount of data from SPI NOR flash. Look at spi_xfer: overuse of malloc/memcpy misuse of word size(always 32 bits) making proper of ESPI_EV_RNE/ESPI_EV_TNF impossible. random test of 0x0b: memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; *(int *)buffer += tran_len; }
I think fixing the driver to work properly first is preferable to DM conversion.
Jocke
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA). Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA.
drivers/spi/fsl_espi.c | 445 ++++++++++++++++++++++++++---------- include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..4b33fae 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@
- eSPI controller driver.
- Copyright 2010-2011 Freescale Semiconductor, Inc.
- Copyright 2019 NXP
- Author: Mingkai Hu (Mingkai.hu@freescale.com)
*/
Chuanhua Han (chuanhua.han@nxp.com)#include <common.h>
#include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h>
struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi;
u32 speed_hz;unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout;@@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL
+/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
#define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32
@@ -62,116 +72,27 @@ struct fsl_spi_slave {
#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)-{
struct fsl_spi_slave *fsl;sys_info_t sysinfo;unsigned long spibrg = 0;unsigned long spi_freq = 0;unsigned char pm = 0;if (!spi_cs_is_valid(bus, cs))return NULL;fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);if (!fsl)return NULL;fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);fsl->mode = mode;fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;/* Set eSPI BRG clock source */get_sys_info(&sysinfo);spibrg = sysinfo.freq_systembus / 2;fsl->div16 = 0;if ((spibrg / max_hz) > 32) {fsl->div16 = ESPI_CSMODE_DIV16;pm = spibrg / (max_hz * 16 * 2);if (pm > 16) {pm = 16;debug("Requested speed is too low: %d Hz, %ld Hz ""is used.\n", max_hz, spibrg / (32 * 16));}} elsepm = spibrg / (max_hz * 2);if (pm)pm--;fsl->pm = pm;if (fsl->div16)spi_freq = spibrg / ((pm + 1) * 2 * 16);elsespi_freq = spibrg / ((pm + 1) * 2);/* set tx_timeout to 10 times of one espi FIFO entry go out */fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT* 10), spi_freq);return &fsl->slave;-}
-void spi_free_slave(struct spi_slave *slave) -{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);free(fsl);-}
-int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi;
unsigned char pm = fsl->pm;unsigned int cs = slave->cs;unsigned int mode = fsl->mode;unsigned int div16 = fsl->div16;int i;debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);/* Enable eSPI interface */out_be32(&espi->mode, ESPI_MODE_RXTHR(3)| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts *//* Init CS mode interface */for (i = 0; i < ESPI_MAX_CS_NUM; i++)out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));/* Set eSPI BRG clock source */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_PM(pm) | div16);/* Set eSPI mode */if (mode & SPI_CPHA)out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_CP_BEGIN_EDGCLK);if (mode & SPI_CPOL)out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_CI_INACTIVEHIGH);/* Character bit order: msb first */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_REV_MSB_FIRST);/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_LEN(7));
unsigned int com = 0;size_t data_len = fsl->data_len;
return 0;
com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));com |= ESPI_COM_CS(cs);com |= ESPI_COM_TRANLEN(data_len - 1);out_be32(&espi->com, com);}
-void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) {
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);ccsr_espi_t *espi = fsl->espi;/* clear the RXCNT and TXCNT */out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);}
static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) debug("***spi_xfer:...Tx timeout! event = %08x\n", event); }
-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
unsigned int bytes){ ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; }
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
void *data_in, unsigned long flags)+void espi_release_bus(struct fsl_spi_slave *fsl) {
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
/* Disable the SPI hardware */out_be32(&fsl->espi->mode,in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN));+}
+int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
const void *data_out, void *data_in, unsigned long flags)+{
struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL;@@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN:
cmd_len = fsl->cmd_len = data_len;
cmd_len = data_len;fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) {
spi_cs_deactivate(slave);
fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len, (size_t)max_tran_len);@@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len;
spi_cs_activate(slave);
fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff);@@ -347,37 +277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out, *(int *)buffer += tran_len; } }
spi_cs_deactivate(slave);
fsl_spi_cs_deactivate(slave); } free(buffer); return 0;}
+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) +{
ccsr_espi_t *espi = fsl->espi;unsigned char pm = fsl->pm;unsigned int mode = fsl->mode;unsigned int div16 = fsl->div16;int i;/* Enable eSPI interface */out_be32(&espi->mode, ESPI_MODE_RXTHR(3)| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */out_be32(&espi->mask, 0x00000000); /* Mask all eSPI interrupts *//* Init CS mode interface */for (i = 0; i < ESPI_MAX_CS_NUM; i++)out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16| ESPI_CSMODE_CI_INACTIVEHIGH | ESPI_CSMODE_CP_BEGIN_EDGCLK| ESPI_CSMODE_REV_MSB_FIRST | ESPI_CSMODE_LEN(0xF)));/* Set eSPI BRG clock source */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_PM(pm) | div16);/* Set eSPI mode */if (mode & SPI_CPHA)out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_CP_BEGIN_EDGCLK);if (mode & SPI_CPOL)out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_CI_INACTIVEHIGH);/* Character bit order: msb first */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_REV_MSB_FIRST);/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_LEN(7));+}
+void espi_setup_slave(struct fsl_spi_slave *fsl) +{
unsigned int max_hz;sys_info_t sysinfo;unsigned long spibrg = 0;unsigned long spi_freq = 0;unsigned char pm = 0;max_hz = fsl->speed_hz;get_sys_info(&sysinfo);spibrg = sysinfo.freq_systembus / 2;fsl->div16 = 0;if ((spibrg / max_hz) > 32) {fsl->div16 = ESPI_CSMODE_DIV16;pm = spibrg / (max_hz * 16 * 2);if (pm > 16) {pm = 16;debug("max_hz is too low: %d Hz, %ld Hz is used.\n",max_hz, spibrg / (32 * 16));}} else {pm = spibrg / (max_hz * 2);}if (pm)pm--;fsl->pm = pm;if (fsl->div16)spi_freq = spibrg / ((pm + 1) * 2 * 16);elsespi_freq = spibrg / ((pm + 1) * 2);/* set tx_timeout to 10 times of one espi FIFO entry go out */fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT* 10), spi_freq);/* Set eSPI BRG clock source */+}
+#ifndef CONFIG_DM_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; }
-void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)+{
struct fsl_spi_slave *fsl;if (!spi_cs_is_valid(bus, cs))return NULL;fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);if (!fsl)return NULL;fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);fsl->mode = mode;fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;fsl->speed_hz = max_hz;espi_setup_slave(fsl);return &fsl->slave;+}
+void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
ccsr_espi_t *espi = fsl->espi;unsigned int com = 0;size_t data_len = fsl->data_len;com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));com |= ESPI_COM_CS(slave->cs);com |= ESPI_COM_TRANLEN(data_len - 1);out_be32(&espi->com, com);
free(fsl);}
-void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
ccsr_espi_t *espi = fsl->espi;/* clear the RXCNT and TXCNT */out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));out_be32(&espi->mode, in_be32(&espi->mode) | ESPI_MODE_EN);
espi_claim_bus(fsl, slave->cs);return 0;+}
+void spi_release_bus(struct spi_slave *slave) +{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);espi_release_bus(fsl);+}
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)+{
struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags);+} +#else +static void __espi_set_speed(struct fsl_spi_slave *fsl) +{
espi_setup_slave(fsl);/* Set eSPI BRG clock source */out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])| ESPI_CSMODE_PM(fsl->pm) | fsl->div16);+}
+static void __espi_set_mode(struct fsl_spi_slave *fsl) +{
/* Set eSPI mode */if (fsl->mode & SPI_CPHA)out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])| ESPI_CSMODE_CP_BEGIN_EDGCLK);if (fsl->mode & SPI_CPOL)out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])| ESPI_CSMODE_CI_INACTIVEHIGH);+}
+static int fsl_espi_claim_bus(struct udevice *dev) +{
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);espi_claim_bus(fsl, fsl->cs);return 0;+}
+static int fsl_espi_release_bus(struct udevice *dev) +{
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);espi_release_bus(fsl);return 0;+}
+static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long flags)+{
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags);+}
+static int fsl_espi_set_speed(struct udevice *bus, uint speed) +{
struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s speed %u\n", __func__, speed);fsl->speed_hz = speed;__espi_set_speed(fsl);return 0;+}
+static int fsl_espi_set_mode(struct udevice *bus, uint mode) +{
struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s mode %u\n", __func__, mode);fsl->mode = mode;__espi_set_mode(fsl);return 0;}
+static int fsl_espi_child_pre_probe(struct udevice *dev) +{
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s cs %u\n", __func__, slave_plat->cs);fsl->cs = slave_plat->cs;return 0;+}
+static int fsl_espi_probe(struct udevice *bus) +{
struct fsl_espi_platdata *plat = dev_get_platdata(bus);struct fsl_spi_slave *fsl = dev_get_priv(bus);fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;fsl->speed_hz = plat->speed_hz;debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);return 0;+}
+static const struct dm_spi_ops fsl_espi_ops = {
.claim_bus = fsl_espi_claim_bus,.release_bus = fsl_espi_release_bus,.xfer = fsl_espi_xfer,.set_speed = fsl_espi_set_speed,.set_mode = fsl_espi_set_mode,+};
+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int fsl_espi_ofdata_to_platdata(struct udevice *bus) +{
fdt_addr_t addr;struct fsl_espi_platdata *plat = bus->platdata;const void *blob = gd->fdt_blob;int node = dev_of_offset(bus);addr = dev_read_addr(bus);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->regs_addr = lower_32_bits(addr);plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",FSL_ESPI_DEFAULT_SCK_FREQ);debug("ESPI: regs=%p, max-frequency=%d\n",&plat->regs_addr, plat->speed_hz);return 0;+}
+static const struct udevice_id fsl_espi_ids[] = {
{ .compatible = "fsl,mpc8536-espi" },{ }+}; +#endif
+U_BOOT_DRIVER(fsl_espi) = {
.name = "fsl_espi",.id = UCLASS_SPI,+#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = fsl_espi_ids,.ofdata_to_platdata = fsl_espi_ofdata_to_platdata,+#endif
.ops = &fsl_espi_ops,.platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),.priv_auto_alloc_size = sizeof(struct fsl_spi_slave),.probe = fsl_espi_probe,.child_pre_probe = fsl_espi_child_pre_probe,+}; +#endif diff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- */
+#ifndef __fsl_espi_h +#define __fsl_espi_h
+struct fsl_espi_platdata {
uint flags;uint speed_hz;uint num_chipselect;fdt_addr_t regs_addr;+};
+#endif /* __fsl_espi_h */
2.9.5
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月20日 19:04 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, 2019-08-20 at 06:59 +0000, Xiaowei Bao wrote:
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
These are not the only problems with this driver it is borken for anything but loading small amount of data from SPI NOR flash. Look at spi_xfer: overuse of malloc/memcpy misuse of word size(always 32 bits) making proper of ESPI_EV_RNE/ESPI_EV_TNF impossible. random test of 0x0b: memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; *(int *)buffer += tran_len; }
I think fixing the driver to work properly first is preferable to DM conversion.
Thanks a lot for your comments, in fact, these code exist all the time, I never modify this part code, and I have verified the SPI flash use 4K data, the test result is ok, I will check and analyze this part code, and give the reply later, thanks.
Jocke
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5: - Modify the function spi_cs_activate to fsl_spi_cs_activate. - Move cs to the parameter of the fsl_spi_cs_activate function. Changes in v4: - Update copyright information. - Move the fsl_espi_platdata data structure to the include/dm/platform_data/. - Merge the contents of the fsl_espi_priv structure into the fsl_spi_slave structure. - Implement the fsl_espi_set_speed function. - Implement the fsl_espi_set_mode function. - Implement the espi_release_bus function. - Remove unwanted fsl_espi_bind functions. - Implement the fsl_espi_child_pre_probe function as needed. - Use #if CONFIG_IS_ENABLED(OF_CONTROL)
&& !CONFIG_IS_ENABLED(OF_PLATDATA).
Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - The fsl_espi driver support both OF_CONTROL and PLATDATA.
drivers/spi/fsl_espi.c | 445
++++++++++++++++++++++++++----------
include/dm/platform_data/fsl_espi.h | 16 ++ 2 files changed, 337 insertions(+), 124 deletions(-) create mode 100644 include/dm/platform_data/fsl_espi.h
diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index 7444ae1..4b33fae 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -3,18 +3,25 @@
- eSPI controller driver.
- Copyright 2010-2011 Freescale Semiconductor, Inc.
- Copyright 2019 NXP
- Author: Mingkai Hu (Mingkai.hu@freescale.com)
*/
Chuanhua Han (chuanhua.han@nxp.com)#include <common.h>
#include <malloc.h> #include <spi.h> #include <asm/immap_85xx.h> +#include <dm.h> +#include <errno.h> +#include <fdtdec.h> +#include <dm/platform_data/fsl_espi.h>
struct fsl_spi_slave { struct spi_slave slave; ccsr_espi_t *espi;
u32 speed_hz;unsigned int cs; unsigned int div16; unsigned int pm; int tx_timeout;@@ -28,6 +35,9 @@ struct fsl_spi_slave { #define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave) #define US_PER_SECOND 1000000UL
+/* default SCK frequency, unit: HZ */ +#define FSL_ESPI_DEFAULT_SCK_FREQ 10000000
#define ESPI_MAX_CS_NUM 4 #define ESPI_FIFO_WIDTH_BIT 32
@@ -62,116 +72,27 @@ struct fsl_spi_slave {
#define ESPI_MAX_DATA_TRANSFER_LEN 0xFFF0
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)-{
struct fsl_spi_slave *fsl;sys_info_t sysinfo;unsigned long spibrg = 0;unsigned long spi_freq = 0;unsigned char pm = 0;if (!spi_cs_is_valid(bus, cs))return NULL;fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);if (!fsl)return NULL;fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);fsl->mode = mode;fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;/* Set eSPI BRG clock source */get_sys_info(&sysinfo);spibrg = sysinfo.freq_systembus / 2;fsl->div16 = 0;if ((spibrg / max_hz) > 32) {fsl->div16 = ESPI_CSMODE_DIV16;pm = spibrg / (max_hz * 16 * 2);if (pm > 16) {pm = 16;debug("Requested speed is too low: %dHz, %ld Hz "
"is used.\n", max_hz, spibrg / (32 *16));
}} elsepm = spibrg / (max_hz * 2);if (pm)pm--;fsl->pm = pm;if (fsl->div16)spi_freq = spibrg / ((pm + 1) * 2 * 16);elsespi_freq = spibrg / ((pm + 1) * 2);/* set tx_timeout to 10 times of one espi FIFO entry go out */fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *ESPI_FIFO_WIDTH_BIT
* 10), spi_freq);return &fsl->slave;-}
-void spi_free_slave(struct spi_slave *slave) -{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);free(fsl);-}
-int spi_claim_bus(struct spi_slave *slave) +void fsl_spi_cs_activate(struct spi_slave *slave, uint cs) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave); ccsr_espi_t *espi = fsl->espi;
unsigned char pm = fsl->pm;unsigned int cs = slave->cs;unsigned int mode = fsl->mode;unsigned int div16 = fsl->div16;int i;debug("%s: bus:%i cs:%i\n", __func__, slave->bus, cs);/* Enable eSPI interface */out_be32(&espi->mode, ESPI_MODE_RXTHR(3)| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */out_be32(&espi->mask, 0x00000000); /* Mask all eSPIinterrupts */
/* Init CS mode interface */for (i = 0; i < ESPI_MAX_CS_NUM; i++)out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16| ESPI_CSMODE_CI_INACTIVEHIGH |ESPI_CSMODE_CP_BEGIN_EDGCLK
| ESPI_CSMODE_REV_MSB_FIRST |ESPI_CSMODE_LEN(0xF)));
/* Set eSPI BRG clock source */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_PM(pm) | div16);/* Set eSPI mode */if (mode & SPI_CPHA)out_be32(&espi->csmode[cs],in_be32(&espi->csmode[cs])
| ESPI_CSMODE_CP_BEGIN_EDGCLK);if (mode & SPI_CPOL)out_be32(&espi->csmode[cs],in_be32(&espi->csmode[cs])
| ESPI_CSMODE_CI_INACTIVEHIGH);/* Character bit order: msb first */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_REV_MSB_FIRST);/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_LEN(7));
unsigned int com = 0;size_t data_len = fsl->data_len;
return 0;
com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));com |= ESPI_COM_CS(cs);com |= ESPI_COM_TRANLEN(data_len - 1);out_be32(&espi->com, com);}
-void spi_release_bus(struct spi_slave *slave) +void fsl_spi_cs_deactivate(struct spi_slave *slave) {
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);ccsr_espi_t *espi = fsl->espi;/* clear the RXCNT and TXCNT */out_be32(&espi->mode, in_be32(&espi->mode) &(~ESPI_MODE_EN));
out_be32(&espi->mode, in_be32(&espi->mode) |ESPI_MODE_EN);
}
static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout) @@ -204,7 +125,8 @@ static void fsl_espi_tx(struct fsl_spi_slave *fsl, const
void *dout)
debug("***spi_xfer:...Tx timeout! event = %08x\n",event); }
-static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) +static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din,
unsigned int bytes){ ccsr_espi_t *espi = fsl->espi; unsigned int tmpdin, rx_times; @@ -236,10 +158,17 @@ static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes) return bytes; }
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void
*data_out,
void *data_in, unsigned long flags)+void espi_release_bus(struct fsl_spi_slave *fsl) {
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
/* Disable the SPI hardware */out_be32(&fsl->espi->mode,in_be32(&fsl->espi->mode) & (~ESPI_MODE_EN)); }+int espi_xfer(struct fsl_spi_slave *fsl, uint cs, unsigned int bitlen,
const void *data_out, void *data_in, unsigned long+flags) {
struct spi_slave *slave = &fsl->slave; ccsr_espi_t *espi = fsl->espi; unsigned int event, rx_bytes; const void *dout = NULL;@@ -258,13 +187,14 @@ int spi_xfer(struct spi_slave *slave, unsigned int
bitlen, const void *data_out,
max_tran_len = fsl->max_transfer_length; switch (flags) { case SPI_XFER_BEGIN:
cmd_len = fsl->cmd_len = data_len;
cmd_len = data_len;fsl->cmd_len = cmd_len; memcpy(cmd_buf, data_out, cmd_len); return 0; case 0: case SPI_XFER_END: if (bitlen == 0) {
spi_cs_deactivate(slave);
fsl_spi_cs_deactivate(slave); return 0; } buf_len = 2 * cmd_len + min(data_len,(size_t)max_tran_len); @@ -304,7 +234,7 @@ int spi_xfer(struct spi_slave
*slave, unsigned int bitlen, const void *data_out,
num_blks = DIV_ROUND_UP(tran_len + cmd_len, 4); num_bytes = (tran_len + cmd_len) % 4; fsl->data_len = tran_len + cmd_len;
spi_cs_activate(slave);
fsl_spi_cs_activate(slave, cs); /* Clear all eSPI events */ out_be32(&espi->event , 0xffffffff); @@ -347,37+277,304 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const
void *data_out,
*(int *)buffer += tran_len; } }
spi_cs_deactivate(slave);
fsl_spi_cs_deactivate(slave); } free(buffer); return 0;}
+void espi_claim_bus(struct fsl_spi_slave *fsl, unsigned int cs) {
ccsr_espi_t *espi = fsl->espi;unsigned char pm = fsl->pm;unsigned int mode = fsl->mode;unsigned int div16 = fsl->div16;int i;/* Enable eSPI interface */out_be32(&espi->mode, ESPI_MODE_RXTHR(3)| ESPI_MODE_TXTHR(4) | ESPI_MODE_EN);out_be32(&espi->event, 0xffffffff); /* Clear all eSPI events */out_be32(&espi->mask, 0x00000000); /* Mask all eSPI- interrupts */
/* Init CS mode interface */for (i = 0; i < ESPI_MAX_CS_NUM; i++)out_be32(&espi->csmode[i], ESPI_CSMODE_INIT_VAL);out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs]) &~(ESPI_CSMODE_PM(0xF) | ESPI_CSMODE_DIV16| ESPI_CSMODE_CI_INACTIVEHIGH |ESPI_CSMODE_CP_BEGIN_EDGCLK
| ESPI_CSMODE_REV_MSB_FIRST |ESPI_CSMODE_LEN(0xF)));
/* Set eSPI BRG clock source */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_PM(pm) | div16);/* Set eSPI mode */if (mode & SPI_CPHA)out_be32(&espi->csmode[cs],in_be32(&espi->csmode[cs])
| ESPI_CSMODE_CP_BEGIN_EDGCLK);if (mode & SPI_CPOL)out_be32(&espi->csmode[cs],in_be32(&espi->csmode[cs])
| ESPI_CSMODE_CI_INACTIVEHIGH);/* Character bit order: msb first */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_REV_MSB_FIRST);/* Character length in bits, between 0x3~0xf, i.e. 4bits~16bits */out_be32(&espi->csmode[cs], in_be32(&espi->csmode[cs])| ESPI_CSMODE_LEN(7)); }+void espi_setup_slave(struct fsl_spi_slave *fsl) {
unsigned int max_hz;sys_info_t sysinfo;unsigned long spibrg = 0;unsigned long spi_freq = 0;unsigned char pm = 0;max_hz = fsl->speed_hz;get_sys_info(&sysinfo);spibrg = sysinfo.freq_systembus / 2;fsl->div16 = 0;if ((spibrg / max_hz) > 32) {fsl->div16 = ESPI_CSMODE_DIV16;pm = spibrg / (max_hz * 16 * 2);if (pm > 16) {pm = 16;debug("max_hz is too low: %d Hz, %ld Hz isused.\n",
max_hz, spibrg / (32 * 16));}} else {pm = spibrg / (max_hz * 2);}if (pm)pm--;fsl->pm = pm;if (fsl->div16)spi_freq = spibrg / ((pm + 1) * 2 * 16);elsespi_freq = spibrg / ((pm + 1) * 2);/* set tx_timeout to 10 times of one espi FIFO entry go out */fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND *ESPI_FIFO_WIDTH_BIT
* 10), spi_freq);/* Set eSPI BRGclock
+source */ }
+#ifndef CONFIG_DM_SPI int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus == 0 && cs < ESPI_MAX_CS_NUM; }
-void spi_cs_activate(struct spi_slave *slave) +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int+mode) {
struct fsl_spi_slave *fsl;if (!spi_cs_is_valid(bus, cs))return NULL;fsl = spi_alloc_slave(struct fsl_spi_slave, bus, cs);if (!fsl)return NULL;fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);fsl->mode = mode;fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;fsl->speed_hz = max_hz;espi_setup_slave(fsl);return &fsl->slave;+}
+void spi_free_slave(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
ccsr_espi_t *espi = fsl->espi;unsigned int com = 0;size_t data_len = fsl->data_len;com &= ~(ESPI_COM_CS(0x3) | ESPI_COM_TRANLEN(0xFFFF));com |= ESPI_COM_CS(slave->cs);com |= ESPI_COM_TRANLEN(data_len - 1);out_be32(&espi->com, com);
free(fsl);}
-void spi_cs_deactivate(struct spi_slave *slave) +int spi_claim_bus(struct spi_slave *slave) { struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
ccsr_espi_t *espi = fsl->espi;/* clear the RXCNT and TXCNT */out_be32(&espi->mode, in_be32(&espi->mode) &(~ESPI_MODE_EN));
out_be32(&espi->mode, in_be32(&espi->mode) |ESPI_MODE_EN);
espi_claim_bus(fsl, slave->cs);return 0;+}
+void spi_release_bus(struct spi_slave *slave) {
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);espi_release_bus(fsl);+}
+int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags) {struct fsl_spi_slave *fsl = (struct fsl_spi_slave *)slave;return espi_xfer(fsl, slave->cs, bitlen, dout, din, flags); }+#else static void __espi_set_speed(struct fsl_spi_slave *fsl) {
espi_setup_slave(fsl);/* Set eSPI BRG clock source */out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])| ESPI_CSMODE_PM(fsl->pm) | fsl->div16); }+static void __espi_set_mode(struct fsl_spi_slave *fsl) {
/* Set eSPI mode */if (fsl->mode & SPI_CPHA)out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])|ESPI_CSMODE_CP_BEGIN_EDGCLK);
if (fsl->mode & SPI_CPOL)out_be32(&fsl->espi->csmode[fsl->cs],in_be32(&fsl->espi->csmode[fsl->cs])|ESPI_CSMODE_CI_INACTIVEHIGH); }
+static int fsl_espi_claim_bus(struct udevice *dev) {
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);espi_claim_bus(fsl, fsl->cs);return 0;+}
+static int fsl_espi_release_bus(struct udevice *dev) {
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);espi_release_bus(fsl);return 0;+}
+static int fsl_espi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din, unsigned long+flags) {
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);return espi_xfer(fsl, fsl->cs, bitlen, dout, din, flags); }+static int fsl_espi_set_speed(struct udevice *bus, uint speed) {
struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s speed %u\n", __func__, speed);fsl->speed_hz = speed;__espi_set_speed(fsl);return 0;+}
+static int fsl_espi_set_mode(struct udevice *bus, uint mode) {
struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s mode %u\n", __func__, mode);fsl->mode = mode;__espi_set_mode(fsl);return 0;}
+static int fsl_espi_child_pre_probe(struct udevice *dev) {
struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);
struct udevice *bus = dev->parent;struct fsl_spi_slave *fsl = dev_get_priv(bus);debug("%s cs %u\n", __func__, slave_plat->cs);fsl->cs = slave_plat->cs;return 0;+}
+static int fsl_espi_probe(struct udevice *bus) {
struct fsl_espi_platdata *plat = dev_get_platdata(bus);struct fsl_spi_slave *fsl = dev_get_priv(bus);fsl->espi = (ccsr_espi_t *)((u32)plat->regs_addr);fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;fsl->speed_hz = plat->speed_hz;debug("%s probe done, bus-num %d.\n", bus->name, bus->seq);return 0;+}
+static const struct dm_spi_ops fsl_espi_ops = {
.claim_bus = fsl_espi_claim_bus,.release_bus = fsl_espi_release_bus,.xfer = fsl_espi_xfer,.set_speed = fsl_espi_set_speed,.set_mode = fsl_espi_set_mode,+};
+#if CONFIG_IS_ENABLED(OF_CONTROL)
&& !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int fsl_espi_ofdata_to_platdata(struct udevice *bus) {
fdt_addr_t addr;struct fsl_espi_platdata *plat = bus->platdata;const void *blob = gd->fdt_blob;int node = dev_of_offset(bus);addr = dev_read_addr(bus);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->regs_addr = lower_32_bits(addr);plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",FSL_ESPI_DEFAULT_SCK_FREQ);
debug("ESPI: regs=%p, max-frequency=%d\n",&plat->regs_addr, plat->speed_hz);return 0;+}
+static const struct udevice_id fsl_espi_ids[] = {
{ .compatible = "fsl,mpc8536-espi" },{ }+}; +#endif
+U_BOOT_DRIVER(fsl_espi) = {
.name = "fsl_espi",.id = UCLASS_SPI,+#if CONFIG_IS_ENABLED(OF_CONTROL)
&& !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = fsl_espi_ids,.ofdata_to_platdata = fsl_espi_ofdata_to_platdata, #endif.ops = &fsl_espi_ops,.platdata_auto_alloc_size = sizeof(struct fsl_espi_platdata),.priv_auto_alloc_size = sizeof(struct fsl_spi_slave),.probe = fsl_espi_probe,.child_pre_probe = fsl_espi_child_pre_probe, }; #endifdiff --git a/include/dm/platform_data/fsl_espi.h b/include/dm/platform_data/fsl_espi.h new file mode 100644 index 0000000..812933f --- /dev/null +++ b/include/dm/platform_data/fsl_espi.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright 2019 NXP
- */
+#ifndef __fsl_espi_h +#define __fsl_espi_h
+struct fsl_espi_platdata {
uint flags;uint speed_hz;uint num_chipselect;fdt_addr_t regs_addr;+};
+#endif /* __fsl_espi_h */
2.9.5
On Wed, 2019-08-21 at 01:19 +0000, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月20日 19:04 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, 2019-08-20 at 06:59 +0000, Xiaowei Bao wrote:
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
These are not the only problems with this driver it is borken for anything but loading small amount of data from SPI NOR flash. Look at spi_xfer: overuse of malloc/memcpy misuse of word size(always 32 bits) making proper of ESPI_EV_RNE/ESPI_EV_TNF impossible. random test of 0x0b: memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; *(int *)buffer += tran_len; }
I think fixing the driver to work properly first is preferable to DM conversion.
Thanks a lot for your comments, in fact, these code exist all the time, I never modify this part code, and I have verified the SPI flash use 4K data, the test result is ok, I will check and analyze this part code, and give the reply later, thanks.
Yes, this code has been borken for years and like I said, it only works for SPI NOR flash which is what you tested. Try a simple SPI device, reading and writing registers.
Here is an old hack for loading FPGAs using ESPI_COM_TO, hopefully this can be of some use: https://patchwork.ozlabs.org/patch/330242/
In short, the inner working of spi_xfer() needs a full rewrite, using the proper SPI word size, you have no chance of supporting SPI_LSB_FIRST without correct word size.
Jocke
Jocke
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月21日 15:52 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Wed, 2019-08-21 at 01:19 +0000, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月20日 19:04 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika
Gupta
ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, 2019-08-20 at 06:59 +0000, Xiaowei Bao wrote:
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
These are not the only problems with this driver it is borken for anything but loading small amount of data from SPI NOR flash. Look at spi_xfer: overuse of malloc/memcpy misuse of word size(always 32 bits) making proper of ESPI_EV_RNE/ESPI_EV_TNF impossible. random test of 0x0b: memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; *(int *)buffer += tran_len; }
I think fixing the driver to work properly first is preferable to DM
conversion.
Thanks a lot for your comments, in fact, these code exist all the time, I never modify this part code, and I have verified the SPI flash use 4K data, the test result is ok, I will check and analyze this part code, and
give the reply later, thanks.
Yes, this code has been borken for years and like I said, it only works for SPI NOR flash which is what you tested. Try a simple SPI device, reading and writing registers.
Here is an old hack for loading FPGAs using ESPI_COM_TO, hopefully this can be of some use: https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch work.ozlabs.org%2Fpatch%2F330242%2F&data=02%7C01%7Cxiaowei.b ao%40nxp.com%7Cbb03e40adaf14ddabb3308d7260c624a%7C686ea1d3bc2 b4c6fa92cd99c5c301635%7C0%7C0%7C637019706960729747&sdata= LBnGwExukwfx4Txln7gbC797CK0Nuu1Q%2BG8iK4lCR4M%3D&reserved =0
In short, the inner working of spi_xfer() needs a full rewrite, using the proper SPI word size, you have no chance of supporting SPI_LSB_FIRST without correct word size.
Thanks a lot, I think I need to do another new patch which reimplement the xfer function, This is better, because this issue fix should not in DM patch, I will submit another new patch to fix this issue, but maybe spend some time, because I am not very clear about the FSL ESPI driver, and the verification will be a problem, because I don't find other SPI device except SPI flash device in our RDB or QDS board, but I am going to do this.
Jocke
Jocke
On Wed, 2019-08-21 at 09:46 +0000, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月21日 15:52 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Wed, 2019-08-21 at 01:19 +0000, Xiaowei Bao wrote:
-----Original Message----- From: Joakim Tjernlund Joakim.Tjernlund@infinera.com Sent: 2019年8月20日 19:04 To: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika
Gupta
ruchika.gupta@nxp.com; Xiaowei Bao xiaowei.bao@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; wd@denx.de; jagan@amarulasolutions.com Cc: u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 2/5] dm: spi: Convert Freescale ESPI driver to driver model
On Tue, 2019-08-20 at 06:59 +0000, Xiaowei Bao wrote:
From: Chuanhua Han chuanhua.han@nxp.com
Modify the Freescale ESPI driver to support the driver model. Also resolved the following problems:
===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI. Please update the board before v2019.04 for no dm conversion and v2019.07 for partially dm converted drivers. Failure to update can lead to driver/board removal See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This
board does
not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
These are not the only problems with this driver it is borken for anything but loading small amount of data from SPI NOR flash. Look at spi_xfer: overuse of malloc/memcpy misuse of word size(always 32 bits) making proper of ESPI_EV_RNE/ESPI_EV_TNF impossible. random test of 0x0b: memcpy(data_in, buffer + 2 * cmd_len, tran_len); if (*buffer == 0x0b) { data_in += tran_len; data_len -= tran_len; *(int *)buffer += tran_len; }
I think fixing the driver to work properly first is preferable to DM
conversion.
Thanks a lot for your comments, in fact, these code exist all the time, I never modify this part code, and I have verified the SPI flash use 4K data, the test result is ok, I will check and analyze this part code, and
give the reply later, thanks.
Yes, this code has been borken for years and like I said, it only works for SPI NOR flash which is what you tested. Try a simple SPI device, reading and writing registers.
Here is an old hack for loading FPGAs using ESPI_COM_TO, hopefully this can be of some use: https://patch work.ozlabs.org%2Fpatch%2F330242%2F&data=02%7C01%7Cxiaowei.b ao%40nxp.com%7Cbb03e40adaf14ddabb3308d7260c624a%7C686ea1d3bc2 b4c6fa92cd99c5c301635%7C0%7C0%7C637019706960729747&sdata= LBnGwExukwfx4Txln7gbC797CK0Nuu1Q%2BG8iK4lCR4M%3D&reserved =0
In short, the inner working of spi_xfer() needs a full rewrite, using the proper SPI word size, you have no chance of supporting SPI_LSB_FIRST without correct word size.
Thanks a lot, I think I need to do another new patch which reimplement the xfer function, This is better, because this issue fix should not in DM patch, I will submit another new patch to fix this issue, but maybe spend some time, because I am not very clear about the FSL ESPI driver, and the verification will be a problem, because I don't find other SPI device except SPI flash device in our RDB or QDS board, but I am going to do this.
Thanks, I think random access(read/write) to SPI NOR flash will be enough for testing. It won't be any worse than today as it is broken already.
Jocke
Jocke
Jocke
From: Chuanhua Han chuanhua.han@nxp.com
Add espi controller node to support t2080.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v5: - No change. Changes in v4: - No change. Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - No change.
arch/powerpc/dts/t2080.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/powerpc/dts/t2080.dtsi b/arch/powerpc/dts/t2080.dtsi index d2bebb0..e3970d3 100644 --- a/arch/powerpc/dts/t2080.dtsi +++ b/arch/powerpc/dts/t2080.dtsi @@ -69,6 +69,16 @@ voltage-ranges = <1800 1800 3300 3300>; };
+ espi0: spi@110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,mpc8536-espi"; + reg = <0x110000 0x1000>; + interrupts = <53 0x2 0 0>; + fsl,espi-num-chipselects = <4>; + status = "disabled"; + }; + usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>;
From: Chuanhua Han chuanhua.han@nxp.com
Add espi slave nodes to support t2080qds.
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v5: - No change. Changes in v4: - Modify the spi-max-frequency attribute value of the flash@x node of the device tree. Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - No change.
arch/powerpc/dts/t2080qds.dts | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+)
diff --git a/arch/powerpc/dts/t2080qds.dts b/arch/powerpc/dts/t2080qds.dts index 1819a08..f9e786b 100644 --- a/arch/powerpc/dts/t2080qds.dts +++ b/arch/powerpc/dts/t2080qds.dts @@ -14,4 +14,37 @@ #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; + + aliases { + spi0 = &espi0; + }; +}; + +&espi0 { + + status = "okay"; + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; /* 16MB */ + reg = <0>; + spi-max-frequency = <10000000>; + }; + + flash@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25wf040", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <10000000>; + }; + + flash@2 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "eon,en25s64", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <10000000>; + }; + };
From: Chuanhua Han chuanhua.han@nxp.com
This patch is to enable espi DM for T2080QDS in uboot
Signed-off-by: Chuanhua Han chuanhua.han@nxp.com --- Changes in v5: - No change. Changes in v4: - No change. Changes in v3: - Add a cover-letter for this patch set. Changes in v2: - No change.
configs/T2080QDS_NAND_defconfig | 2 ++ configs/T2080QDS_SDCARD_defconfig | 2 ++ configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++ configs/T2080QDS_SPIFLASH_defconfig | 2 ++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2080QDS_defconfig | 2 ++ 6 files changed, 12 insertions(+)
diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index f7dfb94..91030e1 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -75,3 +75,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index a89c410..f7d39d4 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -72,3 +72,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 6996f85..912e6b2 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -62,3 +62,5 @@ CONFIG_USB_STORAGE=y CONFIG_RSA=y CONFIG_SPL_RSA=y CONFIG_RSA_SOFTWARE_EXP=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 101e23d..5d2e3ce 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -73,3 +73,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 1346d5e..437d5cc 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -52,3 +52,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index bcbd276..1ed592e 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -59,3 +59,5 @@ CONFIG_FSL_ESPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline? Do I need to depend on your patches? If yes, please provide the full patches link, I can't see the contents of this set of patches.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
From: Chuanhua Han chuanhua.han@nxp.com
This patch solves the problem that spiboot cannot be performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif +
Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com Signed-off-by: Chuanhua Han chuanhua.han@nxp.com
Changes in v5:
- No change.
Changes in v4:
- No change.
Changes in v3:
- Add a cover-letter for this patch set.
Changes in v2:
- No change.
include/config_uncmd_spl.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,6 +15,7 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Tue, 20 Aug 2019 09:00:40 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:14 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
Hi Xiaowei,
> From: Chuanhua Han chuanhua.han@nxp.com > > This patch solves the problem that spiboot cannot be > performed in non-DM SPL.
I've posted recently a set of patches to move setting of DM_SPI_FLASH to Kconfig: https://patchwork.ozlabs.org/cover/1146494/
Please rebase your work on top of it.
Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif
The whole point is to avoid adding the above code.
The rationale for this can be found in the commit message: https://patchwork.ozlabs.org/patch/1146375/
> > Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com > Signed-off-by: Chuanhua Han chuanhua.han@nxp.com > --- > Changes in v5: > - No change. > Changes in v4: > - No change. > Changes in v3: > - Add a cover-letter for this patch set. > Changes in v2: > - No change. > > include/config_uncmd_spl.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/config_uncmd_spl.h > b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 > --- a/include/config_uncmd_spl.h > +++ b/include/config_uncmd_spl.h > @@ -15,6 +15,7 @@ > #undef CONFIG_DM_GPIO > #undef CONFIG_DM_I2C > #undef CONFIG_DM_SPI > +#undef CONFIG_DM_SPI_FLASH > #endif > > #undef CONFIG_DM_WARN
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 17:50 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 09:00:40 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
> -----Original Message----- > From: Lukasz Majewski lukma@denx.de > Sent: 2019年8月20日 15:14 > To: Xiaowei Bao xiaowei.bao@nxp.com > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
> shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan > Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM > flash for non-DM SPL > > Hi Xiaowei, > > > From: Chuanhua Han chuanhua.han@nxp.com > > > > This patch solves the problem that spiboot cannot be > > performed in non-DM SPL. > > I've posted recently a set of patches to move setting of > DM_SPI_FLASH to Kconfig: > https://patchwork.ozlabs.org/cover/1146494/ > > Please rebase your work on top of it. Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
Do I need to depend on your patches?
It would be best to avoid duplicating the effort.
If yes, please provide the full patches link, I can't see the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif
The whole point is to avoid adding the above code.
The rationale for this can be found in the commit message: https://patchwork.ozlabs.org/patch/1146375/
Hi Lukasz, thanks for your comments, ask a question, I modify my driver like this: diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fd5ac97..54be036 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -367,6 +367,7 @@ void espi_setup_slave(struct fsl_spi_slave *fsl) * 10), spi_freq);/* Set eSPI BRG clock source */ }
#ifndef CONFIG_DM_SPI +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) {
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7a1c580..cf53e54 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y
When I compile the driver with SPL mode, the DM or non DM mode cod will be compiled together, I think CONFIG_IS_ENABLED(DM_SPI) is 0 or 1, so the DM code or non DM code will be compiled, but not both, this make me confused, do I miss something, could you tell me the reason? Thanks a lot.
> > > > > Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com > > Signed-off-by: Chuanhua Han chuanhua.han@nxp.com > > --- > > Changes in v5: > > - No change. > > Changes in v4: > > - No change. > > Changes in v3: > > - Add a cover-letter for this patch set. > > Changes in v2: > > - No change. > > > > include/config_uncmd_spl.h | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/include/config_uncmd_spl.h > > b/include/config_uncmd_spl.h index c2f9735..da94b3d 100644 > > --- a/include/config_uncmd_spl.h > > +++ b/include/config_uncmd_spl.h > > @@ -15,6 +15,7 @@ > > #undef CONFIG_DM_GPIO > > #undef CONFIG_DM_I2C > > #undef CONFIG_DM_SPI > > +#undef CONFIG_DM_SPI_FLASH > > #endif > > > > #undef CONFIG_DM_WARN > > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director:
Wolfgang
> Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
On Thu, 22 Aug 2019 01:56:48 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 17:50 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 09:00:40 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 15:43 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
> > -----Original Message----- > > From: Lukasz Majewski lukma@denx.de > > Sent: 2019年8月20日 15:14 > > To: Xiaowei Bao xiaowei.bao@nxp.com > > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu > > shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; > > Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> > Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable > > SPI DM flash for non-DM SPL > > > > Hi Xiaowei, > > > > > From: Chuanhua Han chuanhua.han@nxp.com > > > > > > This patch solves the problem that spiboot cannot be > > > performed in non-DM SPL. > > > > I've posted recently a set of patches to move setting of > > DM_SPI_FLASH to Kconfig: > > https://patchwork.ozlabs.org/cover/1146494/ > > > > Please rebase your work on top of it. > Did this set of patches merge to the u-boot mainline?
Those patches were not yet accepted to mainline.
> Do I need to > depend on your patches?
It would be best to avoid duplicating the effort.
> If yes, please provide the full patches link, I can't see > the contents of this set of patches.
When you open the link: https://patchwork.ozlabs.org/cover/1146494/
On top left you have: "Related" -> "show"
After clicking on it you will see the list of patches.
You may also want to use "Series" on top right and download the whole patch series.
I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif
The whole point is to avoid adding the above code.
The rationale for this can be found in the commit message: https://patchwork.ozlabs.org/patch/1146375/
Hi Lukasz, thanks for your comments, ask a question, I modify my driver like this: diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fd5ac97..54be036 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -367,6 +367,7 @@ void espi_setup_slave(struct fsl_spi_slave *fsl) * 10), spi_freq);/* Set eSPI BRG clock source */ }
#ifndef CONFIG_DM_SPI +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) {
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7a1c580..cf53e54 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y
When I compile the driver with SPL mode, the DM or non DM mode cod will be compiled together, I think CONFIG_IS_ENABLED(DM_SPI) is 0 or 1, so the DM code or non DM code will be compiled, but not both, this make me confused, do I miss something, could you tell me the reason? Thanks a lot.
So the CONFIG_IS_ENABLED(FOO) is true if:
1. The CONFIG_FOO is defined in Kconfig files (if it is defined in ./include/configs/<board.h> then CONFIG_IS_ENABLED will return false, which is wrong).
2. The CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined CONFIG_FOO
3. CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined CONFIG_SPL_FOO
So the CONFIG_IS_ENABLED(FOO) shall be used in conjunction with CONFIG_DM_FOO (SPI in your case).
> > > > > > > > Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com > > > Signed-off-by: Chuanhua Han chuanhua.han@nxp.com > > > --- > > > Changes in v5: > > > - No change. > > > Changes in v4: > > > - No change. > > > Changes in v3: > > > - Add a cover-letter for this patch set. > > > Changes in v2: > > > - No change. > > > > > > include/config_uncmd_spl.h | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/include/config_uncmd_spl.h > > > b/include/config_uncmd_spl.h index c2f9735..da94b3d > > > 100644 --- a/include/config_uncmd_spl.h > > > +++ b/include/config_uncmd_spl.h > > > @@ -15,6 +15,7 @@ > > > #undef CONFIG_DM_GPIO > > > #undef CONFIG_DM_I2C > > > #undef CONFIG_DM_SPI > > > +#undef CONFIG_DM_SPI_FLASH > > > #endif > > > > > > #undef CONFIG_DM_WARN > > > > > > > > Best regards, > > > > Lukasz Majewski > > > > -- > > > > DENX Software Engineering GmbH, Managing Director: > >
Wolfgang
> > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > > (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月23日 4:48 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Thu, 22 Aug 2019 01:56:48 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 17:50 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 09:00:40 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
> -----Original Message----- > From: Lukasz Majewski lukma@denx.de > Sent: 2019年8月20日 15:43 > To: Xiaowei Bao xiaowei.bao@nxp.com > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
> shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan > Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM > flash for non-DM SPL > > On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao > xiaowei.bao@nxp.com wrote: > > > > -----Original Message----- > > > From: Lukasz Majewski lukma@denx.de > > > Sent: 2019年8月20日 15:14 > > > To: Xiaowei Bao xiaowei.bao@nxp.com > > > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
> Liu > > > shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > > > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > > > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; > > > Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> > > Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable > > > SPI DM flash for non-DM SPL > > > > > > Hi Xiaowei, > > > > > > > From: Chuanhua Han chuanhua.han@nxp.com > > > > > > > > This patch solves the problem that spiboot cannot be > > > > performed in non-DM SPL. > > > > > > I've posted recently a set of patches to move setting of > > > DM_SPI_FLASH to Kconfig: > > > https://patchwork.ozlabs.org/cover/1146494/ > > > > > > Please rebase your work on top of it. > > Did this set of patches merge to the u-boot mainline? > > Those patches were not yet accepted to mainline. > > > Do I need to > > depend on your patches? > > It would be best to avoid duplicating the effort. > > > If yes, please provide the full patches link, I can't see > > the contents of this set of patches. > > When you open the link: > https://patchwork.ozlabs.org/cover/1146494/ > > On top left you have: > "Related" -> "show" > > After clicking on it you will see the list of patches. > > You may also want to use "Series" on top right and download > the whole patch series. I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif
The whole point is to avoid adding the above code.
The rationale for this can be found in the commit message: https://patchwork.ozlabs.org/patch/1146375/
Hi Lukasz, thanks for your comments, ask a question, I modify my driver like this: diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fd5ac97..54be036 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -367,6 +367,7 @@ void espi_setup_slave(struct fsl_spi_slave *fsl) * 10), spi_freq);/* Set eSPI BRG
clock
source */ }
#ifndef CONFIG_DM_SPI +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) {
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7a1c580..cf53e54 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y
When I compile the driver with SPL mode, the DM or non DM mode cod will be compiled together, I think CONFIG_IS_ENABLED(DM_SPI) is 0 or 1, so the DM code or non DM code will be compiled, but not both, this make me confused, do I miss something, could you tell me the reason? Thanks a lot.
So the CONFIG_IS_ENABLED(FOO) is true if:
- The CONFIG_FOO is defined in Kconfig files (if it is defined
in ./include/configs/<board.h> then CONFIG_IS_ENABLED will return false, which is wrong).
- The CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined
CONFIG_FOO
- CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined
CONFIG_SPL_FOO
So the CONFIG_IS_ENABLED(FOO) shall be used in conjunction with CONFIG_DM_FOO (SPI in your case).
Thanks a lot, got it.
> > > > > > > > > > > > Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com > > > > Signed-off-by: Chuanhua Han chuanhua.han@nxp.com > > > > --- > > > > Changes in v5: > > > > - No change. > > > > Changes in v4: > > > > - No change. > > > > Changes in v3: > > > > - Add a cover-letter for this patch set. > > > > Changes in v2: > > > > - No change. > > > > > > > > include/config_uncmd_spl.h | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/include/config_uncmd_spl.h > > > > b/include/config_uncmd_spl.h index c2f9735..da94b3d > > > > 100644 --- a/include/config_uncmd_spl.h > > > > +++ b/include/config_uncmd_spl.h > > > > @@ -15,6 +15,7 @@ > > > > #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C
#undef
> > > > CONFIG_DM_SPI > > > > +#undef CONFIG_DM_SPI_FLASH > > > > #endif > > > > > > > > #undef CONFIG_DM_WARN > > > > > > > > > > > > Best regards, > > > > > > Lukasz Majewski > > > > > > -- > > > > > > DENX Software Engineering GmbH, Managing Director: > > >
Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > > > (+49)-8142-66989-80 Email: lukma@denx.de > > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director:
Wolfgang
> Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Hi Lukasz,
My patches depends on your patches https://patchwork.ozlabs.org/project/uboot/list/?series=129069, do you have plan to update it? I saw that the status is "changes required", any comments?
Thanks Xiaowei
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月23日 4:48 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Thu, 22 Aug 2019 01:56:48 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 17:50 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com; Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 09:00:40 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
-----Original Message----- From: Lukasz Majewski lukma@denx.de Sent: 2019年8月20日 16:20 To: Xiaowei Bao xiaowei.bao@nxp.com Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
shengzhou.liu@nxp.com; jagan@amarulasolutions.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Chuanhua Han chuanhua.han@nxp.com Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM flash for non-DM SPL
On Tue, 20 Aug 2019 07:51:18 +0000 Xiaowei Bao xiaowei.bao@nxp.com wrote:
> -----Original Message----- > From: Lukasz Majewski lukma@denx.de > Sent: 2019年8月20日 15:43 > To: Xiaowei Bao xiaowei.bao@nxp.com > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
Liu
> shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; Pan > Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable SPI DM > flash for non-DM SPL > > On Tue, 20 Aug 2019 07:27:39 +0000 Xiaowei Bao > xiaowei.bao@nxp.com wrote: > > > > -----Original Message----- > > > From: Lukasz Majewski lukma@denx.de > > > Sent: 2019年8月20日 15:14 > > > To: Xiaowei Bao xiaowei.bao@nxp.com > > > Cc: wd@denx.de; Ruchika Gupta ruchika.gupta@nxp.com;
Shengzhou
> Liu > > > shengzhou.liu@nxp.com; jagan@amarulasolutions.com; > > > Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; > > > u-boot@lists.denx.de; Jiafei Pan jiafei.pan@nxp.com; > > > Pan Jiafei Jiafei.Pan@freescale.com; Chuanhua Han
> > > Subject: Re: [U-Boot] [PATCH v5 1/5] spl: dm: disable > > > SPI DM flash for non-DM SPL > > > > > > Hi Xiaowei, > > > > > > > From: Chuanhua Han chuanhua.han@nxp.com > > > > > > > > This patch solves the problem that spiboot cannot be > > > > performed in non-DM SPL. > > > > > > I've posted recently a set of patches to move setting of > > > DM_SPI_FLASH to Kconfig: > > > https://patchwork.ozlabs.org/cover/1146494/ > > > > > > Please rebase your work on top of it. > > Did this set of patches merge to the u-boot mainline? > > Those patches were not yet accepted to mainline. > > > Do I need to > > depend on your patches? > > It would be best to avoid duplicating the effort. > > > If yes, please provide the full patches link, I can't see > > the contents of this set of patches. > > When you open the link: > https://patchwork.ozlabs.org/cover/1146494/ > > On top left you have: > "Related" -> "show" > > After clicking on it you will see the list of patches. > > You may also want to use "Series" on top right and download > the whole patch series. I have check these set of patches, it don't impact my patches, my patches implemented the ESPI DM driver of POWERPC.
But you add:
+#undef CONFIG_DM_SPI_FLASH
for SPL, Which is problematic as explained in the patch set.
Can I modify the patches like this? diff --git a/include/config_uncmd_spl.h b/include/config_uncmd_spl.h index da94b3d..c2f9735 100644 --- a/include/config_uncmd_spl.h +++ b/include/config_uncmd_spl.h @@ -15,7 +15,6 @@ #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C #undef CONFIG_DM_SPI -#undef CONFIG_DM_SPI_FLASH #endif
#undef CONFIG_DM_WARN diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 98bb334..b45ec4a 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -10,6 +10,13 @@ #ifndef __T208xQDS_H #define __T208xQDS_H
+/* SPI Flash Configs */ +#if defined(CONFIG_SPL_BUILD) +#undef CONFIG_DM_SPI +#undef CONFIG_DM_SPI_FLASH +#undef CONFIG_SPI_FLASH_MTD +#endif
The whole point is to avoid adding the above code.
The rationale for this can be found in the commit message: https://patchwork.ozlabs.org/patch/1146375/
Hi Lukasz, thanks for your comments, ask a question, I modify my driver like this: diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index fd5ac97..54be036 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -367,6 +367,7 @@ void espi_setup_slave(struct fsl_spi_slave *fsl) * 10), spi_freq);/* Set eSPI BRG
clock
source */ }
#ifndef CONFIG_DM_SPI +#if !CONFIG_IS_ENABLED(DM_SPI) int spi_cs_is_valid(unsigned int bus, unsigned int cs) {
diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 7a1c580..cf53e54 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -80,3 +80,5 @@ CONFIG_DM_SPI=y CONFIG_DM_SPI_FLASH=y +CONFIG_SPL_DM_SPI=y +CONFIG_SPL_DM_SPI_FLASH=y
When I compile the driver with SPL mode, the DM or non DM mode cod will be compiled together, I think CONFIG_IS_ENABLED(DM_SPI) is 0 or 1, so the DM code or non DM code will be compiled, but not both, this make me confused, do I miss something, could you tell me the reason? Thanks a lot.
So the CONFIG_IS_ENABLED(FOO) is true if:
- The CONFIG_FOO is defined in Kconfig files (if it is defined
in ./include/configs/<board.h> then CONFIG_IS_ENABLED will return false, which is wrong).
- The CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined
CONFIG_FOO
- CONFIG_IS_ENABLED(FOO) is true if in Kconfig you have defined
CONFIG_SPL_FOO
So the CONFIG_IS_ENABLED(FOO) shall be used in conjunction with CONFIG_DM_FOO (SPI in your case).
> > > > > > > > > > > > Signed-off-by: Pan Jiafei Jiafei.Pan@freescale.com > > > > Signed-off-by: Chuanhua Han chuanhua.han@nxp.com > > > > --- > > > > Changes in v5: > > > > - No change. > > > > Changes in v4: > > > > - No change. > > > > Changes in v3: > > > > - Add a cover-letter for this patch set. > > > > Changes in v2: > > > > - No change. > > > > > > > > include/config_uncmd_spl.h | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/include/config_uncmd_spl.h > > > > b/include/config_uncmd_spl.h index c2f9735..da94b3d > > > > 100644 --- a/include/config_uncmd_spl.h > > > > +++ b/include/config_uncmd_spl.h > > > > @@ -15,6 +15,7 @@ > > > > #undef CONFIG_DM_GPIO #undef CONFIG_DM_I2C
#undef
> > > > CONFIG_DM_SPI > > > > +#undef CONFIG_DM_SPI_FLASH > > > > #endif > > > > > > > > #undef CONFIG_DM_WARN > > > > > > > > > > > > Best regards, > > > > > > Lukasz Majewski > > > > > > -- > > > > > > DENX Software Engineering GmbH, Managing Director: > > >
Wolfgang
> > > Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > > > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > > > (+49)-8142-66989-80 Email: lukma@denx.de > > > > Best regards, > > Lukasz Majewski > > -- > > DENX Software Engineering GmbH, Managing Director:
Wolfgang
> Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 > Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: > (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director:
Wolfgang
Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
Best regards,
Lukasz Majewski
--
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: lukma@denx.de
participants (3)
-
Joakim Tjernlund -
Lukasz Majewski -
Xiaowei Bao