[U-Boot] [RFC PATCH 0/6] Move some config macros to Kconfig
Guys,
I try to move some config macros to Kconfig. This is a beginning. Please review this set and let me know.
[RFC PATCH 1/6] arm: Fix Kconfig for proper display menu [RFC PATCH 2/6] arm: Move FSL_LSCH2 FSL_LSCH3 to Kconfig [RFC PATCH 3/6] arm: Move MAX_CPUS to Kconfig [RFC PATCH 4/6] arm: Move SYS_FSL_IFC_BANK_COUNT to Kconfig [RFC PATCH 5/6] arm: Move FSL_HAS_DP_DDR and NUM_DDR_CONTROLLERS to [RFC PATCH 6/6] arm: Move SYS_FSL_SRDS_* and SYS_HAS_SERDES to Kconfig
York
Some config options should not have prompt. They are selected by choosing target.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 5 +++-- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++++++---- 2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 920eb4a..f0e7ae9 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,7 @@ config ARCH_LS1021A - bool "Freescale Layerscape LS1021A SoC" + bool select SYS_FSL_ERRATUM_A010315
config LS1_DEEP_SLEEP - bool "Freescale Layerscape 1 deep sleep" + bool "Deep sleep" + depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f8057ba..045261f 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,17 +1,20 @@ config ARCH_LS1012A - bool "Freescale Layerscape LS1012A SoC" + bool select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315
config ARCH_LS1043A - bool "Freescale Layerscape LS1043A SoC" + bool select SYS_FSL_ERRATUM_A010315
config ARCH_LS1046A - bool "Freescale Layerscape LS1046A SoC" + bool + +config ARCH_LS2080A + bool
config SYS_FSL_MMDC - bool "Freescale Multi Mode DDR Controller" + bool
config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Some config options should not have prompt. They are selected by choosing target.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 5 +++-- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++++++---- 2 files changed, 10 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/ls102xa/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 15 +++++++++++++++ include/configs/ls1012a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 2 -- 8 files changed, 27 insertions(+), 6 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1e4830a..43722bc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -729,6 +729,7 @@ config TARGET_VEXPRESS64_JUNO
config TARGET_LS2080A_EMU bool "Support ls2080a_emu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -739,6 +740,7 @@ config TARGET_LS2080A_EMU
config TARGET_LS2080A_SIMU bool "Support ls2080a_simu" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY help @@ -749,6 +751,7 @@ config TARGET_LS2080A_SIMU
config TARGET_LS2080AQDS bool "Support ls2080aqds" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL @@ -760,6 +763,7 @@ config TARGET_LS2080AQDS
config TARGET_LS2080ARDB bool "Support ls2080ardb" + select ARCH_LS2080A select ARM64 select ARMV8_MULTIENTRY select SUPPORT_SPL diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index f0e7ae9..2648416 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -2,6 +2,14 @@ config ARCH_LS1021A bool select SYS_FSL_ERRATUM_A010315
+menu "LS102xA architecture" + depends on ARCH_LS1021A + config LS1_DEEP_SLEEP bool "Deep sleep" depends on ARCH_LS1021A + +config SYS_FSL_ERRATUM_A010315 + bool "Workaround for PCIe erratum A010315" + +endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 045261f..5619e0d 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -1,20 +1,35 @@ config ARCH_LS1012A bool + select FSL_LSCH2 select SYS_FSL_MMDC select SYS_FSL_ERRATUM_A010315
config ARCH_LS1043A bool + select FSL_LSCH2 select SYS_FSL_ERRATUM_A010315
config ARCH_LS1046A bool + select FSL_LSCH2
config ARCH_LS2080A bool + select FSL_LSCH3 + +config FSL_LSCH2 + bool + +config FSL_LSCH3 + bool + +menu "Layerscape architecture" + depends on FSL_LSCH2 || FSL_LSCH3
config SYS_FSL_MMDC bool
config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315" + +endmenu diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 5fb6c47..1056755 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -8,7 +8,6 @@ #define __LS1012A_COMMON_H
#define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_GICV2
#define CONFIG_SYS_HAS_SERDES diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ed0e434..ac86c08 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -9,7 +9,6 @@
#define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_LS1043A #define CONFIG_MP #define CONFIG_SYS_FSL_CLK diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index 7c5e635..ec6c908 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -9,7 +9,6 @@
#define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH2 #define CONFIG_MP #define CONFIG_SYS_FSL_CLK #define CONFIG_GICV2 diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index 42d0298..d9eea09 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -9,7 +9,6 @@
#define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE -#define CONFIG_FSL_LSCH3 #define CONFIG_MP #define CONFIG_GICV3 #define CONFIG_FSL_TZPC_BP147 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index efa95f0..d717103 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1299,8 +1299,6 @@ CONFIG_FSL_LAW CONFIG_FSL_LAYERSCAPE CONFIG_FSL_LBC CONFIG_FSL_LINFLEXUART -CONFIG_FSL_LSCH2 -CONFIG_FSL_LSCH3 CONFIG_FSL_LS_PPA CONFIG_FSL_MC9SDZ60 CONFIG_FSL_MC_ENET
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Move these options to Kconfig and create a sub-menu to avoid name conflict with other architectures.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/Kconfig | 4 ++++ arch/arm/cpu/armv7/ls102xa/Kconfig | 8 ++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 15 +++++++++++++++ include/configs/ls1012a_common.h | 1 - include/configs/ls1043a_common.h | 1 - include/configs/ls1046a_common.h | 1 - include/configs/ls2080a_common.h | 1 - scripts/config_whitelist.txt | 2 -- 8 files changed, 27 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 +++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ---- arch/arm/include/asm/arch-ls102xa/config.h | 1 - 4 files changed, 24 insertions(+), 5 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 2648416..e8264f5 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -9,6 +9,17 @@ config LS1_DEEP_SLEEP bool "Deep sleep" depends on ARCH_LS1021A
+config MAX_CPUS + int "Maximum number of CPUs permitted for LS102xA" + depends on ARCH_LS1021A + default 2 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 5619e0d..6d87fd8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -32,4 +32,17 @@ config SYS_FSL_MMDC config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config MAX_CPUS + int "Maximum number of CPUs permitted for Layerscape" + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 16 if ARCH_LS2080A + default 1 + help + Set this number to the maximum number of possible CPUs in the SoC. + SoCs may have multiple clusters with each cluster may have multiple + ports. If some ports are reserved but higher ports are used for + cores, count the reserved ports. This will allocate enough memory + in spin table to properly handle all cores. + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index a5c6c4c..572fa94 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A -#define CONFIG_MAX_CPUS 16 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ @@ -171,7 +170,6 @@
/* SoC related */ #ifdef CONFIG_LS1043A -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 @@ -206,13 +204,11 @@ #define CONFIG_SYS_FSL_ERRATUM_A009660 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_ARCH_LS1012A) -#define CONFIG_MAX_CPUS 1 #undef CONFIG_SYS_FSL_DDRC_ARM_GEN3
#define GICD_BASE 0x01401000 #define GICC_BASE 0x01402000 #elif defined(CONFIG_ARCH_LS1046A) -#define CONFIG_MAX_CPUS 4 #define CONFIG_SYS_FMAN_V3 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index fab8774..70cc703 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -123,7 +123,6 @@ #define CONFIG_SYS_FSL_SRDS_1
#ifdef CONFIG_LS102XA -#define CONFIG_MAX_CPUS 2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Move MAX_CPUS option to Kconfig and clean up existing uses for ARM. This option is used by Freescale Layerscape SoCs.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 13 +++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 4 ---- arch/arm/include/asm/arch-ls102xa/config.h | 1 - 4 files changed, 24 insertions(+), 5 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Good start - I suppose we should unify these one day.
Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index e8264f5..88983f4 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -23,4 +23,9 @@ config MAX_CPUS config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1021A + default 8 + endmenu diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 6d87fd8..aa412ec 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,4 +45,11 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores.
+config SYS_FSL_IFC_BANK_COUNT + int "Maximum banks of Integrated flash controller" + depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A + default 4 if ARCH_LS1043A + default 4 if ARCH_LS1046A + default 8 if ARCH_LS2080A + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 572fa94..2f10ab7 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 3 #define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } @@ -174,7 +173,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 7 #define CONFIG_SYS_NUM_FM1_10GEC 1 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE @@ -213,7 +211,6 @@ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Move this option to Kconfig and clean up existing uses. This option is also used by PowerPC SoCs.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 5 +++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 7 +++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 3 files changed, 12 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index aa412ec..f683a14 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -45,6 +45,11 @@ config MAX_CPUS cores, count the reserved ports. This will allocate enough memory in spin table to properly handle all cores.
+config NUM_DDR_CONTROLLERS + int "Maximum DDR controllers" + default 3 if ARCH_LS2080A + default 1 + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A @@ -52,4 +57,7 @@ config SYS_FSL_IFC_BANK_COUNT default 4 if ARCH_LS1046A default 8 if ARCH_LS2080A
+config SYS_FSL_HAS_DP_DDR + bool + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 2f10ab7..6ee75cb 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -30,8 +30,6 @@ #define CONFIG_SYS_MEM_RESERVE_SECURE (2048 * 1024) /* 2MB */
#ifdef CONFIG_LS2080A -#define CONFIG_NUM_DDR_CONTROLLERS 3 -#define CONFIG_SYS_FSL_HAS_DP_DDR /* Runtime check to confirm */ #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_FSL_SRDS_1 @@ -150,7 +148,6 @@
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1 #elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_SYS_FSL_SEC_COMPAT 5 #define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define CONFIG_SYS_FSL_OCRAM_SIZE 0x00200000 /* 2M */
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Move this option to Kconfig and clean up existing uses. NUM_DDR_CONTROLLERS is also used by PowerPC SoCs.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8 ++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 3 --- 2 files changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Move these options to Kconfig and clean up existing uses.
Signed-off-by: York Sun york.sun@nxp.com --- arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 16 ++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 ----- arch/arm/include/asm/arch-ls102xa/config.h | 2 -- include/configs/ls1012a_common.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 3 --- include/configs/ls1043aqds.h | 2 -- include/configs/ls1046a_common.h | 3 --- include/configs/ls1046aqds.h | 2 -- include/configs/ls2080a_common.h | 3 --- 12 files changed, 27 insertions(+), 26 deletions(-)
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig index 88983f4..17f1975 100644 --- a/arch/arm/cpu/armv7/ls102xa/Kconfig +++ b/arch/arm/cpu/armv7/ls102xa/Kconfig @@ -1,6 +1,8 @@ config ARCH_LS1021A bool select SYS_FSL_ERRATUM_A010315 + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES
menu "LS102xA architecture" depends on ARCH_LS1021A @@ -23,6 +25,15 @@ config MAX_CPUS config SYS_FSL_ERRATUM_A010315 bool "Workaround for PCIe erratum A010315"
+config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + config SYS_FSL_IFC_BANK_COUNT int "Maximum banks of Integrated flash controller" depends on ARCH_LS1021A diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index f683a14..66e509e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -12,16 +12,23 @@ config ARCH_LS1043A config ARCH_LS1046A bool select FSL_LSCH2 + select SYS_FSL_SRDS_2
config ARCH_LS2080A bool select FSL_LSCH3 + select SYS_FSL_HAS_DP_DDR + select SYS_FSL_SRDS_2
config FSL_LSCH2 bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES
config FSL_LSCH3 bool + select SYS_FSL_SRDS_1 + select SYS_HAS_SERDES
menu "Layerscape architecture" depends on FSL_LSCH2 || FSL_LSCH3 @@ -60,4 +67,13 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_DP_DDR bool
+config SYS_FSL_SRDS_1 + bool + +config SYS_FSL_SRDS_2 + bool + +config SYS_HAS_SERDES + bool + endmenu diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 6ee75cb..3039e72 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -32,8 +32,6 @@ #ifdef CONFIG_LS2080A #define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 -#define CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES #define L1_CACHE_SHIFT 6 @@ -162,8 +160,6 @@ #define CONFIG_SYS_FSL_PEX_LUT_BE #define CONFIG_SYS_FSL_SEC_BE
-#define CONFIG_SYS_FSL_SRDS_1 - /* SoC related */ #ifdef CONFIG_LS1043A #define CONFIG_SYS_FMAN_V3 @@ -212,7 +208,6 @@ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
-#define CONFIG_SYS_FSL_SRDS_2 #define CONFIG_SYS_FSL_IFC_BE #define CONFIG_SYS_FSL_SFP_VER_3_2 #define CONFIG_SYS_FSL_SNVS_LE diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 70cc703..dfcb546 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -120,8 +120,6 @@
#define DCU_LAYER_MAX_NUM 16
-#define CONFIG_SYS_FSL_SRDS_1 - #ifdef CONFIG_LS102XA #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_NUM_DDR_CONTROLLERS 1 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 1056755..ced8ead 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -10,8 +10,6 @@ #define CONFIG_FSL_LAYERSCAPE #define CONFIG_GICV2
-#define CONFIG_SYS_HAS_SERDES - #include <asm/arch/config.h> #define CONFIG_SYS_NO_FLASH
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 0d72e69..5ff3db6 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -143,8 +143,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif
-#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index e5ac50e..67b43c6 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -170,8 +170,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_SYS_HAS_SERDES - #define CONFIG_FSL_CAAM /* Enable CAAM */
#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index ac86c08..3a85b6a 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -15,9 +15,6 @@ #define CONFIG_GICV2
#include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif
/* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index a80e33d..b18fcc0 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -52,8 +52,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif
-#define CONFIG_SYS_HAS_SERDES - #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index ec6c908..c4bbd56 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -14,9 +14,6 @@ #define CONFIG_GICV2
#include <asm/arch/config.h> -#ifdef CONFIG_SYS_FSL_SRDS_1 -#define CONFIG_SYS_HAS_SERDES -#endif
/* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 2e5c2f1..d1adf3f 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -49,8 +49,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_MEM_INIT_VALUE 0xdeadbeef #endif
-#define CONFIG_SYS_HAS_SERDES - /* DSPI */ #ifdef CONFIG_FSL_DSPI #define CONFIG_SPI_FLASH_STMICRO /* cs0 */ diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index d9eea09..187aee1 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -15,9 +15,6 @@
#include <asm/arch/ls2080a_stream_id.h> #include <asm/arch/config.h> -#if (defined(CONFIG_SYS_FSL_SRDS_1) || defined(CONFIG_SYS_FSL_SRDS_2)) -#define CONFIG_SYS_HAS_SERDES -#endif
/* Link Definitions */ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
On 30 September 2016 at 15:19, York Sun york.sun@nxp.com wrote:
Move these options to Kconfig and clean up existing uses.
Signed-off-by: York Sun york.sun@nxp.com
arch/arm/cpu/armv7/ls102xa/Kconfig | 11 +++++++++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 16 ++++++++++++++++ arch/arm/include/asm/arch-fsl-layerscape/config.h | 5 ----- arch/arm/include/asm/arch-ls102xa/config.h | 2 -- include/configs/ls1012a_common.h | 2 -- include/configs/ls1021aqds.h | 2 -- include/configs/ls1021atwr.h | 2 -- include/configs/ls1043a_common.h | 3 --- include/configs/ls1043aqds.h | 2 -- include/configs/ls1046a_common.h | 3 --- include/configs/ls1046aqds.h | 2 -- include/configs/ls2080a_common.h | 3 --- 12 files changed, 27 insertions(+), 26 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
participants (2)
-
Simon Glass -
York Sun