[U-Boot-Users] RE: changing core frequency in omap 5912
Hi Sriram, HK,
-----Original Message----- From: linux-omap-open-source-bounces@linux.omap.com
[mailto:linux-omap-
open-source-bounces@linux.omap.com] On Behalf Of Hiroki Kaminaga Sent: Monday, February 13, 2006 2:19 AM To: vshrirama@gmail.com Cc: u-boot-users@lists.sourceforge.net; linux-omap-open- source@linux.omap.com Subject: Re: changing core frequency in omap 5912
Hi,
How do i change the cpu core frequency in omap 5912. I tried changing the DPLL registers. but u-boot hangs.writing clock control value(0x050f) to address(0xfffece00)?
You need to take care when modifying the DPLL1 and the ARM_CKCTL register. Simply configuring the DPLL1 for 192MHz will not work, as by default uboot configures the device for what is know as "fully scalable mode", where the ARM, DSP and Traffic Controller (TC) run at the DPLL1 speed. The TC can NOT operate at 192MHz. It is limited to 96MHz. Therefore, before configuring the DPLL1 and ARM_CKCTL, you need to put the device into "synchronous scalable" mode where the ARM, DSP and TC can run at different speeds determined by the ARM_CKCTL register.
So here is what you need to do:
1). Make sure the DPLL1 is in bypass 2). Configure the ARM_SYSST for "synchronous scalable" mode 3). Configure the ARM_CKCTL register so that the different clock domains operate no faster than the maximum speed for that particular domain. See "OMAP5912 Global Clock Rules" in the OMAP5912 Errata guide for a list showing the maximum speed for each clock domain (http://focus.ti.com/docs/prod/folders/print/omap5912.html) 4). Configure DPLL1.
Regards, Jon
Hi,
So here is what you need to do:
1). Make sure the DPLL1 is in bypass 2). Configure the ARM_SYSST for "synchronous scalable" mode 3). Configure the ARM_CKCTL register so that the different clock domains operate no faster than the maximum speed for that particular domain. See "OMAP5912 Global Clock Rules" in the OMAP5912 Errata guide for a list showing the maximum speed for each clock domain (http://focus.ti.com/docs/prod/folders/print/omap5912.html) 4). Configure DPLL1.
Thank you!
I tried below code, (in temporary cmd in u-boot):
/* register address */ #define CLKGEN_REG_BASE (0xfffece00) #define REG_ARM_CKCTL (CLKGEN_REG_BASE + 0x0) #define REG_ARM_IDLECT1 (CLKGEN_REG_BASE + 0x4) #define REG_ARM_IDLECT2 (CLKGEN_REG_BASE + 0x8) #define REG_ARM_EWUPCT (CLKGEN_REG_BASE + 0xC) #define REG_ARM_RSTCT1 (CLKGEN_REG_BASE + 0x10) #define REG_ARM_RSTCT2 (CLKGEN_REG_BASE + 0x14) #define REG_ARM_SYSST (CLKGEN_REG_BASE + 0x18) #define REG_ARM_IDLECT3 (CLKGEN_REG_BASE + 0x24) #define REG_ARM_DPLL1 (0xfffecf00) /* register set value */ #define VAL_ARM_SYSST (0x1000) #define VAL_ARM_DPLL1 (0x2810) #define VAL_ARM_CKCTL (0x050f) #define VAL_ARM_IDLECT1 (0x0400) #define VAL_ARM_IDLECT2 (0x0000) /* ARM_IDLECT2 bit shifts */ #define EN_WDTCK 0 #define EN_XORPCK 1 #define EN_PERCK 2 #define EN_LCDCK 3 #define EN_LBCK 4 /* Not on 1610/1710 */ /*#define EN_HSABCK 5*/ #define EN_APICK 6 #define EN_TIMCK 7
...
*(short *)REG_ARM_SYSST = VAL_ARM_SYSST; { /* busy loop wait finish bubbles */ int i = 0x400; while (i--) ; } *(short *)REG_ARM_DPLL1 = VAL_ARM_DPLL1; { /* busy loop wait to let it settle */ int i = 10; while (i--) ; } *(short *)REG_ARM_CKCTL = VAL_ARM_CKCTL; *(short *)REG_ARM_CKCTL &= 0xfff; *(short *)REG_ARM_RSTCT1 = 0x0; *(short *)REG_ARM_RSTCT2 = 0x1; /* PER_EN bit */ *(short *)REG_ARM_IDLECT1 = VAL_ARM_IDLECT1;
*(short *)REG_ARM_IDLECT2 |= EN_PERCK; *(short *)REG_ARM_IDLECT2 |= EN_XORPCK; *(short *)REG_ARM_IDLECT2 |= EN_TIMCK;
{ /* busy loop wait finish bubbles */ int i = 0x400; while (i--) ; }
and seems working:
(ARM CKCTL register content) OMAP5912 OSK # md.l fffece00 fffece00: 0000050f 00000400 000003ff 0000003f ............?... fffece10: 00000000 00000001 00001000 00000015 ................ fffece20: 00000000 00000015 0000ffff 0000ffff ................ ... (ARM DPLL1 register content) OMAP5912 OSK # md.l fffecf00 fffecf00: 00002813 2b58c02f 00010000 00000000 .(../.X+........
I'm not sure about the amount and place of delay I need though... (I set delay referencing board/omap5912osk/lowlevel_init.S)
# Also, is there any simpler method to read ARM926EJS cpu speed?
Best Regards,
HK. --
participants (2)
-
Hiroki Kaminaga -
Hunter, Jon