From: Rainer Boschung rainer.boschung@keymile.com

- make use of the QRIO1 32bit register at 0x20 as bootcounter register - check for BOOTCOUNT_MAGIC pattern when before bootcounter value is read

Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Acked-by: Valentin Longchamp valentin.longchamp@keymile.com ---

board/keymile/kmp204x/kmp204x.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index f02642a..b41929a 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -134,22 +134,25 @@ void qrio_prstcfg(u8 bit, u8 mode) }

-#define BOOTCOUNT_OFF 0x12 +#define BOOTCOUNT_OFF 0x20

void bootcount_store(ulong counter) { - u8 val; void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE;

- val = (counter <= 255) ? (u8)counter : 255; - out_8(qrio_base + BOOTCOUNT_OFF, val); + out_be32(qrio_base + BOOTCOUNT_OFF, counter); }

ulong bootcount_load(void) { - u8 val; + u32 val; void __iomem *qrio_base = (void *)CONFIG_SYS_QRIO_BASE; - val = in_8(qrio_base + BOOTCOUNT_OFF); + val = in_be32(qrio_base + BOOTCOUNT_OFF + 4); + + if (val == BOOTCOUNT_MAGIC) + val = in_be32(qrio_base + BOOTCOUNT_OFF); + else + val = 0; return val; }

From: Rainer Boschung rainer.boschung@keymile.com

-uses common deblocking algorithm from ../common/common.c -supports deblocking of of I2C-bus1 by means of QRIO GPIO - SCL1 = GPIO_A16 - SDA1 = GPIO_A17

QRIO GPIOs act in an open-drain-like manner, for 0 GPIO drives low and for 1 the GPIO is an input and must be pulled up externaly!

Signed-off-by: Rainer Boschung rainer.boschung@keymile.com Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com Acked-by: Valentin Longchamp valentin.longchamp@keymile.com ---

board/keymile/kmp204x/kmp204x.c | 53 ++++++++++++++++++++++++++++++++++--- include/configs/km/kmp204x-common.h | 10 +++++++ 2 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index dae5378..141d7ee 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -33,12 +33,51 @@ int checkboard(void) return 0; }

-/* TODO: implement the I2C deblocking function */ -int i2c_make_abort(void) +/* I2C deblocking uses the algorithm defined in ../common/common.c, which + * makes use of 2 QRIO GPIOs to act on the SCL and SDA signals of an I2C bus. + * According to the standard I2C IOs must not drive HI-Levels, so the + * QRIO GPIOs are used in open-drain fashion: + * -> 0 GPIO configured as output that drives low + * -> 1 GPIO configured as input pull-up ties high + */ + +/* GPIOs used for deblocking I2C bus 1 */ +#define DBLK_PORT1 GPIO_A +#define DBLK_SCL1 16 +#define DBLK_SDA1 17 + +/* By default deblock GPIOs are floating */ +static void i2c_deblock_gpio_cfg(void) +{ + /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */ + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SCL1); + qrio_gpio_direction_input(DBLK_PORT1, DBLK_SDA1); + + qrio_set_gpio(DBLK_PORT1, DBLK_SCL1, 0); + qrio_set_gpio(DBLK_PORT1, DBLK_SDA1, 0); +} + +void set_sda(int state) +{ + qrio_set_opendrain_gpio(DBLK_PORT1, DBLK_SDA1, state); +} + +void set_scl(int state) +{ + qrio_set_opendrain_gpio(DBLK_PORT1, DBLK_SCL1, state); +} + +int get_sda(void) +{ + return qrio_get_gpio(DBLK_PORT1, DBLK_SDA1); +} + +int get_scl(void) { - return 1; + return qrio_get_gpio(DBLK_PORT1, DBLK_SCL1); }

+ #define ZL30158_RST 8 #define ZL30343_RST 9

@@ -77,6 +116,14 @@ unsigned long get_board_sys_clk(unsigned long dummy) return 66666666; }

+int misc_init_f(void) +{ + /* configure QRIO pis for i2c deblocking */ + i2c_deblock_gpio_cfg(); + + return 0; +} + #define BOOTCOUNT_OFF 0x20

void bootcount_store(ulong counter) diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index 50330cc..b4242e5 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -209,6 +209,7 @@ unsigned long get_board_sys_clk(unsigned long dummy);

#define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ +#define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R #define CONFIG_LAST_STAGE_INIT

@@ -264,7 +265,10 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */

/* I2C */ + #define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_INIT_BOARD +#define CONFIG_SYS_I2C_SPEED 100000 /* deblocking */ #define CONFIG_SYS_NUM_I2C_BUSES 3 #define CONFIG_SYS_I2C_MAX_HOPS 1 #define CONFIG_SYS_I2C_FSL /* Use FSL I2C driver */ @@ -277,6 +281,12 @@ unsigned long get_board_sys_clk(unsigned long dummy); {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \ {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \ } +#ifndef __ASSEMBLY__ +void set_sda(int state); +void set_scl(int state); +int get_sda(void); +int get_scl(void); +#endif

#define CONFIG_KM_IVM_BUS 1 /* I2C1 (Mux-Port 1)*/

The kmcoge4 board is the product board derived from the kmlion1 prototype. The main difference between the 2 boards is that the kmcoge4 does not configure the Local Bus controller for LCS2.

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com ---

boards.cfg | 1 + include/configs/kmp204x.h | 7 ++++++- 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/boards.cfg b/boards.cfg index d177f82..4198ccf 100644 --- a/boards.cfg +++ b/boards.cfg @@ -991,6 +991,7 @@ Active powerpc mpc85xx - gdsys p1022 Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER controlcenterd:TRAILBLAZER,SPIFLASH Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach eibach@gdsys.de Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp valentin.longchamp@keymile.com +Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp valentin.longchamp@keymile.com Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek dan@embeddedalley.com Active powerpc mpc85xx - stx stxssa stxssa stxssa Dan Malek dan@embeddedalley.com Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek dan@embeddedalley.com diff --git a/include/configs/kmp204x.h b/include/configs/kmp204x.h index 4158c8d..8bb3571 100644 --- a/include/configs/kmp204x.h +++ b/include/configs/kmp204x.h @@ -13,6 +13,11 @@ #define CONFIG_HOSTNAME kmlion1 #define CONFIG_KM_BOARD_NAME "kmlion1"

+/* KMCOGE4 */ +#elif defined(CONFIG_KMCOGE4) +#define CONFIG_HOSTNAME kmcoge4 +#define CONFIG_KM_BOARD_NAME "kmcoge4" + #else #error ("Board not supported") #endif @@ -42,6 +47,7 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM /* Local bus app1 Options */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM +#endif

/* App2 Local bus */ #define CONFIG_SYS_LBAPP2_BASE 0xE0000000 @@ -63,6 +69,5 @@ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM /* Local bus app2 Options */ #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM -#endif

#endif /* __CONFIG_H */

This define can be used if the ubi boot partition (defined for all Keymile boards with KM_UBI_PARTITION_NAME_BOOT #define to ubi0) needs some additionnal boot options.

This is the case for the kmp204x boards since u-boot does not support NAND Flash subpage accesses on this platform, an additionnal argument that defines the VID offstet must be given to the kernel.

The UBI cmd line option now looks like this "ubi.mtd=ubi0,2048" on this platform.

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com ---

include/configs/km/keymile-common.h | 10 ++++++++-- include/configs/km/kmp204x-common.h | 4 ++++ 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 2a15ad4..a4e0f7c 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -99,11 +99,16 @@ #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" #endif /* CONFIG_KM_UBI_PARTITION_NAME_BOOT */

+#ifndef CONFIG_KM_UBI_PART_BOOT_OPTS +#define CONFIG_KM_UBI_PART_BOOT_OPTS "" +#endif /* CONFIG_KM_UBI_PART_BOOT_OPTS */ + #ifndef CONFIG_KM_UBI_PARTITION_NAME_APP /* one flash chip only called boot */ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=ubi part " CONFIG_KM_UBI_PARTITION_NAME_BOOT "\0" #else /* CONFIG_KM_UBI_PARTITION_NAME_APP */ @@ -111,7 +116,8 @@ /* boot: CONFIG_KM_UBI_PARTITION_NAME_BOOT */ /* app: CONFIG_KM_UBI_PARTITION_NAME_APP */ # define CONFIG_KM_UBI_LINUX_MTD \ - "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT " " \ + "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_BOOT \ + CONFIG_KM_UBI_PART_BOOT_OPTS " " \ "ubi.mtd=" CONFIG_KM_UBI_PARTITION_NAME_APP # define CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI \ "ubiattach=if test ${boot_bank} -eq 0; then; " \ diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index b4242e5..935aa7e 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -15,6 +15,10 @@

#define CONFIG_KM_DEF_NETDEV "netdev=eth0\0"

+/* an additionnal option is required for UBI as subpage access is + * supported in u-boot */ +#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048" + #define CONFIG_NAND_ECC_BCH

/* common KM defines */

The PEXHC PCIe configuration mechanism ensures that the FPGA get configured at power-up. Since all the PCIe devices should be configured when the kernel start, u-boot has to take care that the FPGA gets configured also in other reset scenarios, mostly because of possible configuration change.

The used mechanism is taken from the km_kirkwood design and adapted to the kmp204x case (slightly different HW and PCIe configuration).

Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com ---

board/keymile/kmp204x/kmp204x.c | 7 +++- board/keymile/kmp204x/pci.c | 85 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 91 insertions(+), 1 deletion(-)

diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index 141d7ee..4814efb 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -101,6 +101,7 @@ int board_early_init_f(void)

int board_early_init_r(void) { + int ret = 0; /* Flush d-cache and invalidate i-cache of any FLASH data */ flush_dcache(); invalidate_icache(); @@ -108,7 +109,11 @@ int board_early_init_r(void) set_liodns(); setup_portals();

- return 0; + ret = trigger_fpga_config(); + if (ret) + printf("error triggering PCIe FPGA config\n"); + + return ret; }

unsigned long get_board_sys_clk(unsigned long dummy) diff --git a/board/keymile/kmp204x/pci.c b/board/keymile/kmp204x/pci.c index ec20c8a..a484eb5 100644 --- a/board/keymile/kmp204x/pci.c +++ b/board/keymile/kmp204x/pci.c @@ -14,18 +14,103 @@ #include <libfdt.h> #include <fdt_support.h> #include <asm/fsl_serdes.h> +#include <asm/errno.h>

#include "kmp204x.h"

+#define PROM_SEL_L 11 +/* control the PROM_SEL_L signal*/ +static void toggle_fpga_eeprom_bus(bool cpu_own) +{ + qrio_gpio_direction_output(GPIO_A, PROM_SEL_L, !cpu_own); +} + +#define CONF_SEL_L 10 +#define FPGA_PROG_L 19 +#define FPGA_DONE 18 +#define FPGA_INIT_L 17 + +int trigger_fpga_config(void) +{ + int ret = 0, init_l; + /* approx 10ms */ + u32 timeout = 10000; + + /* make sure the FPGA_can access the EEPROM */ + toggle_fpga_eeprom_bus(false); + + /* assert CONF_SEL_L to be able to drive FPGA_PROG_L */ + qrio_gpio_direction_output(GPIO_A, CONF_SEL_L, 0); + + /* trigger the config start */ + qrio_gpio_direction_output(GPIO_A, FPGA_PROG_L, 0); + + /* small delay for INIT_L line */ + udelay(10); + + /* wait for FPGA_INIT to be asserted */ + do { + init_l = qrio_get_gpio(GPIO_A, FPGA_INIT_L); + if (timeout-- == 0) { + printf("FPGA_INIT timeout\n"); + ret = -EFAULT; + break; + } + udelay(10); + } while (init_l); + + /* deassert FPGA_PROG, config should start */ + qrio_set_gpio(GPIO_A, FPGA_PROG_L, 1); + + return ret; +} + +/* poll the FPGA_DONE signal and give the EEPROM back to the QorIQ */ +static int wait_for_fpga_config(void) +{ + int ret = 0, done; + /* approx 5 s */ + u32 timeout = 500000; + + printf("PCIe FPGA config:"); + do { + done = qrio_get_gpio(GPIO_A, FPGA_DONE); + if (timeout-- == 0) { + printf(" FPGA_DONE timeout\n"); + ret = -EFAULT; + goto err_out; + } + udelay(10); + } while (!done); + + printf(" done\n"); + +err_out: + /* deactive CONF_SEL and give the CPU conf EEPROM access */ + qrio_set_gpio(GPIO_A, CONF_SEL_L, 1); + toggle_fpga_eeprom_bus(true); + + return ret; +} + #define PCIE_SW_RST 14 +#define PEXHC_SW_RST 13 #define HOOPER_SW_RST 12

void pci_init_board(void) { + /* first wait for the PCIe FPGA to be configured + * it has been triggered earlier in board_early_init_r */ + int ret = wait_for_fpga_config(); + if (ret) + printf("error finishing PCIe FPGA config\n"); + qrio_prst(PCIE_SW_RST, false, false); + qrio_prst(PEXHC_SW_RST, false, false); qrio_prst(HOOPER_SW_RST, false, false); /* Hooper is not direcly PCIe capable */ mdelay(50); + fsl_pcie_init_board(0); }