[PATCH v3 03/19] imx: kontron-sl-mx8mm: Remove custom board_boot_order() workaround
From: Frieder Schrempf frieder.schrempf@kontron.de
Nowadays detecting the SPI NOR as boot device from the ROMAPI is fixed and works even if the SPI NOR is used as fallback boot device.
Therefore we don't need this workaround anymore.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * new patch --- board/kontron/sl-mx8mm/spl.c | 22 ---------------------- 1 file changed, 22 deletions(-)
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index c379d37f1e8..2a562f4ac97 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -238,25 +238,3 @@ void board_init_f(ulong dummy)
board_init_r(NULL, 0); } - -void board_boot_order(u32 *spl_boot_list) -{ - u32 bootdev = spl_boot_device(); - - /* - * The default boot fuse settings use the SD card (MMC2) as primary - * boot device, but allow SPI NOR as a fallback boot device. - * We can't detect the fallback case and spl_boot_device() will return - * BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR. - * Therefore we try to load U-Boot proper vom SPI NOR after loading - * from MMC has failed. - */ - spl_boot_list[0] = bootdev; - - switch (bootdev) { - case BOOT_DEVICE_MMC1: - case BOOT_DEVICE_MMC2: - spl_boot_list[1] = BOOT_DEVICE_SPI; - break; - } -}
From: Frieder Schrempf frieder.schrempf@kontron.de
This allows using the command line with longer lines like large scripts in env variables.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * new patch --- configs/kontron-sl-mx8mm_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 3e71e786072..90618022510 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -49,7 +49,7 @@ CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000 CONFIG_SPL_WATCHDOG=y CONFIG_SPL_ATF=y -CONFIG_SYS_CBSIZE=256 +CONFIG_SYS_CBSIZE=2048 CONFIG_SYS_PBSIZE=276 CONFIG_CMD_NVEDIT_EFI=y # CONFIG_CMD_LZMADEC is not set
From: Frieder Schrempf frieder.schrempf@kontron.de This allows using the command line with longer lines like large scripts in env variables. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Enable the MTD command to be used for the SPI NOR on the SoM.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * new patch --- configs/kontron-sl-mx8mm_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 90618022510..b67ab8668db 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -59,6 +59,7 @@ CONFIG_CMD_FUSE=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y CONFIG_CMD_CACHE=y
From: Frieder Schrempf frieder.schrempf@kontron.de Enable the MTD command to be used for the SPI NOR on the SoM. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Enable the redundant environment feature to allow falling back in case of storage corruption. The partition layout for the SPI NOR device is added to the devicetree.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * fix hex numbers and unit addresses in partitions
Changes in v2: * describe SPI NOR partitions in devicetree * move environment to end of SPI NOR --- arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 21 +++++++++++++++++++++ configs/kontron-sl-mx8mm_defconfig | 4 +++- 2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi index 8f90eb02550..3b66e560927 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -70,6 +70,27 @@ compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; spi-max-frequency = <80000000>; reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x1e0000>; + }; + + partition@1e0000 { + label = "env"; + reg = <0x1e0000 0x10000>; + }; + + partition@1f0000 { + label = "env_redundant"; + reg = <0x1f0000 0x10000>; + }; + }; }; };
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index b67ab8668db..5c1dc754967 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_ENV_SIZE=0x10000 -CONFIG_ENV_OFFSET=0x1f0000 +CONFIG_ENV_OFFSET=0x1E0000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg" CONFIG_DM_GPIO=y @@ -19,6 +19,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_BOOTCOUNT_BOOTLIMIT=3 CONFIG_SPL=y +CONFIG_ENV_OFFSET_REDUND=0x1F0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_SYS_LOAD_ADDR=0x42000000 @@ -72,6 +73,7 @@ CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM=y
From: Frieder Schrempf frieder.schrempf@kontron.de Enable the redundant environment feature to allow falling back in case of storage corruption. The partition layout for the SPI NOR device is added to the devicetree. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
In case we boot from SD card or eMMC, we also want to load the environment from the according boot device.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- board/kontron/sl-mx8mm/sl-mx8mm.c | 31 ++++++++++++++++++++++++++++++ configs/kontron-sl-mx8mm_defconfig | 1 + 2 files changed, 32 insertions(+)
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index fea93278374..416c4cbb407 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -4,10 +4,13 @@ */
#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> +#include <asm/mach-imx/boot_mode.h> #include <efi.h> #include <efi_loader.h> +#include <env_internal.h> #include <fdt_support.h> #include <linux/errno.h> #include <linux/kernel.h> @@ -117,3 +120,31 @@ int board_init(void) { return 0; } + +enum env_location env_get_location(enum env_operation op, int prio) +{ + enum boot_device boot_dev = get_boot_device(); + + if (prio) + return ENVL_UNKNOWN; + + /* + * Make sure that the environment is loaded from + * the MMC if we are running from SD card or eMMC. + */ + if (CONFIG_IS_ENABLED(ENV_IS_IN_MMC) && + (boot_dev == SD1_BOOT || boot_dev == SD2_BOOT)) + return ENVL_MMC; + + if (CONFIG_IS_ENABLED(ENV_IS_IN_SPI_FLASH)) + return ENVL_SPI_FLASH; + + return ENVL_NOWHERE; +} + +#if defined(CONFIG_ENV_IS_IN_MMC) +int board_mmc_get_env_dev(int devno) +{ + return devno; +} +#endif diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 5c1dc754967..842a1a01e1a 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -72,6 +72,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
From: Frieder Schrempf frieder.schrempf@kontron.de In case we boot from SD card or eMMC, we also want to load the environment from the according boot device. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Move the environment from the board header to a separate text file and also drop those variables that are already set in env_default.h from the Kconfig options.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- board/kontron/sl-mx8mm/sl-mx8mm.env | 7 +++++++ include/configs/kontron-sl-mx8mm.h | 16 +--------------- 2 files changed, 8 insertions(+), 15 deletions(-) create mode 100644 board/kontron/sl-mx8mm/sl-mx8mm.env
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.env b/board/kontron/sl-mx8mm/sl-mx8mm.env new file mode 100644 index 00000000000..ef6fc1f3428 --- /dev/null +++ b/board/kontron/sl-mx8mm/sl-mx8mm.env @@ -0,0 +1,7 @@ +kernel_addr_r=0x42000000 +fdt_addr_r=0x48000000 +fdtoverlay_addr_r=0x49000000 +ramdisk_addr_r=0x48080000 +scriptaddr=0x40000000 +pxefile_addr_r=0x40100000 +dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000 diff --git a/include/configs/kontron-sl-mx8mm.h b/include/configs/kontron-sl-mx8mm.h index 622ab597624..a2aedefcec2 100644 --- a/include/configs/kontron-sl-mx8mm.h +++ b/include/configs/kontron-sl-mx8mm.h @@ -50,20 +50,6 @@ #define CONFIG_MALLOC_F_ADDR 0x930000 #endif
-#define ENV_MEM_LAYOUT_SETTINGS \ - "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ - "kernel_addr_r=0x42000000\0" \ - "fdt_addr_r=0x48000000\0" \ - "fdtoverlay_addr_r=0x49000000\0" \ - "ramdisk_addr_r=0x48080000\0" \ - "scriptaddr=0x40000000\0"\ - "pxefile_addr_r=0x40100000\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "dfu_alt_info=sf 0:0=flash-bin raw 0x400 0x1f0000\0" \ - "bootdelay=3\0" \ - "hostname=" CONFIG_HOSTNAME "\0" \ - ENV_MEM_LAYOUT_SETTINGS \ - BOOTENV +#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV
#endif /* __KONTRON_MX8MM_CONFIG_H */
From: Frieder Schrempf frieder.schrempf@kontron.de Move the environment from the board header to a separate text file and also drop those variables that are already set in env_default.h from the Kconfig options. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Enable the bootaux command in order to be able to load a binary into the M4 core when needed.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- configs/kontron-sl-mx8mm_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 842a1a01e1a..5dcee988478 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1F0000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_FIT=y
From: Frieder Schrempf frieder.schrempf@kontron.de Enable the bootaux command in order to be able to load a binary into the M4 core when needed. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Fix the spaces and alignment for easier tracking of changes and comparing with configs generated by the tools.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- board/kontron/sl-mx8mm/lpddr4_timing.c | 2076 ++++++++++++------------ 1 file changed, 1038 insertions(+), 1038 deletions(-)
diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index 0eabb160185..a8dcaafb180 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -10,313 +10,313 @@
struct dram_cfg_param ddr_ddrc_cfg[] = { /** Initialize DDRC registers **/ - {0x3d400304, 0x1}, - {0x3d400030, 0x1}, - {0x3d400000, 0xa3080020}, - {0x3d400020, 0x223}, - {0x3d400024, 0x3a980}, - {0x3d400064, 0x5b0087}, - {0x3d4000d0, 0xc00305ba}, - {0x3d4000d4, 0x940000}, - {0x3d4000dc, 0xd4002d}, - {0x3d4000e0, 0x310000}, - {0x3d4000e8, 0x66004d}, - {0x3d4000ec, 0x16004d}, - {0x3d400100, 0x191e1920}, - {0x3d400104, 0x60630}, - {0x3d40010c, 0xb0b000}, - {0x3d400110, 0xe04080e}, - {0x3d400114, 0x2040c0c}, - {0x3d400118, 0x1010007}, - {0x3d40011c, 0x401}, - {0x3d400130, 0x20600}, - {0x3d400134, 0xc100002}, - {0x3d400138, 0xd8}, - {0x3d400144, 0x96004b}, - {0x3d400180, 0x2ee0017}, - {0x3d400184, 0x2605b8e}, - {0x3d400188, 0x0}, - {0x3d400190, 0x497820a}, - {0x3d400194, 0x80303}, - {0x3d4001b4, 0x170a}, - {0x3d4001a0, 0xe0400018}, - {0x3d4001a4, 0xdf00e4}, - {0x3d4001a8, 0x80000000}, - {0x3d4001b0, 0x11}, - {0x3d4001c0, 0x1}, - {0x3d4001c4, 0x1}, - {0x3d4000f4, 0xc99}, - {0x3d400108, 0x70e1617}, - {0x3d400200, 0x17}, - {0x3d40020c, 0x0}, - {0x3d400210, 0x1f1f}, - {0x3d400204, 0x80808}, - {0x3d400214, 0x7070707}, - {0x3d400218, 0x7070707}, - {0x3d400250, 0x29001701}, - {0x3d400254, 0x2c}, - {0x3d40025c, 0x4000030}, - {0x3d400264, 0x900093e7}, - {0x3d40026c, 0x2005574}, - {0x3d400400, 0x111}, - {0x3d400408, 0x72ff}, - {0x3d400494, 0x2100e07}, - {0x3d400498, 0x620096}, - {0x3d40049c, 0x1100e07}, - {0x3d4004a0, 0xc8012c}, - {0x3d402020, 0x21}, - {0x3d402024, 0x7d00}, - {0x3d402050, 0x20d040}, - {0x3d402064, 0xc001c}, - {0x3d4020dc, 0x840000}, - {0x3d4020e0, 0x310000}, - {0x3d4020e8, 0x66004d}, - {0x3d4020ec, 0x16004d}, - {0x3d402100, 0xa040305}, - {0x3d402104, 0x30407}, - {0x3d402108, 0x203060b}, - {0x3d40210c, 0x505000}, - {0x3d402110, 0x2040202}, - {0x3d402114, 0x2030202}, - {0x3d402118, 0x1010004}, - {0x3d40211c, 0x301}, - {0x3d402130, 0x20300}, - {0x3d402134, 0xa100002}, - {0x3d402138, 0x1d}, - {0x3d402144, 0x14000a}, - {0x3d402180, 0x640004}, - {0x3d402190, 0x3818200}, - {0x3d402194, 0x80303}, - {0x3d4021b4, 0x100}, - {0x3d403020, 0x21}, - {0x3d403024, 0x1f40}, - {0x3d403050, 0x20d040}, - {0x3d403064, 0x30007}, - {0x3d4030dc, 0x840000}, - {0x3d4030e0, 0x310000}, - {0x3d4030e8, 0x66004d}, - {0x3d4030ec, 0x16004d}, - {0x3d403100, 0xa010102}, - {0x3d403104, 0x30404}, - {0x3d403108, 0x203060b}, - {0x3d40310c, 0x505000}, - {0x3d403110, 0x2040202}, - {0x3d403114, 0x2030202}, - {0x3d403118, 0x1010004}, - {0x3d40311c, 0x301}, - {0x3d403130, 0x20300}, - {0x3d403134, 0xa100002}, - {0x3d403138, 0x8}, - {0x3d403144, 0x50003}, - {0x3d403180, 0x190004}, - {0x3d403190, 0x3818200}, - {0x3d403194, 0x80303}, - {0x3d4031b4, 0x100}, - {0x3d400028, 0x0}, + { 0x3d400304, 0x1 }, + { 0x3d400030, 0x1 }, + { 0x3d400000, 0xa3080020 }, + { 0x3d400020, 0x223 }, + { 0x3d400024, 0x3a980 }, + { 0x3d400064, 0x5b0087 }, + { 0x3d4000d0, 0xc00305ba }, + { 0x3d4000d4, 0x940000 }, + { 0x3d4000dc, 0xd4002d }, + { 0x3d4000e0, 0x310000 }, + { 0x3d4000e8, 0x66004d }, + { 0x3d4000ec, 0x16004d }, + { 0x3d400100, 0x191e1920 }, + { 0x3d400104, 0x60630 }, + { 0x3d40010c, 0xb0b000 }, + { 0x3d400110, 0xe04080e }, + { 0x3d400114, 0x2040c0c }, + { 0x3d400118, 0x1010007 }, + { 0x3d40011c, 0x401 }, + { 0x3d400130, 0x20600 }, + { 0x3d400134, 0xc100002 }, + { 0x3d400138, 0xd8 }, + { 0x3d400144, 0x96004b }, + { 0x3d400180, 0x2ee0017 }, + { 0x3d400184, 0x2605b8e }, + { 0x3d400188, 0x0 }, + { 0x3d400190, 0x497820a }, + { 0x3d400194, 0x80303 }, + { 0x3d4001b4, 0x170a }, + { 0x3d4001a0, 0xe0400018 }, + { 0x3d4001a4, 0xdf00e4 }, + { 0x3d4001a8, 0x80000000 }, + { 0x3d4001b0, 0x11 }, + { 0x3d4001c0, 0x1 }, + { 0x3d4001c4, 0x1 }, + { 0x3d4000f4, 0xc99 }, + { 0x3d400108, 0x70e1617 }, + { 0x3d400200, 0x17 }, + { 0x3d40020c, 0x0 }, + { 0x3d400210, 0x1f1f }, + { 0x3d400204, 0x80808 }, + { 0x3d400214, 0x7070707 }, + { 0x3d400218, 0x7070707 }, + { 0x3d400250, 0x29001701 }, + { 0x3d400254, 0x2c }, + { 0x3d40025c, 0x4000030 }, + { 0x3d400264, 0x900093e7 }, + { 0x3d40026c, 0x2005574 }, + { 0x3d400400, 0x111 }, + { 0x3d400408, 0x72ff }, + { 0x3d400494, 0x2100e07 }, + { 0x3d400498, 0x620096 }, + { 0x3d40049c, 0x1100e07 }, + { 0x3d4004a0, 0xc8012c }, + { 0x3d402020, 0x21 }, + { 0x3d402024, 0x7d00 }, + { 0x3d402050, 0x20d040 }, + { 0x3d402064, 0xc001c }, + { 0x3d4020dc, 0x840000 }, + { 0x3d4020e0, 0x310000 }, + { 0x3d4020e8, 0x66004d }, + { 0x3d4020ec, 0x16004d }, + { 0x3d402100, 0xa040305 }, + { 0x3d402104, 0x30407 }, + { 0x3d402108, 0x203060b }, + { 0x3d40210c, 0x505000 }, + { 0x3d402110, 0x2040202 }, + { 0x3d402114, 0x2030202 }, + { 0x3d402118, 0x1010004 }, + { 0x3d40211c, 0x301 }, + { 0x3d402130, 0x20300 }, + { 0x3d402134, 0xa100002 }, + { 0x3d402138, 0x1d }, + { 0x3d402144, 0x14000a }, + { 0x3d402180, 0x640004 }, + { 0x3d402190, 0x3818200 }, + { 0x3d402194, 0x80303 }, + { 0x3d4021b4, 0x100 }, + { 0x3d403020, 0x21 }, + { 0x3d403024, 0x1f40 }, + { 0x3d403050, 0x20d040 }, + { 0x3d403064, 0x30007 }, + { 0x3d4030dc, 0x840000 }, + { 0x3d4030e0, 0x310000 }, + { 0x3d4030e8, 0x66004d }, + { 0x3d4030ec, 0x16004d }, + { 0x3d403100, 0xa010102 }, + { 0x3d403104, 0x30404 }, + { 0x3d403108, 0x203060b }, + { 0x3d40310c, 0x505000 }, + { 0x3d403110, 0x2040202 }, + { 0x3d403114, 0x2030202 }, + { 0x3d403118, 0x1010004 }, + { 0x3d40311c, 0x301 }, + { 0x3d403130, 0x20300 }, + { 0x3d403134, 0xa100002 }, + { 0x3d403138, 0x8 }, + { 0x3d403144, 0x50003 }, + { 0x3d403180, 0x190004 }, + { 0x3d403190, 0x3818200 }, + { 0x3d403194, 0x80303 }, + { 0x3d4031b4, 0x100 }, + { 0x3d400028, 0x0 }, };
/* PHY Initialize Configuration */ struct dram_cfg_param ddr_ddrphy_cfg[] = { - {0x100a0, 0x0}, - {0x100a1, 0x1}, - {0x100a2, 0x2}, - {0x100a3, 0x3}, - {0x100a4, 0x4}, - {0x100a5, 0x5}, - {0x100a6, 0x6}, - {0x100a7, 0x7}, - {0x110a0, 0x0}, - {0x110a1, 0x1}, - {0x110a2, 0x3}, - {0x110a3, 0x4}, - {0x110a4, 0x5}, - {0x110a5, 0x2}, - {0x110a6, 0x7}, - {0x110a7, 0x6}, - {0x120a0, 0x0}, - {0x120a1, 0x1}, - {0x120a2, 0x3}, - {0x120a3, 0x2}, - {0x120a4, 0x5}, - {0x120a5, 0x4}, - {0x120a6, 0x7}, - {0x120a7, 0x6}, - {0x130a0, 0x0}, - {0x130a1, 0x1}, - {0x130a2, 0x2}, - {0x130a3, 0x3}, - {0x130a4, 0x4}, - {0x130a5, 0x5}, - {0x130a6, 0x6}, - {0x130a7, 0x7}, - {0x1005f, 0x1ff}, - {0x1015f, 0x1ff}, - {0x1105f, 0x1ff}, - {0x1115f, 0x1ff}, - {0x1205f, 0x1ff}, - {0x1215f, 0x1ff}, - {0x1305f, 0x1ff}, - {0x1315f, 0x1ff}, - {0x11005f, 0x1ff}, - {0x11015f, 0x1ff}, - {0x11105f, 0x1ff}, - {0x11115f, 0x1ff}, - {0x11205f, 0x1ff}, - {0x11215f, 0x1ff}, - {0x11305f, 0x1ff}, - {0x11315f, 0x1ff}, - {0x21005f, 0x1ff}, - {0x21015f, 0x1ff}, - {0x21105f, 0x1ff}, - {0x21115f, 0x1ff}, - {0x21205f, 0x1ff}, - {0x21215f, 0x1ff}, - {0x21305f, 0x1ff}, - {0x21315f, 0x1ff}, - {0x55, 0x1ff}, - {0x1055, 0x1ff}, - {0x2055, 0x1ff}, - {0x3055, 0x1ff}, - {0x4055, 0x1ff}, - {0x5055, 0x1ff}, - {0x6055, 0x1ff}, - {0x7055, 0x1ff}, - {0x8055, 0x1ff}, - {0x9055, 0x1ff}, - {0x200c5, 0x19}, - {0x1200c5, 0x7}, - {0x2200c5, 0x7}, - {0x2002e, 0x2}, - {0x12002e, 0x2}, - {0x22002e, 0x2}, - {0x90204, 0x0}, - {0x190204, 0x0}, - {0x290204, 0x0}, - {0x20024, 0x1ab}, - {0x2003a, 0x0}, - {0x120024, 0x1ab}, - {0x2003a, 0x0}, - {0x220024, 0x1ab}, - {0x2003a, 0x0}, - {0x20056, 0x3}, - {0x120056, 0x3}, - {0x220056, 0x3}, - {0x1004d, 0xe00}, - {0x1014d, 0xe00}, - {0x1104d, 0xe00}, - {0x1114d, 0xe00}, - {0x1204d, 0xe00}, - {0x1214d, 0xe00}, - {0x1304d, 0xe00}, - {0x1314d, 0xe00}, - {0x11004d, 0xe00}, - {0x11014d, 0xe00}, - {0x11104d, 0xe00}, - {0x11114d, 0xe00}, - {0x11204d, 0xe00}, - {0x11214d, 0xe00}, - {0x11304d, 0xe00}, - {0x11314d, 0xe00}, - {0x21004d, 0xe00}, - {0x21014d, 0xe00}, - {0x21104d, 0xe00}, - {0x21114d, 0xe00}, - {0x21204d, 0xe00}, - {0x21214d, 0xe00}, - {0x21304d, 0xe00}, - {0x21314d, 0xe00}, - {0x10049, 0xeba}, - {0x10149, 0xeba}, - {0x11049, 0xeba}, - {0x11149, 0xeba}, - {0x12049, 0xeba}, - {0x12149, 0xeba}, - {0x13049, 0xeba}, - {0x13149, 0xeba}, - {0x110049, 0xeba}, - {0x110149, 0xeba}, - {0x111049, 0xeba}, - {0x111149, 0xeba}, - {0x112049, 0xeba}, - {0x112149, 0xeba}, - {0x113049, 0xeba}, - {0x113149, 0xeba}, - {0x210049, 0xeba}, - {0x210149, 0xeba}, - {0x211049, 0xeba}, - {0x211149, 0xeba}, - {0x212049, 0xeba}, - {0x212149, 0xeba}, - {0x213049, 0xeba}, - {0x213149, 0xeba}, - {0x43, 0x63}, - {0x1043, 0x63}, - {0x2043, 0x63}, - {0x3043, 0x63}, - {0x4043, 0x63}, - {0x5043, 0x63}, - {0x6043, 0x63}, - {0x7043, 0x63}, - {0x8043, 0x63}, - {0x9043, 0x63}, - {0x20018, 0x3}, - {0x20075, 0x4}, - {0x20050, 0x0}, - {0x20008, 0x2ee}, - {0x120008, 0x64}, - {0x220008, 0x19}, - {0x20088, 0x9}, - {0x200b2, 0xdc}, - {0x10043, 0x5a1}, - {0x10143, 0x5a1}, - {0x11043, 0x5a1}, - {0x11143, 0x5a1}, - {0x12043, 0x5a1}, - {0x12143, 0x5a1}, - {0x13043, 0x5a1}, - {0x13143, 0x5a1}, - {0x1200b2, 0xdc}, - {0x110043, 0x5a1}, - {0x110143, 0x5a1}, - {0x111043, 0x5a1}, - {0x111143, 0x5a1}, - {0x112043, 0x5a1}, - {0x112143, 0x5a1}, - {0x113043, 0x5a1}, - {0x113143, 0x5a1}, - {0x2200b2, 0xdc}, - {0x210043, 0x5a1}, - {0x210143, 0x5a1}, - {0x211043, 0x5a1}, - {0x211143, 0x5a1}, - {0x212043, 0x5a1}, - {0x212143, 0x5a1}, - {0x213043, 0x5a1}, - {0x213143, 0x5a1}, - {0x200fa, 0x1}, - {0x1200fa, 0x1}, - {0x2200fa, 0x1}, - {0x20019, 0x1}, - {0x120019, 0x1}, - {0x220019, 0x1}, - {0x200f0, 0x660}, - {0x200f1, 0x0}, - {0x200f2, 0x4444}, - {0x200f3, 0x8888}, - {0x200f4, 0x5665}, - {0x200f5, 0x0}, - {0x200f6, 0x0}, - {0x200f7, 0xf000}, - {0x20025, 0x0}, - {0x2002d, 0x0}, - {0x12002d, 0x0}, - {0x22002d, 0x0}, - {0x200c7, 0x21}, - {0x1200c7, 0x21}, - {0x2200c7, 0x21}, - {0x200ca, 0x24}, - {0x1200ca, 0x24}, - {0x2200ca, 0x24}, + { 0x100a0, 0x0 }, + { 0x100a1, 0x1 }, + { 0x100a2, 0x2 }, + { 0x100a3, 0x3 }, + { 0x100a4, 0x4 }, + { 0x100a5, 0x5 }, + { 0x100a6, 0x6 }, + { 0x100a7, 0x7 }, + { 0x110a0, 0x0 }, + { 0x110a1, 0x1 }, + { 0x110a2, 0x3 }, + { 0x110a3, 0x4 }, + { 0x110a4, 0x5 }, + { 0x110a5, 0x2 }, + { 0x110a6, 0x7 }, + { 0x110a7, 0x6 }, + { 0x120a0, 0x0 }, + { 0x120a1, 0x1 }, + { 0x120a2, 0x3 }, + { 0x120a3, 0x2 }, + { 0x120a4, 0x5 }, + { 0x120a5, 0x4 }, + { 0x120a6, 0x7 }, + { 0x120a7, 0x6 }, + { 0x130a0, 0x0 }, + { 0x130a1, 0x1 }, + { 0x130a2, 0x2 }, + { 0x130a3, 0x3 }, + { 0x130a4, 0x4 }, + { 0x130a5, 0x5 }, + { 0x130a6, 0x6 }, + { 0x130a7, 0x7 }, + { 0x1005f, 0x1ff }, + { 0x1015f, 0x1ff }, + { 0x1105f, 0x1ff }, + { 0x1115f, 0x1ff }, + { 0x1205f, 0x1ff }, + { 0x1215f, 0x1ff }, + { 0x1305f, 0x1ff }, + { 0x1315f, 0x1ff }, + { 0x11005f, 0x1ff }, + { 0x11015f, 0x1ff }, + { 0x11105f, 0x1ff }, + { 0x11115f, 0x1ff }, + { 0x11205f, 0x1ff }, + { 0x11215f, 0x1ff }, + { 0x11305f, 0x1ff }, + { 0x11315f, 0x1ff }, + { 0x21005f, 0x1ff }, + { 0x21015f, 0x1ff }, + { 0x21105f, 0x1ff }, + { 0x21115f, 0x1ff }, + { 0x21205f, 0x1ff }, + { 0x21215f, 0x1ff }, + { 0x21305f, 0x1ff }, + { 0x21315f, 0x1ff }, + { 0x55, 0x1ff }, + { 0x1055, 0x1ff }, + { 0x2055, 0x1ff }, + { 0x3055, 0x1ff }, + { 0x4055, 0x1ff }, + { 0x5055, 0x1ff }, + { 0x6055, 0x1ff }, + { 0x7055, 0x1ff }, + { 0x8055, 0x1ff }, + { 0x9055, 0x1ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 0x7 }, + { 0x2200c5, 0x7 }, + { 0x2002e, 0x2 }, + { 0x12002e, 0x2 }, + { 0x22002e, 0x2 }, + { 0x90204, 0x0 }, + { 0x190204, 0x0 }, + { 0x290204, 0x0 }, + { 0x20024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x120024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x220024, 0x1ab }, + { 0x2003a, 0x0 }, + { 0x20056, 0x3 }, + { 0x120056, 0x3 }, + { 0x220056, 0x3 }, + { 0x1004d, 0xe00 }, + { 0x1014d, 0xe00 }, + { 0x1104d, 0xe00 }, + { 0x1114d, 0xe00 }, + { 0x1204d, 0xe00 }, + { 0x1214d, 0xe00 }, + { 0x1304d, 0xe00 }, + { 0x1314d, 0xe00 }, + { 0x11004d, 0xe00 }, + { 0x11014d, 0xe00 }, + { 0x11104d, 0xe00 }, + { 0x11114d, 0xe00 }, + { 0x11204d, 0xe00 }, + { 0x11214d, 0xe00 }, + { 0x11304d, 0xe00 }, + { 0x11314d, 0xe00 }, + { 0x21004d, 0xe00 }, + { 0x21014d, 0xe00 }, + { 0x21104d, 0xe00 }, + { 0x21114d, 0xe00 }, + { 0x21204d, 0xe00 }, + { 0x21214d, 0xe00 }, + { 0x21304d, 0xe00 }, + { 0x21314d, 0xe00 }, + { 0x10049, 0xeba }, + { 0x10149, 0xeba }, + { 0x11049, 0xeba }, + { 0x11149, 0xeba }, + { 0x12049, 0xeba }, + { 0x12149, 0xeba }, + { 0x13049, 0xeba }, + { 0x13149, 0xeba }, + { 0x110049, 0xeba }, + { 0x110149, 0xeba }, + { 0x111049, 0xeba }, + { 0x111149, 0xeba }, + { 0x112049, 0xeba }, + { 0x112149, 0xeba }, + { 0x113049, 0xeba }, + { 0x113149, 0xeba }, + { 0x210049, 0xeba }, + { 0x210149, 0xeba }, + { 0x211049, 0xeba }, + { 0x211149, 0xeba }, + { 0x212049, 0xeba }, + { 0x212149, 0xeba }, + { 0x213049, 0xeba }, + { 0x213149, 0xeba }, + { 0x43, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 0x3 }, + { 0x20075, 0x4 }, + { 0x20050, 0x0 }, + { 0x20008, 0x2ee }, + { 0x120008, 0x64 }, + { 0x220008, 0x19 }, + { 0x20088, 0x9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x5a1 }, + { 0x10143, 0x5a1 }, + { 0x11043, 0x5a1 }, + { 0x11143, 0x5a1 }, + { 0x12043, 0x5a1 }, + { 0x12143, 0x5a1 }, + { 0x13043, 0x5a1 }, + { 0x13143, 0x5a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x5a1 }, + { 0x110143, 0x5a1 }, + { 0x111043, 0x5a1 }, + { 0x111143, 0x5a1 }, + { 0x112043, 0x5a1 }, + { 0x112143, 0x5a1 }, + { 0x113043, 0x5a1 }, + { 0x113143, 0x5a1 }, + { 0x2200b2, 0xdc }, + { 0x210043, 0x5a1 }, + { 0x210143, 0x5a1 }, + { 0x211043, 0x5a1 }, + { 0x211143, 0x5a1 }, + { 0x212043, 0x5a1 }, + { 0x212143, 0x5a1 }, + { 0x213043, 0x5a1 }, + { 0x213143, 0x5a1 }, + { 0x200fa, 0x1 }, + { 0x1200fa, 0x1 }, + { 0x2200fa, 0x1 }, + { 0x20019, 0x1 }, + { 0x120019, 0x1 }, + { 0x220019, 0x1 }, + { 0x200f0, 0x660 }, + { 0x200f1, 0x0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5665 }, + { 0x200f5, 0x0 }, + { 0x200f6, 0x0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0x0 }, + { 0x2002d, 0x0 }, + { 0x12002d, 0x0 }, + { 0x22002d, 0x0 }, + { 0x200c7, 0x21 }, + { 0x1200c7, 0x21 }, + { 0x2200c7, 0x21 }, + { 0x200ca, 0x24 }, + { 0x1200ca, 0x24 }, + { 0x2200ca, 0x24 }, };
/* ddr phy trained csr */ @@ -1044,757 +1044,757 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xbb8}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x131f}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x5400d, 0x100}, - {0x54012, 0x310}, - {0x54019, 0x2dd4}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x2dd4}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x3}, - {0x54032, 0xd400}, - {0x54033, 0x312d}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0xd400}, - {0x54039, 0x312d}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x131f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, };
/* P1 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp1_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x101}, - {0x54003, 0x190}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x5400d, 0x100}, - {0x54012, 0x310}, - {0x54019, 0x84}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x84}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x3}, - {0x54032, 0x8400}, - {0x54033, 0x3100}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0x8400}, - {0x54039, 0x3100}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, + { 0xd0000, 0x0 }, + { 0x54002, 0x101 }, + { 0x54003, 0x190 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, };
/* P2 message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp2_cfg[] = { - {0xd0000, 0x0}, - {0x54002, 0x102}, - {0x54003, 0x64}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x121f}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x5400d, 0x100}, - {0x54012, 0x310}, - {0x54019, 0x84}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x84}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x3}, - {0x54032, 0x8400}, - {0x54033, 0x3100}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0x8400}, - {0x54039, 0x3100}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, - {0xd0000, 0x1}, + { 0xd0000, 0x0 }, + { 0x54002, 0x102 }, + { 0x54003, 0x64 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x121f }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400d, 0x100 }, + { 0x54012, 0x310 }, + { 0x54019, 0x84 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x84 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0x8400 }, + { 0x54033, 0x3100 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0x8400 }, + { 0x54039, 0x3100 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, + { 0xd0000, 0x1 }, };
/* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { - {0xd0000, 0x0}, - {0x54003, 0xbb8}, - {0x54004, 0x2}, - {0x54005, 0x2228}, - {0x54006, 0x11}, - {0x54008, 0x61}, - {0x54009, 0xc8}, - {0x5400b, 0x2}, - {0x5400f, 0x100}, - {0x54010, 0x1f7f}, - {0x54012, 0x310}, - {0x54019, 0x2dd4}, - {0x5401a, 0x31}, - {0x5401b, 0x4d66}, - {0x5401c, 0x4d00}, - {0x5401e, 0x16}, - {0x5401f, 0x2dd4}, - {0x54020, 0x31}, - {0x54021, 0x4d66}, - {0x54022, 0x4d00}, - {0x54024, 0x16}, - {0x5402b, 0x1000}, - {0x5402c, 0x3}, - {0x54032, 0xd400}, - {0x54033, 0x312d}, - {0x54034, 0x6600}, - {0x54035, 0x4d}, - {0x54036, 0x4d}, - {0x54037, 0x1600}, - {0x54038, 0xd400}, - {0x54039, 0x312d}, - {0x5403a, 0x6600}, - {0x5403b, 0x4d}, - {0x5403c, 0x4d}, - {0x5403d, 0x1600}, + { 0xd0000, 0x0 }, + { 0x54003, 0xbb8 }, + { 0x54004, 0x2 }, + { 0x54005, 0x2228 }, + { 0x54006, 0x11 }, + { 0x54008, 0x61 }, + { 0x54009, 0xc8 }, + { 0x5400b, 0x2 }, + { 0x5400f, 0x100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x310 }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4d66 }, + { 0x5401c, 0x4d00 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4d66 }, + { 0x54022, 0x4d00 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, 0x3 }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x4d }, + { 0x54036, 0x4d }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x4d }, + { 0x5403c, 0x4d }, + { 0x5403d, 0x1600 }, { 0xd0000, 0x1 }, };
/* DRAM PHY init engine image */ struct dram_cfg_param ddr_phy_pie[] = { - {0xd0000, 0x0}, - {0x90000, 0x10}, - {0x90001, 0x400}, - {0x90002, 0x10e}, - {0x90003, 0x0}, - {0x90004, 0x0}, - {0x90005, 0x8}, - {0x90029, 0xb}, - {0x9002a, 0x480}, - {0x9002b, 0x109}, - {0x9002c, 0x8}, - {0x9002d, 0x448}, - {0x9002e, 0x139}, - {0x9002f, 0x8}, - {0x90030, 0x478}, - {0x90031, 0x109}, - {0x90032, 0x0}, - {0x90033, 0xe8}, - {0x90034, 0x109}, - {0x90035, 0x2}, - {0x90036, 0x10}, - {0x90037, 0x139}, - {0x90038, 0xf}, - {0x90039, 0x7c0}, - {0x9003a, 0x139}, - {0x9003b, 0x44}, - {0x9003c, 0x630}, - {0x9003d, 0x159}, - {0x9003e, 0x14f}, - {0x9003f, 0x630}, - {0x90040, 0x159}, - {0x90041, 0x47}, - {0x90042, 0x630}, - {0x90043, 0x149}, - {0x90044, 0x4f}, - {0x90045, 0x630}, - {0x90046, 0x179}, - {0x90047, 0x8}, - {0x90048, 0xe0}, - {0x90049, 0x109}, - {0x9004a, 0x0}, - {0x9004b, 0x7c8}, - {0x9004c, 0x109}, - {0x9004d, 0x0}, - {0x9004e, 0x1}, - {0x9004f, 0x8}, - {0x90050, 0x0}, - {0x90051, 0x45a}, - {0x90052, 0x9}, - {0x90053, 0x0}, - {0x90054, 0x448}, - {0x90055, 0x109}, - {0x90056, 0x40}, - {0x90057, 0x630}, - {0x90058, 0x179}, - {0x90059, 0x1}, - {0x9005a, 0x618}, - {0x9005b, 0x109}, - {0x9005c, 0x40c0}, - {0x9005d, 0x630}, - {0x9005e, 0x149}, - {0x9005f, 0x8}, - {0x90060, 0x4}, - {0x90061, 0x48}, - {0x90062, 0x4040}, - {0x90063, 0x630}, - {0x90064, 0x149}, - {0x90065, 0x0}, - {0x90066, 0x4}, - {0x90067, 0x48}, - {0x90068, 0x40}, - {0x90069, 0x630}, - {0x9006a, 0x149}, - {0x9006b, 0x10}, - {0x9006c, 0x4}, - {0x9006d, 0x18}, - {0x9006e, 0x0}, - {0x9006f, 0x4}, - {0x90070, 0x78}, - {0x90071, 0x549}, - {0x90072, 0x630}, - {0x90073, 0x159}, - {0x90074, 0xd49}, - {0x90075, 0x630}, - {0x90076, 0x159}, - {0x90077, 0x94a}, - {0x90078, 0x630}, - {0x90079, 0x159}, - {0x9007a, 0x441}, - {0x9007b, 0x630}, - {0x9007c, 0x149}, - {0x9007d, 0x42}, - {0x9007e, 0x630}, - {0x9007f, 0x149}, - {0x90080, 0x1}, - {0x90081, 0x630}, - {0x90082, 0x149}, - {0x90083, 0x0}, - {0x90084, 0xe0}, - {0x90085, 0x109}, - {0x90086, 0xa}, - {0x90087, 0x10}, - {0x90088, 0x109}, - {0x90089, 0x9}, - {0x9008a, 0x3c0}, - {0x9008b, 0x149}, - {0x9008c, 0x9}, - {0x9008d, 0x3c0}, - {0x9008e, 0x159}, - {0x9008f, 0x18}, - {0x90090, 0x10}, - {0x90091, 0x109}, - {0x90092, 0x0}, - {0x90093, 0x3c0}, - {0x90094, 0x109}, - {0x90095, 0x18}, - {0x90096, 0x4}, - {0x90097, 0x48}, - {0x90098, 0x18}, - {0x90099, 0x4}, - {0x9009a, 0x58}, - {0x9009b, 0xa}, - {0x9009c, 0x10}, - {0x9009d, 0x109}, - {0x9009e, 0x2}, - {0x9009f, 0x10}, - {0x900a0, 0x109}, - {0x900a1, 0x5}, - {0x900a2, 0x7c0}, - {0x900a3, 0x109}, - {0x900a4, 0x10}, - {0x900a5, 0x10}, - {0x900a6, 0x109}, - {0x40000, 0x811}, - {0x40020, 0x880}, - {0x40040, 0x0}, - {0x40060, 0x0}, - {0x40001, 0x4008}, - {0x40021, 0x83}, - {0x40041, 0x4f}, - {0x40061, 0x0}, - {0x40002, 0x4040}, - {0x40022, 0x83}, - {0x40042, 0x51}, - {0x40062, 0x0}, - {0x40003, 0x811}, - {0x40023, 0x880}, - {0x40043, 0x0}, - {0x40063, 0x0}, - {0x40004, 0x720}, - {0x40024, 0xf}, - {0x40044, 0x1740}, - {0x40064, 0x0}, - {0x40005, 0x16}, - {0x40025, 0x83}, - {0x40045, 0x4b}, - {0x40065, 0x0}, - {0x40006, 0x716}, - {0x40026, 0xf}, - {0x40046, 0x2001}, - {0x40066, 0x0}, - {0x40007, 0x716}, - {0x40027, 0xf}, - {0x40047, 0x2800}, - {0x40067, 0x0}, - {0x40008, 0x716}, - {0x40028, 0xf}, - {0x40048, 0xf00}, - {0x40068, 0x0}, - {0x40009, 0x720}, - {0x40029, 0xf}, - {0x40049, 0x1400}, - {0x40069, 0x0}, - {0x4000a, 0xe08}, - {0x4002a, 0xc15}, - {0x4004a, 0x0}, - {0x4006a, 0x0}, - {0x4000b, 0x623}, - {0x4002b, 0x15}, - {0x4004b, 0x0}, - {0x4006b, 0x0}, - {0x4000c, 0x4028}, - {0x4002c, 0x80}, - {0x4004c, 0x0}, - {0x4006c, 0x0}, - {0x4000d, 0xe08}, - {0x4002d, 0xc1a}, - {0x4004d, 0x0}, - {0x4006d, 0x0}, - {0x4000e, 0x623}, - {0x4002e, 0x1a}, - {0x4004e, 0x0}, - {0x4006e, 0x0}, - {0x4000f, 0x4040}, - {0x4002f, 0x80}, - {0x4004f, 0x0}, - {0x4006f, 0x0}, - {0x40010, 0x2604}, - {0x40030, 0x15}, - {0x40050, 0x0}, - {0x40070, 0x0}, - {0x40011, 0x708}, - {0x40031, 0x5}, - {0x40051, 0x0}, - {0x40071, 0x2002}, - {0x40012, 0x8}, - {0x40032, 0x80}, - {0x40052, 0x0}, - {0x40072, 0x0}, - {0x40013, 0x2604}, - {0x40033, 0x1a}, - {0x40053, 0x0}, - {0x40073, 0x0}, - {0x40014, 0x708}, - {0x40034, 0xa}, - {0x40054, 0x0}, - {0x40074, 0x2002}, - {0x40015, 0x4040}, - {0x40035, 0x80}, - {0x40055, 0x0}, - {0x40075, 0x0}, - {0x40016, 0x60a}, - {0x40036, 0x15}, - {0x40056, 0x1200}, - {0x40076, 0x0}, - {0x40017, 0x61a}, - {0x40037, 0x15}, - {0x40057, 0x1300}, - {0x40077, 0x0}, - {0x40018, 0x60a}, - {0x40038, 0x1a}, - {0x40058, 0x1200}, - {0x40078, 0x0}, - {0x40019, 0x642}, - {0x40039, 0x1a}, - {0x40059, 0x1300}, - {0x40079, 0x0}, - {0x4001a, 0x4808}, - {0x4003a, 0x880}, - {0x4005a, 0x0}, - {0x4007a, 0x0}, - {0x900a7, 0x0}, - {0x900a8, 0x790}, - {0x900a9, 0x11a}, - {0x900aa, 0x8}, - {0x900ab, 0x7aa}, - {0x900ac, 0x2a}, - {0x900ad, 0x10}, - {0x900ae, 0x7b2}, - {0x900af, 0x2a}, - {0x900b0, 0x0}, - {0x900b1, 0x7c8}, - {0x900b2, 0x109}, - {0x900b3, 0x10}, - {0x900b4, 0x2a8}, - {0x900b5, 0x129}, - {0x900b6, 0x8}, - {0x900b7, 0x370}, - {0x900b8, 0x129}, - {0x900b9, 0xa}, - {0x900ba, 0x3c8}, - {0x900bb, 0x1a9}, - {0x900bc, 0xc}, - {0x900bd, 0x408}, - {0x900be, 0x199}, - {0x900bf, 0x14}, - {0x900c0, 0x790}, - {0x900c1, 0x11a}, - {0x900c2, 0x8}, - {0x900c3, 0x4}, - {0x900c4, 0x18}, - {0x900c5, 0xe}, - {0x900c6, 0x408}, - {0x900c7, 0x199}, - {0x900c8, 0x8}, - {0x900c9, 0x8568}, - {0x900ca, 0x108}, - {0x900cb, 0x18}, - {0x900cc, 0x790}, - {0x900cd, 0x16a}, - {0x900ce, 0x8}, - {0x900cf, 0x1d8}, - {0x900d0, 0x169}, - {0x900d1, 0x10}, - {0x900d2, 0x8558}, - {0x900d3, 0x168}, - {0x900d4, 0x70}, - {0x900d5, 0x788}, - {0x900d6, 0x16a}, - {0x900d7, 0x1ff8}, - {0x900d8, 0x85a8}, - {0x900d9, 0x1e8}, - {0x900da, 0x50}, - {0x900db, 0x798}, - {0x900dc, 0x16a}, - {0x900dd, 0x60}, - {0x900de, 0x7a0}, - {0x900df, 0x16a}, - {0x900e0, 0x8}, - {0x900e1, 0x8310}, - {0x900e2, 0x168}, - {0x900e3, 0x8}, - {0x900e4, 0xa310}, - {0x900e5, 0x168}, - {0x900e6, 0xa}, - {0x900e7, 0x408}, - {0x900e8, 0x169}, - {0x900e9, 0x6e}, - {0x900ea, 0x0}, - {0x900eb, 0x68}, - {0x900ec, 0x0}, - {0x900ed, 0x408}, - {0x900ee, 0x169}, - {0x900ef, 0x0}, - {0x900f0, 0x8310}, - {0x900f1, 0x168}, - {0x900f2, 0x0}, - {0x900f3, 0xa310}, - {0x900f4, 0x168}, - {0x900f5, 0x1ff8}, - {0x900f6, 0x85a8}, - {0x900f7, 0x1e8}, - {0x900f8, 0x68}, - {0x900f9, 0x798}, - {0x900fa, 0x16a}, - {0x900fb, 0x78}, - {0x900fc, 0x7a0}, - {0x900fd, 0x16a}, - {0x900fe, 0x68}, - {0x900ff, 0x790}, - {0x90100, 0x16a}, - {0x90101, 0x8}, - {0x90102, 0x8b10}, - {0x90103, 0x168}, - {0x90104, 0x8}, - {0x90105, 0xab10}, - {0x90106, 0x168}, - {0x90107, 0xa}, - {0x90108, 0x408}, - {0x90109, 0x169}, - {0x9010a, 0x58}, - {0x9010b, 0x0}, - {0x9010c, 0x68}, - {0x9010d, 0x0}, - {0x9010e, 0x408}, - {0x9010f, 0x169}, - {0x90110, 0x0}, - {0x90111, 0x8b10}, - {0x90112, 0x168}, - {0x90113, 0x0}, - {0x90114, 0xab10}, - {0x90115, 0x168}, - {0x90116, 0x0}, - {0x90117, 0x1d8}, - {0x90118, 0x169}, - {0x90119, 0x80}, - {0x9011a, 0x790}, - {0x9011b, 0x16a}, - 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}, + { 0x900bc, 0xc }, + { 0x900bd, 0x408 }, + { 0x900be, 0x199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x790 }, + { 0x900c1, 0x11a }, + { 0x900c2, 0x8 }, + { 0x900c3, 0x4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0xe }, + { 0x900c6, 0x408 }, + { 0x900c7, 0x199 }, + { 0x900c8, 0x8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x790 }, + { 0x900cd, 0x16a }, + { 0x900ce, 0x8 }, + { 0x900cf, 0x1d8 }, + { 0x900d0, 0x169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x788 }, + { 0x900d6, 0x16a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x1e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x798 }, + { 0x900dc, 0x16a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x7a0 }, + { 0x900df, 0x16a }, + { 0x900e0, 0x8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x168 }, + { 0x900e3, 0x8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x168 }, + { 0x900e6, 0xa }, + { 0x900e7, 0x408 }, + { 0x900e8, 0x169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0x0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0x0 }, + { 0x900ed, 0x408 }, + { 0x900ee, 0x169 }, + { 0x900ef, 0x0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x168 }, + { 0x900f2, 0x0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x1e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x798 }, + { 0x900fa, 0x16a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x7a0 }, + { 0x900fd, 0x16a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x790 }, + { 0x90100, 0x16a }, + { 0x90101, 0x8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x168 }, + { 0x90104, 0x8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x168 }, + { 0x90107, 0xa }, + { 0x90108, 0x408 }, + { 0x90109, 0x169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0x0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0x0 }, + { 0x9010e, 0x408 }, + { 0x9010f, 0x169 }, + { 0x90110, 0x0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x168 }, + { 0x90113, 0x0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x168 }, + { 0x90116, 0x0 }, + { 0x90117, 0x1d8 }, + { 0x90118, 0x169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x790 }, + { 0x9011b, 0x16a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x7aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0xa }, + { 0x90120, 0x0 }, + { 0x90121, 0x1e9 }, + { 0x90122, 0x8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x108 }, + { 0x90125, 0xf }, + { 0x90126, 0x408 }, + { 0x90127, 0x169 }, + { 0x90128, 0xc }, + { 0x90129, 0x0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 0x9 }, + { 0x9012c, 0x0 }, + { 0x9012d, 0x1a9 }, + { 0x9012e, 0x0 }, + { 0x9012f, 0x408 }, + { 0x90130, 0x169 }, + { 0x90131, 0x0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x108 }, + { 0x90134, 0x8 }, + { 0x90135, 0x7aa }, + { 0x90136, 0x6a }, + { 0x90137, 0x0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x790 }, + { 0x9013c, 0x16a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0x0 }, + { 0x9013f, 0x68 }, + { 0x90140, 0x8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x168 }, + { 0x90143, 0xf }, + { 0x90144, 0x408 }, + { 0x90145, 0x169 }, + { 0x90146, 0xc }, + { 0x90147, 0x0 }, + { 0x90148, 0x68 }, + { 0x90149, 0x0 }, + { 0x9014a, 0x408 }, + { 0x9014b, 0x169 }, + { 0x9014c, 0x0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x168 }, + { 0x9014f, 0x8 }, + { 0x90150, 0x3c8 }, + { 0x90151, 0x1a9 }, + { 0x90152, 0x3 }, + { 0x90153, 0x370 }, + { 0x90154, 0x129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x2aa }, + { 0x90157, 0x9 }, + { 0x90158, 0x0 }, + { 0x90159, 0x400 }, + { 0x9015a, 0x10e }, + { 0x9015b, 0x8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x109 }, + { 0x9015e, 0x0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x10c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x10c }, + { 0x90164, 0x8 }, + { 0x90165, 0x7c8 }, + { 0x90166, 0x101 }, + { 0x90167, 0x8 }, + { 0x90168, 0x0 }, + { 0x90169, 0x8 }, + { 0x9016a, 0x8 }, + { 0x9016b, 0x448 }, + { 0x9016c, 0x109 }, + { 0x9016d, 0xf }, + { 0x9016e, 0x7c0 }, + { 0x9016f, 0x109 }, + { 0x90170, 0x0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x630 }, + { 0x90175, 0x109 }, + { 0x90176, 0x8 }, + { 0x90177, 0x618 }, + { 0x90178, 0x109 }, + { 0x90179, 0x8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x109 }, + { 0x9017c, 0x0 }, + { 0x9017d, 0x7c8 }, + { 0x9017e, 0x109 }, + { 0x9017f, 0x8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x10c }, + { 0x90182, 0x0 }, + { 0x90183, 0x1 }, + { 0x90184, 0x8 }, + { 0x90185, 0x8 }, + { 0x90186, 0x4 }, + { 0x90187, 0x8 }, + { 0x90188, 0x8 }, + { 0x90189, 0x7c8 }, + { 0x9018a, 0x101 }, + { 0x90006, 0x0 }, + { 0x90007, 0x0 }, + { 0x90008, 0x8 }, + { 0x90009, 0x0 }, + { 0x9000a, 0x0 }, + { 0x9000b, 0x0 }, + { 0xd00e7, 0x400 }, + { 0x90017, 0x0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0x0 }, + { 0x400d1, 0x101 }, + { 0x400d2, 0x105 }, + { 0x400d3, 0x107 }, + { 0x400d4, 0x10f }, + { 0x400d5, 0x202 }, + { 0x400d6, 0x20a }, + { 0x400d7, 0x20b }, + { 0x2003a, 0x2 }, + { 0x2000b, 0x5d }, + { 0x2000c, 0xbb }, + { 0x2000d, 0x753 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0xc }, + { 0x12000c, 0x19 }, + { 0x12000d, 0xfa }, + { 0x12000e, 0x10 }, + { 0x22000b, 0x3 }, + { 0x22000c, 0x6 }, + { 0x22000d, 0x3e }, + { 0x22000e, 0x10 }, + { 0x9000c, 0x0 }, + { 0x9000d, 0x173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 0x3 }, + { 0x120010, 0x5a }, + { 0x120011, 0x3 }, + { 0x220010, 0x5a }, + { 0x220011, 0x3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x240080, 0xe0 }, + { 0x240081, 0x12 }, + { 0x240082, 0xe0 }, + { 0x240083, 0x12 }, + { 0x240084, 0xe0 }, + { 0x240085, 0x12 }, + { 0x400fd, 0xf }, + { 0x10011, 0x1 }, + { 0x10012, 0x1 }, + { 0x10013, 0x180 }, + { 0x10018, 0x1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 0x1 }, + { 0x101b4, 0x1 }, + { 0x102b4, 0x1 }, + { 0x103b4, 0x1 }, + { 0x104b4, 0x1 }, + { 0x105b4, 0x1 }, + { 0x106b4, 0x1 }, + { 0x107b4, 0x1 }, + { 0x108b4, 0x1 }, + { 0x11011, 0x1 }, + { 0x11012, 0x1 }, + { 0x11013, 0x180 }, + { 0x11018, 0x1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 0x1 }, + { 0x111b4, 0x1 }, + { 0x112b4, 0x1 }, + { 0x113b4, 0x1 }, + { 0x114b4, 0x1 }, + { 0x115b4, 0x1 }, + { 0x116b4, 0x1 }, + { 0x117b4, 0x1 }, + { 0x118b4, 0x1 }, + { 0x12011, 0x1 }, + { 0x12012, 0x1 }, + { 0x12013, 0x180 }, + { 0x12018, 0x1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 0x1 }, + { 0x121b4, 0x1 }, + { 0x122b4, 0x1 }, + { 0x123b4, 0x1 }, + { 0x124b4, 0x1 }, + { 0x125b4, 0x1 }, + { 0x126b4, 0x1 }, + { 0x127b4, 0x1 }, + { 0x128b4, 0x1 }, + { 0x13011, 0x1 }, + { 0x13012, 0x1 }, + { 0x13013, 0x180 }, + { 0x13018, 0x1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 0x1 }, + { 0x131b4, 0x1 }, + { 0x132b4, 0x1 }, + { 0x133b4, 0x1 }, + { 0x134b4, 0x1 }, + { 0x135b4, 0x1 }, + { 0x136b4, 0x1 }, + { 0x137b4, 0x1 }, + { 0x138b4, 0x1 }, + { 0x2003a, 0x2 }, + { 0xc0080, 0x2 }, + { 0xd0000, 0x1 } };
struct dram_fsp_msg ddr_dram_fsp_msg[] = { @@ -1818,7 +1818,7 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = ddr_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, + }, { /* P0 3000mts 2D */ .drate = 3000,
From: Frieder Schrempf frieder.schrempf@kontron.de Fix the spaces and alignment for easier tracking of changes and comparing with configs generated by the tools. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- arch/arm/dts/imx8mm-kontron-n801x-som.dtsi | 4 -- board/kontron/sl-mx8mm/lpddr4_timing.c | 49 +--------------------- board/kontron/sl-mx8mm/spl.c | 2 - 3 files changed, 1 insertion(+), 54 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi index 3b66e560927..39c0ce19ef1 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi @@ -46,10 +46,6 @@ ddrc_opp_table: opp-table { compatible = "operating-points-v2";
- opp-25M { - opp-hz = /bits/ 64 <25000000>; - }; - opp-100M { opp-hz = /bits/ 64 <100000000>; }; diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index a8dcaafb180..cdde6ac0dc0 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -1121,46 +1121,6 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0xd0000, 0x1 }, };
-/* P2 message block paremeter for training firmware */ -struct dram_cfg_param ddr_fsp2_cfg[] = { - { 0xd0000, 0x0 }, - { 0x54002, 0x102 }, - { 0x54003, 0x64 }, - { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, - { 0x54006, 0x11 }, - { 0x54008, 0x121f }, - { 0x54009, 0xc8 }, - { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, - { 0x54012, 0x310 }, - { 0x54019, 0x84 }, - { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, - { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, - { 0x5401f, 0x84 }, - { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, - { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, - { 0x5402b, 0x1000 }, - { 0x5402c, 0x3 }, - { 0x54032, 0x8400 }, - { 0x54033, 0x3100 }, - { 0x54034, 0x6600 }, - { 0x54035, 0x4d }, - { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, - { 0x54038, 0x8400 }, - { 0x54039, 0x3100 }, - { 0x5403a, 0x6600 }, - { 0x5403b, 0x4d }, - { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, - { 0xd0000, 0x1 }, -}; - /* P0 2D message block paremeter for training firmware */ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, @@ -1812,13 +1772,6 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = { .fsp_cfg = ddr_fsp1_cfg, .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), }, - { - /* P2 100mts 1D */ - .drate = 100, - .fw_type = FW_1D_IMAGE, - .fsp_cfg = ddr_fsp2_cfg, - .fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg), - }, { /* P0 3000mts 2D */ .drate = 3000, @@ -1840,5 +1793,5 @@ struct dram_timing_info dram_timing = { .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), .ddrphy_pie = ddr_phy_pie, .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), - .fsp_table = { 3000, 400, 100, }, + .fsp_table = { 3000, 400, }, }; diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 2a562f4ac97..447da13984e 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -95,8 +95,6 @@ static void spl_dram_init(void) dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1; - dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110; - dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
if (!ddr_init(&dram_timing)) { if (check_ram_available(SZ_2G))
From: Frieder Schrempf frieder.schrempf@kontron.de The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf frieder@fris.de wrote:
From: Frieder Schrempf frieder.schrempf@kontron.de
The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Frieder,
I just noticed this patch and was curious what it was about.
What do you mean by 'the new stable configuration is missing the 100mt setpoint'? Does this refer to something NXP has changed in their DDR config tools?
Best Regards,
Tim
Hi Tim,
On 21.10.22 21:24, Tim Harvey wrote:
On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf frieder@fris.de wrote:
From: Frieder Schrempf frieder.schrempf@kontron.de
The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Frieder,
I just noticed this patch and was curious what it was about.
What do you mean by 'the new stable configuration is missing the 100mt setpoint'? Does this refer to something NXP has changed in their DDR config tools?
At some point we started using 4GB LPDDR4 chips from Nanya on our SoMs while before we only had Micron chips. For some unknown reason (NXP couldn't explain it either), the only configuration that works for all used chips (Micron and Nanya) is only stable if the lowest of the three frequency setpoints is removed.
Unfortunately I have no idea how this behavior could be explained.
Best regards Frieder
On Mon, Oct 24, 2022 at 4:54 AM Frieder Schrempf frieder.schrempf@kontron.de wrote:
Hi Tim,
On 21.10.22 21:24, Tim Harvey wrote:
On Wed, Aug 24, 2022 at 7:01 AM Frieder Schrempf frieder@fris.de wrote:
From: Frieder Schrempf frieder.schrempf@kontron.de
The new stable configuration is missing the 100mt setpoint, remove it before updating the config to make sure the changes are separated cleanly.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Frieder,
I just noticed this patch and was curious what it was about.
What do you mean by 'the new stable configuration is missing the 100mt setpoint'? Does this refer to something NXP has changed in their DDR config tools?
At some point we started using 4GB LPDDR4 chips from Nanya on our SoMs while before we only had Micron chips. For some unknown reason (NXP couldn't explain it either), the only configuration that works for all used chips (Micron and Nanya) is only stable if the lowest of the three frequency setpoints is removed.
Unfortunately I have no idea how this behavior could be explained.
Frieder,
Ok - thanks for the explanation. I'm looking for ways to reduce the SPL impact of DRAM configs as I have 4 of them for imx8mm-venice that are keeping me from adding SDP support due to SPL size.
I wonder if binman and linker labels could be used to load dram configs.
Best Regards,
Tim
From: Frieder Schrempf frieder.schrempf@kontron.de
These parameters are needed for stable performance on new hardware with Nanya LPDDR4 chips.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- board/kontron/sl-mx8mm/lpddr4_timing.c | 184 +++++++------------------ board/kontron/sl-mx8mm/spl.c | 8 +- 2 files changed, 55 insertions(+), 137 deletions(-)
diff --git a/board/kontron/sl-mx8mm/lpddr4_timing.c b/board/kontron/sl-mx8mm/lpddr4_timing.c index cdde6ac0dc0..74b79c7a009 100644 --- a/board/kontron/sl-mx8mm/lpddr4_timing.c +++ b/board/kontron/sl-mx8mm/lpddr4_timing.c @@ -15,13 +15,13 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d400000, 0xa3080020 }, { 0x3d400020, 0x223 }, { 0x3d400024, 0x3a980 }, - { 0x3d400064, 0x5b0087 }, + { 0x3d400064, 0x5b00d2 }, { 0x3d4000d0, 0xc00305ba }, { 0x3d4000d4, 0x940000 }, { 0x3d4000dc, 0xd4002d }, { 0x3d4000e0, 0x310000 }, - { 0x3d4000e8, 0x66004d }, - { 0x3d4000ec, 0x16004d }, + { 0x3d4000e8, 0x63004d }, + { 0x3d4000ec, 0x15004d }, { 0x3d400100, 0x191e1920 }, { 0x3d400104, 0x60630 }, { 0x3d40010c, 0xb0b000 }, @@ -88,30 +88,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = { { 0x3d402190, 0x3818200 }, { 0x3d402194, 0x80303 }, { 0x3d4021b4, 0x100 }, - { 0x3d403020, 0x21 }, - { 0x3d403024, 0x1f40 }, - { 0x3d403050, 0x20d040 }, - { 0x3d403064, 0x30007 }, - { 0x3d4030dc, 0x840000 }, - { 0x3d4030e0, 0x310000 }, - { 0x3d4030e8, 0x66004d }, - { 0x3d4030ec, 0x16004d }, - { 0x3d403100, 0xa010102 }, - { 0x3d403104, 0x30404 }, - { 0x3d403108, 0x203060b }, - { 0x3d40310c, 0x505000 }, - { 0x3d403110, 0x2040202 }, - { 0x3d403114, 0x2030202 }, - { 0x3d403118, 0x1010004 }, - { 0x3d40311c, 0x301 }, - { 0x3d403130, 0x20300 }, - { 0x3d403134, 0xa100002 }, - { 0x3d403138, 0x8 }, - { 0x3d403144, 0x50003 }, - { 0x3d403180, 0x190004 }, - { 0x3d403190, 0x3818200 }, - { 0x3d403194, 0x80303 }, - { 0x3d4031b4, 0x100 }, + { 0x3d4020f4, 0xc99 }, { 0x3d400028, 0x0 }, };
@@ -165,14 +142,6 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x11215f, 0x1ff }, { 0x11305f, 0x1ff }, { 0x11315f, 0x1ff }, - { 0x21005f, 0x1ff }, - { 0x21015f, 0x1ff }, - { 0x21105f, 0x1ff }, - { 0x21115f, 0x1ff }, - { 0x21205f, 0x1ff }, - { 0x21215f, 0x1ff }, - { 0x21305f, 0x1ff }, - { 0x21315f, 0x1ff }, { 0x55, 0x1ff }, { 0x1055, 0x1ff }, { 0x2055, 0x1ff }, @@ -185,22 +154,16 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x9055, 0x1ff }, { 0x200c5, 0x19 }, { 0x1200c5, 0x7 }, - { 0x2200c5, 0x7 }, { 0x2002e, 0x2 }, { 0x12002e, 0x2 }, - { 0x22002e, 0x2 }, { 0x90204, 0x0 }, { 0x190204, 0x0 }, - { 0x290204, 0x0 }, { 0x20024, 0x1ab }, { 0x2003a, 0x0 }, { 0x120024, 0x1ab }, { 0x2003a, 0x0 }, - { 0x220024, 0x1ab }, - { 0x2003a, 0x0 }, { 0x20056, 0x3 }, { 0x120056, 0x3 }, - { 0x220056, 0x3 }, { 0x1004d, 0xe00 }, { 0x1014d, 0xe00 }, { 0x1104d, 0xe00 }, @@ -217,54 +180,37 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x11214d, 0xe00 }, { 0x11304d, 0xe00 }, { 0x11314d, 0xe00 }, - { 0x21004d, 0xe00 }, - { 0x21014d, 0xe00 }, - { 0x21104d, 0xe00 }, - { 0x21114d, 0xe00 }, - { 0x21204d, 0xe00 }, - { 0x21214d, 0xe00 }, - { 0x21304d, 0xe00 }, - { 0x21314d, 0xe00 }, - { 0x10049, 0xeba }, - { 0x10149, 0xeba }, - { 0x11049, 0xeba }, - { 0x11149, 0xeba }, - { 0x12049, 0xeba }, - { 0x12149, 0xeba }, - { 0x13049, 0xeba }, - { 0x13149, 0xeba }, - { 0x110049, 0xeba }, - { 0x110149, 0xeba }, - { 0x111049, 0xeba }, - { 0x111149, 0xeba }, - { 0x112049, 0xeba }, - { 0x112149, 0xeba }, - { 0x113049, 0xeba }, - { 0x113149, 0xeba }, - { 0x210049, 0xeba }, - { 0x210149, 0xeba }, - { 0x211049, 0xeba }, - { 0x211149, 0xeba }, - { 0x212049, 0xeba }, - { 0x212149, 0xeba }, - { 0x213049, 0xeba }, - { 0x213149, 0xeba }, - { 0x43, 0x63 }, - { 0x1043, 0x63 }, - { 0x2043, 0x63 }, - { 0x3043, 0x63 }, - { 0x4043, 0x63 }, - { 0x5043, 0x63 }, - { 0x6043, 0x63 }, - { 0x7043, 0x63 }, - { 0x8043, 0x63 }, - { 0x9043, 0x63 }, + { 0x10049, 0x69a }, + { 0x10149, 0x69a }, + { 0x11049, 0x69a }, + { 0x11149, 0x69a }, + { 0x12049, 0x69a }, + { 0x12149, 0x69a }, + { 0x13049, 0x69a }, + { 0x13149, 0x69a }, + { 0x110049, 0x69a }, + { 0x110149, 0x69a }, + { 0x111049, 0x69a }, + { 0x111149, 0x69a }, + { 0x112049, 0x69a }, + { 0x112149, 0x69a }, + { 0x113049, 0x69a }, + { 0x113149, 0x69a }, + { 0x43, 0xe7 }, + { 0x1043, 0xe7 }, + { 0x2043, 0xe7 }, + { 0x3043, 0xe7 }, + { 0x4043, 0xe7 }, + { 0x5043, 0xe7 }, + { 0x6043, 0xe7 }, + { 0x7043, 0xe7 }, + { 0x8043, 0xe7 }, + { 0x9043, 0xe7 }, { 0x20018, 0x3 }, { 0x20075, 0x4 }, { 0x20050, 0x0 }, { 0x20008, 0x2ee }, { 0x120008, 0x64 }, - { 0x220008, 0x19 }, { 0x20088, 0x9 }, { 0x200b2, 0xdc }, { 0x10043, 0x5a1 }, @@ -284,39 +230,25 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = { { 0x112143, 0x5a1 }, { 0x113043, 0x5a1 }, { 0x113143, 0x5a1 }, - { 0x2200b2, 0xdc }, - { 0x210043, 0x5a1 }, - { 0x210143, 0x5a1 }, - { 0x211043, 0x5a1 }, - { 0x211143, 0x5a1 }, - { 0x212043, 0x5a1 }, - { 0x212143, 0x5a1 }, - { 0x213043, 0x5a1 }, - { 0x213143, 0x5a1 }, { 0x200fa, 0x1 }, { 0x1200fa, 0x1 }, - { 0x2200fa, 0x1 }, { 0x20019, 0x1 }, { 0x120019, 0x1 }, - { 0x220019, 0x1 }, - { 0x200f0, 0x660 }, + { 0x200f0, 0x60 }, { 0x200f1, 0x0 }, { 0x200f2, 0x4444 }, { 0x200f3, 0x8888 }, - { 0x200f4, 0x5665 }, + { 0x200f4, 0x5565 }, { 0x200f5, 0x0 }, { 0x200f6, 0x0 }, { 0x200f7, 0xf000 }, { 0x20025, 0x0 }, { 0x2002d, 0x0 }, { 0x12002d, 0x0 }, - { 0x22002d, 0x0 }, { 0x200c7, 0x21 }, { 0x1200c7, 0x21 }, - { 0x2200c7, 0x21 }, { 0x200ca, 0x24 }, { 0x1200ca, 0x24 }, - { 0x2200ca, 0x24 }, };
/* ddr phy trained csr */ @@ -1047,37 +979,36 @@ struct dram_cfg_param ddr_fsp0_cfg[] = { { 0xd0000, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, + { 0x54005, 0x3028 }, { 0x54006, 0x11 }, { 0x54008, 0x131f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d63 }, { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, + { 0x5401e, 0x15 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d63 }, { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, + { 0x54024, 0x15 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x6300 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, + { 0x54037, 0x1500 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x6300 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, + { 0x5403d, 0x1500 }, { 0xd0000, 0x1 }, };
@@ -1087,12 +1018,11 @@ struct dram_cfg_param ddr_fsp1_cfg[] = { { 0x54002, 0x101 }, { 0x54003, 0x190 }, { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, + { 0x54005, 0x3028 }, { 0x54006, 0x11 }, { 0x54008, 0x121f }, { 0x54009, 0xc8 }, { 0x5400b, 0x2 }, - { 0x5400d, 0x100 }, { 0x54012, 0x310 }, { 0x54019, 0x84 }, { 0x5401a, 0x31 }, @@ -1126,7 +1056,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0xd0000, 0x0 }, { 0x54003, 0xbb8 }, { 0x54004, 0x2 }, - { 0x54005, 0x2228 }, + { 0x54005, 0x3028 }, { 0x54006, 0x11 }, { 0x54008, 0x61 }, { 0x54009, 0xc8 }, @@ -1136,28 +1066,28 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = { { 0x54012, 0x310 }, { 0x54019, 0x2dd4 }, { 0x5401a, 0x31 }, - { 0x5401b, 0x4d66 }, + { 0x5401b, 0x4d63 }, { 0x5401c, 0x4d00 }, - { 0x5401e, 0x16 }, + { 0x5401e, 0x15 }, { 0x5401f, 0x2dd4 }, { 0x54020, 0x31 }, - { 0x54021, 0x4d66 }, + { 0x54021, 0x4d63 }, { 0x54022, 0x4d00 }, - { 0x54024, 0x16 }, + { 0x54024, 0x15 }, { 0x5402b, 0x1000 }, { 0x5402c, 0x3 }, { 0x54032, 0xd400 }, { 0x54033, 0x312d }, - { 0x54034, 0x6600 }, + { 0x54034, 0x6300 }, { 0x54035, 0x4d }, { 0x54036, 0x4d }, - { 0x54037, 0x1600 }, + { 0x54037, 0x1500 }, { 0x54038, 0xd400 }, { 0x54039, 0x312d }, - { 0x5403a, 0x6600 }, + { 0x5403a, 0x6300 }, { 0x5403b, 0x4d }, { 0x5403c, 0x4d }, - { 0x5403d, 0x1600 }, + { 0x5403d, 0x1500 }, { 0xd0000, 0x1 }, };
@@ -1659,10 +1589,6 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x12000c, 0x19 }, { 0x12000d, 0xfa }, { 0x12000e, 0x10 }, - { 0x22000b, 0x3 }, - { 0x22000c, 0x6 }, - { 0x22000d, 0x3e }, - { 0x22000e, 0x10 }, { 0x9000c, 0x0 }, { 0x9000d, 0x173 }, { 0x9000e, 0x60 }, @@ -1675,8 +1601,6 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x20011, 0x3 }, { 0x120010, 0x5a }, { 0x120011, 0x3 }, - { 0x220010, 0x5a }, - { 0x220011, 0x3 }, { 0x40080, 0xe0 }, { 0x40081, 0x12 }, { 0x40082, 0xe0 }, @@ -1689,12 +1613,6 @@ struct dram_cfg_param ddr_phy_pie[] = { { 0x140083, 0x12 }, { 0x140084, 0xe0 }, { 0x140085, 0x12 }, - { 0x240080, 0xe0 }, - { 0x240081, 0x12 }, - { 0x240082, 0xe0 }, - { 0x240083, 0x12 }, - { 0x240084, 0xe0 }, - { 0x240085, 0x12 }, { 0x400fd, 0xf }, { 0x10011, 0x1 }, { 0x10012, 0x1 }, diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 447da13984e..affdc136e10 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -89,10 +89,10 @@ static void spl_dram_init(void) dram_timing.ddrc_cfg[2].val = 0xa1080020; dram_timing.ddrc_cfg[37].val = 0x1f;
- dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110; - dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1; - dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110; - dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1; + dram_timing.fsp_msg[0].fsp_cfg[8].val = 0x110; + dram_timing.fsp_msg[0].fsp_cfg[20].val = 0x1; + dram_timing.fsp_msg[1].fsp_cfg[9].val = 0x110; + dram_timing.fsp_msg[1].fsp_cfg[21].val = 0x1; dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110; dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
From: Frieder Schrempf frieder.schrempf@kontron.de These parameters are needed for stable performance on new hardware with Nanya LPDDR4 chips. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
This sets an env variable 'som_type' from the board code. It can later be used by environment scripts, e. g. to select the proper devicetree for the board.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * use "sl" instead of deprected "n801x" identifier
Changes in v2: * add missing CONFIG_BOARD_LATE_INIT --- board/kontron/sl-mx8mm/sl-mx8mm.c | 6 ++++++ configs/kontron-sl-mx8mm_defconfig | 1 + 2 files changed, 7 insertions(+)
diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 416c4cbb407..6e73edeb232 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -121,6 +121,12 @@ int board_init(void) return 0; }
+int board_late_init(void) +{ + env_set("som_type", "sl"); + return 0; +} + enum env_location env_get_location(enum env_operation op, int prio) { enum boot_device boot_dev = get_boot_device(); diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index 5dcee988478..a5c48a3fbca 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -31,6 +31,7 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_OF_BOARD_SETUP=y CONFIG_BOARD_TYPES=y +CONFIG_BOARD_LATE_INIT=y CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x910000 CONFIG_SPL_BSS_MAX_SIZE=0x2000
From: Frieder Schrempf frieder.schrempf@kontron.de This sets an env variable 'som_type' from the board code. It can later be used by environment scripts, e. g. to select the proper devicetree for the board. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
This adjusts the names of the boards and SoMs to the official naming used by Kontron marketing. These changes also affect devicetree names and compatibles. The same changes have been submitted to the Linux kernel.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * also rename devicetree files and compatibles
Changes in v2: * none --- arch/arm/dts/Makefile | 2 +- ...on-n801x-s-u-boot.dtsi => imx8mm-kontron-bl-u-boot.dtsi} | 0 .../{imx8mm-kontron-n801x-s.dts => imx8mm-kontron-bl.dts} | 6 +++--- ...imx8mm-kontron-n801x-som.dtsi => imx8mm-kontron-sl.dtsi} | 4 ++-- board/kontron/sl-mx8mm/MAINTAINERS | 2 +- board/kontron/sl-mx8mm/spl.c | 3 ++- configs/kontron-sl-mx8mm_defconfig | 2 +- 7 files changed, 10 insertions(+), 9 deletions(-) rename arch/arm/dts/{imx8mm-kontron-n801x-s-u-boot.dtsi => imx8mm-kontron-bl-u-boot.dtsi} (100%) rename arch/arm/dts/{imx8mm-kontron-n801x-s.dts => imx8mm-kontron-bl.dts} (97%) rename arch/arm/dts/{imx8mm-kontron-n801x-som.dtsi => imx8mm-kontron-sl.dtsi} (98%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 75d0664cc01..1e21dbcc7ec 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -939,7 +939,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-evk.dtb \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ - imx8mm-kontron-n801x-s.dtb \ + imx8mm-kontron-bl.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi similarity index 100% rename from arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi rename to arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi diff --git a/arch/arm/dts/imx8mm-kontron-n801x-s.dts b/arch/arm/dts/imx8mm-kontron-bl.dts similarity index 97% rename from arch/arm/dts/imx8mm-kontron-n801x-s.dts rename to arch/arm/dts/imx8mm-kontron-bl.dts index 23be1ec538b..ca533baedcd 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-s.dts +++ b/arch/arm/dts/imx8mm-kontron-bl.dts @@ -5,11 +5,11 @@
/dts-v1/;
-#include "imx8mm-kontron-n801x-som.dtsi" +#include "imx8mm-kontron-sl.dtsi"
/ { - model = "Kontron i.MX8MM N801X S"; - compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + model = "Kontron BL i.MX8MM (N801X S)"; + compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
aliases { ethernet1 = &usbnet; diff --git a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi b/arch/arm/dts/imx8mm-kontron-sl.dtsi similarity index 98% rename from arch/arm/dts/imx8mm-kontron-n801x-som.dtsi rename to arch/arm/dts/imx8mm-kontron-sl.dtsi index 39c0ce19ef1..11a50cffc8c 100644 --- a/arch/arm/dts/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm/dts/imx8mm-kontron-sl.dtsi @@ -6,8 +6,8 @@ #include "imx8mm.dtsi"
/ { - model = "Kontron i.MX8MM N801X SoM"; - compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm"; + model = "Kontron SL i.MX8MM (N801X SOM)"; + compatible = "kontron,imx8mm-sl", "fsl,imx8mm";
memory@40000000 { device_type = "memory"; diff --git a/board/kontron/sl-mx8mm/MAINTAINERS b/board/kontron/sl-mx8mm/MAINTAINERS index 5e68ae0305a..e4e12d3f558 100644 --- a/board/kontron/sl-mx8mm/MAINTAINERS +++ b/board/kontron/sl-mx8mm/MAINTAINERS @@ -1,7 +1,7 @@ Kontron SL/BL i.MX8M Mini Boards (N801x) M: Frieder Schrempf frieder.schrempf@kontron.de S: Maintained -F: arch/arm/dts/imx8mm-kontron-n801x-* +F: arch/arm/dts/imx8mm-kontron* F: board/kontron/sl-mx8mm F: configs/kontron-sl-mx8mm_defconfig F: doc/board/kontron/sl-mx8mm.rst diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index affdc136e10..00e63659f4a 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -150,7 +150,8 @@ int do_board_detect(void) int board_fit_config_name_match(const char *name) { if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() && - !strncmp(name, "imx8mm-kontron-n801x-s", 22)) + (!strcmp(name, "imx8mm-kontron-n801x-s") || + !strcmp(name, "imx8mm-kontron-bl"))) return 0;
return -1; diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index a5c48a3fbca..b55243cf31b 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -11,7 +11,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg" CONFIG_DM_GPIO=y CONFIG_SPL_DM_SPI=y -CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s" +CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-bl" CONFIG_SPL_TEXT_BASE=0x7E1000 CONFIG_TARGET_KONTRON_MX8MM=y CONFIG_SPL_MMC=y
From: Frieder Schrempf frieder.schrempf@kontron.de This adjusts the names of the boards and SoMs to the official naming used by Kontron marketing. These changes also affect devicetree names and compatibles. The same changes have been submitted to the Linux kernel. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly.
Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly.
Reported-by: Heiko Thiery heiko.thiery@gmail.com Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Heiko Thiery heiko.thiery@gmail.com Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * add Heiko's R-b tag (thanks!) --- arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi | 5 ----- arch/arm/dts/imx8mm-kontron-bl.dts | 3 +++ arch/arm/dts/imx8mm-kontron-sl.dtsi | 2 -- 3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi index 2c62f05cec1..a42881d1a89 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi @@ -62,11 +62,6 @@
&pinctrl_pmic { u-boot,dm-spl; - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - /* Disable Pullup for SD_VSEL */ - MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41 - >; };
&pinctrl_uart3 { diff --git a/arch/arm/dts/imx8mm-kontron-bl.dts b/arch/arm/dts/imx8mm-kontron-bl.dts index ca533baedcd..a079322a379 100644 --- a/arch/arm/dts/imx8mm-kontron-bl.dts +++ b/arch/arm/dts/imx8mm-kontron-bl.dts @@ -321,6 +321,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; };
@@ -333,6 +334,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; };
@@ -345,6 +347,7 @@ MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 >; }; }; diff --git a/arch/arm/dts/imx8mm-kontron-sl.dtsi b/arch/arm/dts/imx8mm-kontron-sl.dtsi index 11a50cffc8c..7cfa7473475 100644 --- a/arch/arm/dts/imx8mm-kontron-sl.dtsi +++ b/arch/arm/dts/imx8mm-kontron-sl.dtsi @@ -103,7 +103,6 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators { reg_vdd_soc: BUCK1 { @@ -246,7 +245,6 @@ pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 - MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 >; };
From: Frieder Schrempf frieder.schrempf@kontron.de It turns out that it is not necessary to declare the VSELECT signal as GPIO and let the PMIC driver set it to a fixed high level. This switches the voltage between 3.3V and 1.8V by setting the PMIC register for LDO5 accordingly. Instead we can do it like other boards already do and simply mux the VSELECT signal of the USDHC interface to the pin. This makes sure that the correct voltage is selected by setting the PMIC's SD_VSEL input to high or low accordingly. Reported-by: Heiko Thiery heiko.thiery@gmail.com Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Heiko Thiery heiko.thiery@gmail.com Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Improve the naming of the regulators to contain the voltage rail names from the schematic.
Suggested-by: Heiko Thiery heiko.thiery@gmail.com Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * none --- arch/arm/dts/imx8mm-kontron-sl.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-sl.dtsi b/arch/arm/dts/imx8mm-kontron-sl.dtsi index 7cfa7473475..0679728d248 100644 --- a/arch/arm/dts/imx8mm-kontron-sl.dtsi +++ b/arch/arm/dts/imx8mm-kontron-sl.dtsi @@ -106,7 +106,7 @@
regulators { reg_vdd_soc: BUCK1 { - regulator-name = "buck1"; + regulator-name = "+0V8_VDD_SOC (BUCK1)"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <850000>; regulator-boot-on; @@ -117,7 +117,7 @@ };
reg_vdd_arm: BUCK2 { - regulator-name = "buck2"; + regulator-name = "+0V9_VDD_ARM (BUCK2)"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; @@ -128,7 +128,7 @@ };
reg_vdd_dram: BUCK3 { - regulator-name = "buck3"; + regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; regulator-min-microvolt = <850000>; regulator-max-microvolt = <950000>; regulator-boot-on; @@ -136,7 +136,7 @@ };
reg_vdd_3v3: BUCK4 { - regulator-name = "buck4"; + regulator-name = "+3V3 (BUCK4)"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-boot-on; @@ -144,7 +144,7 @@ };
reg_vdd_1v8: BUCK5 { - regulator-name = "buck5"; + regulator-name = "+1V8 (BUCK5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -152,7 +152,7 @@ };
reg_nvcc_dram: BUCK6 { - regulator-name = "buck6"; + regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; regulator-boot-on; @@ -160,7 +160,7 @@ };
reg_nvcc_snvs: LDO1 { - regulator-name = "ldo1"; + regulator-name = "+1V8_NVCC_SNVS (LDO1)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -168,7 +168,7 @@ };
reg_vdd_snvs: LDO2 { - regulator-name = "ldo2"; + regulator-name = "+0V8_VDD_SNVS (LDO2)"; regulator-min-microvolt = <800000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -176,7 +176,7 @@ };
reg_vdda: LDO3 { - regulator-name = "ldo3"; + regulator-name = "+1V8_VDDA (LDO3)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-boot-on; @@ -184,7 +184,7 @@ };
reg_vdd_phy: LDO4 { - regulator-name = "ldo4"; + regulator-name = "+0V9_VDD_PHY (LDO4)"; regulator-min-microvolt = <900000>; regulator-max-microvolt = <900000>; regulator-boot-on; @@ -192,7 +192,7 @@ };
reg_nvcc_sd: LDO5 { - regulator-name = "ldo5"; + regulator-name = "NVCC_SD (LDO5)"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; };
From: Frieder Schrempf frieder.schrempf@kontron.de Improve the naming of the regulators to contain the voltage rail names from the schematic. Suggested-by: Heiko Thiery heiko.thiery@gmail.com Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Refactor the code a bit without any functional changes.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * fix printing of RAM size
Changes in v2: * fix printf warning * remove unused pinmux definitions --- board/kontron/sl-mx8mm/spl.c | 31 ++++++------------------------- 1 file changed, 6 insertions(+), 25 deletions(-)
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 00e63659f4a..403ab9a3ea2 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -39,11 +39,6 @@ static iomux_v3_cfg_t const i2c1_pads[] = { IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION };
-static iomux_v3_cfg_t const i2c2_pads[] = { - IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION, - IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION -}; - int spl_board_boot_device(enum boot_device boot_dev_spl) { switch (boot_dev_spl) { @@ -109,41 +104,27 @@ static void spl_dram_init(void) size = 1; }
- printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size); + gd->ram_size = size; writel(size, M4_BOOTROM_BASE_ADDR); }
-static int i2c_detect(u8 bus, u16 addr) -{ - struct udevice *udev; - int ret; - - /* - * Try to probe the touch controller to check if an LVDS panel is - * connected. - */ - ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev); - if (ret == 0) - return 0; - - return 1; -} - int do_board_detect(void) { + gd->board_type = BOARD_TYPE_KTN_N801X; + printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", + (unsigned int)gd->ram_size); + /* * Check the I2C PMIC to detect the deprecated SoM with DA9063. */ imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
- if (i2c_detect(0, 0x58) == 0) { + if (i2c_get_chip_for_busnum(0, 0x58, 0, &udev) == 0) { printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n"); printf("### THIS HW IS NOT SUPPORTED AND BOOTING WILL PROBABLY FAIL ###\n"); printf("### PLEASE UPGRADE TO LATEST MODULE ###\n"); }
- gd->board_type = BOARD_TYPE_KTN_N801X; - return 0; }
From: Frieder Schrempf frieder.schrempf@kontron.de Refactor the code a bit without any functional changes. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
This adds support for the Kontron Electronics SoM SL i.MX8MM OSM-S and the matching baseboard BL i.MX8MM OSM-S.
The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm).
The existing board configuration for the non-OSM SoM is reused and allows to detect the SoM variant at runtime.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * fix OSM-S SoM name to match official name * fix docs to match official board names * adjust devicetree names and compatibles * fix printing of RAM size * add missing Makefile entry for new dtb * fix hex numbers and unit addresses in SPI NOR partitions
Changes in v2: * none --- arch/arm/dts/Makefile | 1 + .../dts/imx8mm-kontron-bl-common-u-boot.dtsi | 139 +++++++ .../dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi | 6 + arch/arm/dts/imx8mm-kontron-bl-osm-s.dts | 376 ++++++++++++++++++ arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi | 139 +------ arch/arm/dts/imx8mm-kontron-osm-s.dtsi | 330 +++++++++++++++ board/kontron/sl-mx8mm/sl-mx8mm.c | 7 +- board/kontron/sl-mx8mm/spl.c | 25 +- configs/kontron-sl-mx8mm_defconfig | 2 + doc/board/kontron/sl-mx8mm.rst | 13 +- 10 files changed, 893 insertions(+), 145 deletions(-) create mode 100644 arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mm-kontron-bl-osm-s.dts create mode 100644 arch/arm/dts/imx8mm-kontron-osm-s.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1e21dbcc7ec..93982968547 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -940,6 +940,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mm-icore-mx8mm-ctouch2.dtb \ imx8mm-icore-mx8mm-edimm2.2.dtb \ imx8mm-kontron-bl.dtb \ + imx8mm-kontron-bl-osm-s.dtb \ imx8mm-mx8menlo.dtb \ imx8mm-venice.dtb \ imx8mm-venice-gw71xx-0x.dtb \ diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi new file mode 100644 index 00000000000..e7e900d4fa8 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2019 Kontron Electronics GmbH + */ + +#include "imx8mm-u-boot.dtsi" + +/ { + aliases { + usb0 = &usbotg1; + usb1 = &usbotg2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + u-boot,dm-spl; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; +}; + +&crypto { + u-boot,dm-spl; +}; + +&sec_jr0 { + u-boot,dm-spl; +}; + +&sec_jr1 { + u-boot,dm-spl; +}; + +&sec_jr2 { + u-boot,dm-spl; +}; + +&i2c1 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&i2c2 { + status = "okay"; + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-spl; +}; + +&pinctrl_i2c1 { + u-boot,dm-spl; +}; + +&pinctrl_pmic { + u-boot,dm-spl; +}; + +&pinctrl_uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&pinctrl_usdhc1 { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_100mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc1_200mhz { + u-boot,dm-spl; +}; + +&pinctrl_usdhc2 { + u-boot,dm-spl; +}; + +&pca9450 { + u-boot,dm-spl; +}; + +&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { + u-boot,dm-spl; +}; + +&ecspi1 { + u-boot,dm-spl; +}; + +&gpio1 { + u-boot,dm-spl; +}; + +&gpio2 { + u-boot,dm-spl; +}; + +&gpio3 { + u-boot,dm-spl; +}; + +&gpio4 { + u-boot,dm-spl; +}; + +&gpio5 { + u-boot,dm-spl; +}; + +&uart3 { + u-boot,dm-spl; + u-boot,dm-pre-reloc; +}; + +&usdhc1 { + u-boot,dm-spl; +}; + +&usdhc2 { + u-boot,dm-spl; +}; + +&wdog1 { + u-boot,dm-spl; +}; + +&pinctrl_wdog { + u-boot,dm-spl; +}; diff --git a/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi new file mode 100644 index 00000000000..cd990b16720 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include "imx8mm-kontron-bl-common-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts b/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts new file mode 100644 index 00000000000..8b16bd68576 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-bl-osm-s.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +/dts-v1/; + +#include "imx8mm-kontron-osm-s.dtsi" + +/ { + model = "Kontron BL i.MX8MM OSM-S (N802X S)"; + compatible = "kontron,imx8mm-bl-osm-s", "kontron,imx8mm-osm-s", "fsl,imx8mm"; + + aliases { + ethernet1 = &usbnet; + }; + + /* fixed crystal dedicated to mcp2542fd */ + osc_can: clock-osc-can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + clock-output-names = "osc-can"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led1 { + label = "led1"; + gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + + led2 { + label = "led2"; + gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; + }; + + led3 { + label = "led3"; + gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; + }; + }; + + pwm-beeper { + compatible = "pwm-beeper"; + pwms = <&pwm2 0 5000 0>; + }; + + reg_rst_eth2: regulator-rst-eth2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_eth2>; + gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + regulator-name = "rst-usb-eth2"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_vbus>; + gpio = <&gpio3 25 GPIO_ACTIVE_LOW>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "usb1-vbus"; + }; + + reg_vdd_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-name = "vdd-5v"; + }; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + can@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can>; + clocks = <&osc_can>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_LEVEL_LOW>; + /* + * Limit the SPI clock to 15 MHz to prevent issues + * with corrupted data due to chip errata. + */ + spi-max-frequency = <15000000>; + vdd-supply = <®_vdd_3v3>; + xceiver-supply = <®_vdd_5v>; + }; +}; + +&ecspi3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>; + status = "okay"; + + eeram@0 { + compatible = "microchip,48l640"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-connection-type = "rgmii-rxid"; + phy-handle = <ðphy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + reset-assert-us = <1>; + reset-deassert-us = <15000>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + gpio-line-names = "", "", "", "dio1-out", "", "", "dio1-in", "dio2-out", + "dio2-in", "dio3-out", "dio3-in", "dio4-out", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>; + gpio-line-names = "", "", "dio4-in", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; +}; + +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + dr_mode = "otg"; + disable-over-current; + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + usb1@1 { + compatible = "usb424,9514"; + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + usbnet: ethernet@1 { + compatible = "usb424,ec00"; + reg = <1>; + local-mac-address = [ 00 00 00 00 00 00 ]; + }; + }; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_nvcc_sd>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can: cangrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82 + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82 + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19 + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82 + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x19 /* PHY RST */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* ETH IRQ */ + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19 + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x19 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19 + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pwm2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19 + >; + }; + + pinctrl_reg_usb1_vbus: regusb1vbusgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140 + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140 + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140 + >; + }; + + pinctrl_usb_eth2: usbeth2grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi index a42881d1a89..cd990b16720 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi @@ -1,139 +1,6 @@ -// SPDX-License-Identifier: GPL-2.0+ +// SPDX-License-Identifier: GPL-2.0+ OR MIT /* - * Copyright (C) 2019 Kontron Electronics GmbH + * Copyright (C) 2022 Kontron Electronics GmbH */
-#include "imx8mm-u-boot.dtsi" - -/ { - aliases { - usb0 = &usbotg1; - usb1 = &usbotg2; - }; - - wdt-reboot { - compatible = "wdt-reboot"; - wdt = <&wdog1>; - u-boot,dm-spl; - }; - - firmware { - optee { - compatible = "linaro,optee-tz"; - method = "smc"; - }; - }; -}; - -&crypto { - u-boot,dm-spl; -}; - -&sec_jr0 { - u-boot,dm-spl; -}; - -&sec_jr1 { - u-boot,dm-spl; -}; - -&sec_jr2 { - u-boot,dm-spl; -}; - -&i2c1 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&i2c2 { - status = "okay"; - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&pinctrl_ecspi1 { - u-boot,dm-spl; -}; - -&pinctrl_i2c1 { - u-boot,dm-spl; -}; - -&pinctrl_pmic { - u-boot,dm-spl; -}; - -&pinctrl_uart3 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&pinctrl_usdhc1 { - u-boot,dm-spl; -}; - -&pinctrl_usdhc1_100mhz { - u-boot,dm-spl; -}; - -&pinctrl_usdhc1_200mhz { - u-boot,dm-spl; -}; - -&pinctrl_usdhc2 { - u-boot,dm-spl; -}; - -&pca9450 { - u-boot,dm-spl; -}; - -&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} { - u-boot,dm-spl; -}; - -&ecspi1 { - u-boot,dm-spl; -}; - -&gpio1 { - u-boot,dm-spl; -}; - -&gpio2 { - u-boot,dm-spl; -}; - -&gpio3 { - u-boot,dm-spl; -}; - -&gpio4 { - u-boot,dm-spl; -}; - -&gpio5 { - u-boot,dm-spl; -}; - -&uart3 { - u-boot,dm-spl; - u-boot,dm-pre-reloc; -}; - -&usdhc1 { - u-boot,dm-spl; -}; - -&usdhc2 { - u-boot,dm-spl; -}; - -&wdog1 { - u-boot,dm-spl; -}; - -&pinctrl_wdog { - u-boot,dm-spl; -}; +#include "imx8mm-kontron-bl-common-u-boot.dtsi" diff --git a/arch/arm/dts/imx8mm-kontron-osm-s.dtsi b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi new file mode 100644 index 00000000000..8d10f5b4129 --- /dev/null +++ b/arch/arm/dts/imx8mm-kontron-osm-s.dtsi @@ -0,0 +1,330 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright (C) 2022 Kontron Electronics GmbH + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include "imx8mm.dtsi" + +/ { + model = "Kontron OSM-S i.MX8MM (N802X SOM)"; + compatible = "kontron,imx8mm-osm-s", "fsl,imx8mm"; + + memory@40000000 { + device_type = "memory"; + /* + * There are multiple SoM flavors with different DDR sizes. + * The smallest is 1GB. For larger sizes the bootloader will + * update the reg property. + */ + reg = <0x0 0x40000000 0 0x80000000>; + }; + + chosen { + stdout-path = &uart3; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ddrc { + operating-points-v2 = <&ddrc_opp_table>; + + ddrc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100M { + opp-hz = /bits/ 64 <100000000>; + }; + + opp-750M { + opp-hz = /bits/ 64 <750000000>; + }; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + flash@0 { + compatible = "mxicy,mx25r1635f", "jedec,spi-nor"; + spi-max-frequency = <80000000>; + reg = <0>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x1e0000>; + }; + + partition@1e0000 { + label = "env"; + reg = <0x1e0000 0x10000>; + }; + + partition@1f0000 { + label = "env_redundant"; + reg = <0x1f0000 0x10000>; + }; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pca9450: pmic@25 { + compatible = "nxp,pca9450a"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupt-parent = <&gpio1>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "+0V8_VDD_SOC (BUCK1)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <850000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <850000>; + nxp,dvs-standby-voltage = <800000>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "+0V9_VDD_ARM (BUCK2)"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_dram: BUCK3 { + regulator-name = "+0V9_VDD_DRAM&PU (BUCK3)"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <950000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "+3V3 (BUCK4)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "+1V8 (BUCK5)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram: BUCK6 { + regulator-name = "+1V1_NVCC_DRAM (BUCK6)"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs: LDO1 { + regulator-name = "+1V8_NVCC_SNVS (LDO1)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_snvs: LDO2 { + regulator-name = "+0V8_VDD_SNVS (LDO2)"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda: LDO3 { + regulator-name = "+1V8_VDDA (LDO3)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_phy: LDO4 { + regulator-name = "+0V9_VDD_PHY (LDO4)"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd: LDO5 { + regulator-name = "NVCC_SD (LDO5)"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; + + rtc@52 { + compatible = "microcrystal,rv3028"; + reg = <0x52>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio4 1 IRQ_TYPE_LEVEL_HIGH>; + trickle-diode-disable; + }; +}; + +&uart3 { /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 6e73edeb232..641130112aa 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -123,7 +123,12 @@ int board_init(void)
int board_late_init(void) { - env_set("som_type", "sl"); + if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") || + !fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-osm-s")) { + env_set("som_type", "osm-s"); + else + env_set("som_type", "sl"); + return 0; }
diff --git a/board/kontron/sl-mx8mm/spl.c b/board/kontron/sl-mx8mm/spl.c index 403ab9a3ea2..8e7d017688b 100644 --- a/board/kontron/sl-mx8mm/spl.c +++ b/board/kontron/sl-mx8mm/spl.c @@ -29,6 +29,7 @@ DECLARE_GLOBAL_DATA_PTR;
enum { BOARD_TYPE_KTN_N801X, + BOARD_TYPE_KTN_N802X, BOARD_TYPE_MAX };
@@ -110,9 +111,22 @@ static void spl_dram_init(void)
int do_board_detect(void) { - gd->board_type = BOARD_TYPE_KTN_N801X; - printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", - (unsigned int)gd->ram_size); + struct udevice *udev; + + /* + * Check for the RTC on the OSM module. + */ + imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads)); + + if (i2c_get_chip_for_busnum(0, 0x52, 0, &udev) == 0) { + gd->board_type = BOARD_TYPE_KTN_N802X; + printf("Kontron OSM-S i.MX8MM (N802X) module, %u GB RAM detected\n", + (unsigned int)gd->ram_size); + } else { + gd->board_type = BOARD_TYPE_KTN_N801X; + printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", + (unsigned int)gd->ram_size); + }
/* * Check the I2C PMIC to detect the deprecated SoM with DA9063. @@ -135,6 +149,11 @@ int board_fit_config_name_match(const char *name) !strcmp(name, "imx8mm-kontron-bl"))) return 0;
+ if (gd->board_type == BOARD_TYPE_KTN_N802X && is_imx8mm() && + (!strcmp(name, "imx8mm-kontron-n802x-s") || + !strcmp(name, "imx8mm-kontron-bl-osm-s"))) + return 0; + return -1; }
diff --git a/configs/kontron-sl-mx8mm_defconfig b/configs/kontron-sl-mx8mm_defconfig index b55243cf31b..2883e322707 100644 --- a/configs/kontron-sl-mx8mm_defconfig +++ b/configs/kontron-sl-mx8mm_defconfig @@ -74,6 +74,7 @@ CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_LIST="imx8mm-kontron-bl imx8mm-kontron-bl-osm-s" CONFIG_ENV_IS_IN_MMC=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y @@ -122,6 +123,7 @@ CONFIG_SPL_DM_PMIC_PCA9450=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_PCA9450=y CONFIG_DM_RTC=y +CONFIG_RTC_RV3028=y CONFIG_RTC_RV8803=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y diff --git a/doc/board/kontron/sl-mx8mm.rst b/doc/board/kontron/sl-mx8mm.rst index 7a4c1134b54..f022e0979b1 100644 --- a/doc/board/kontron/sl-mx8mm.rst +++ b/doc/board/kontron/sl-mx8mm.rst @@ -1,13 +1,16 @@ .. SPDX-License-Identifier: GPL-2.0+
-Kontron Electronics SL i.MX8MM SoM -================================== +Kontron Electronics i.MX8MM SoMs and Boards +===========================================
-The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module +The SL i.MX8MM and OSM-S i.MX8MM by Kontron Electronics GmbH are SoM modules with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
-The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0, -HDMI/LVDS, SD card, CAN, RS485, RS232 and much more. +The matching evaluation boards (Board-Line, BL) have two Ethernet ports, +USB 2.0, HDMI/LVDS, SD card, CAN, RS485, RS232 and much more. + +The OSM-S i.MX8MM is compliant to the Open Standard Module (OSM) 1.0 +specification, size S (https://sget.org/standards/osm).
Quick Start -----------
From: Frieder Schrempf frieder.schrempf@kontron.de This adds support for the Kontron Electronics SoM SL i.MX8MM OSM-S and the matching baseboard BL i.MX8MM OSM-S. The SoM hardware complies to the Open Standard Module (OSM) 1.0 specification, size S (https://sget.org/standards/osm). The existing board configuration for the non-OSM SoM is reused and allows to detect the SoM variant at runtime. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de
Enable the I2C bus and set a env variable for the reset GPIO of the touch controller. This allows us to probe the panel in a script.
Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de --- Changes in v3: * none
Changes in v2: * new patch --- arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi | 13 +++++++++++-- arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi | 8 ++++++++ arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi | 8 ++++++++ board/kontron/sl-mx8mm/sl-mx8mm.c | 5 ++++- 4 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi index e7e900d4fa8..5b8b472159a 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-common-u-boot.dtsi @@ -48,8 +48,17 @@
&i2c2 { status = "okay"; - u-boot,dm-spl; - u-boot,dm-pre-reloc; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; };
&pinctrl_ecspi1 { diff --git a/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi index cd990b16720..fac24a21fbf 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-osm-s-u-boot.dtsi @@ -4,3 +4,11 @@ */
#include "imx8mm-kontron-bl-common-u-boot.dtsi" + +&iomuxc { + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */ + >; + }; +}; diff --git a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi index cd990b16720..e9fa8d7b2a1 100644 --- a/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi +++ b/arch/arm/dts/imx8mm-kontron-bl-u-boot.dtsi @@ -4,3 +4,11 @@ */
#include "imx8mm-kontron-bl-common-u-boot.dtsi" + +&iomuxc { + pinctrl_touch: touchgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Touch Reset */ + >; + }; +}; diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 641130112aa..4ac430b29a9 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -126,8 +126,11 @@ int board_late_init(void) if (!fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-n802x-som") || !fdt_node_check_compatible(gd->fdt_blob, 0, "kontron,imx8mm-osm-s")) { env_set("som_type", "osm-s"); - else + env_set("touch_rst_gpio", "111"); + } else { env_set("som_type", "sl"); + env_set("touch_rst_gpio", "87"); + }
return 0; }
From: Frieder Schrempf frieder.schrempf@kontron.de Enable the I2C bus and set a env variable for the reset GPIO of the touch controller. This allows us to probe the panel in a script. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
From: Frieder Schrempf frieder.schrempf@kontron.de Nowadays detecting the SPI NOR as boot device from the ROMAPI is fixed and works even if the SPI NOR is used as fallback boot device. Therefore we don't need this workaround anymore. Signed-off-by: Frieder Schrempf frieder.schrempf@kontron.de Reviewed-by: Fabio Estevam festevam@denx.de
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (4)
-
Frieder Schrempf -
Frieder Schrempf -
sbabic＠denx.de -
Tim Harvey