Need this function for autoboot keyd

Signed-off-by: Matthias Weisser weisserm@arcor.de --- arch/arm/cpu/arm926ejs/mx25/timer.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 14f0c2d..7c8a71b 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -187,3 +187,15 @@ void __udelay (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_MX25_CLK32; + return tbclk; +}

Adding support for USB host on imx25 using the internal PHY

Signed-off-by: Matthias Weisser weisserm@arcor.de --- drivers/usb/host/ehci-mxc.c | 28 ++++++++++++++++++++++++++-- 1 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 6af35ab..eca430f 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -29,6 +29,14 @@

#define USBCTRL_OTGBASE_OFFSET 0x600

+#ifdef CONFIG_MX25 +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) +#define MX25_USB_CTRL_HSTD_BIT (1<<5) +#define MX25_USB_CTRL_USBTE_BIT (1<<4) +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#endif + +#ifdef CONFIG_MX31 #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) @@ -42,10 +50,19 @@ #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#endif

static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; + +#ifdef CONFIG_MX25 + v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | + MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; + + writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); +#endif + #ifdef CONFIG_MX31 v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET);

@@ -94,27 +111,34 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)

int ehci_hcd_init(void) { - u32 tmp; struct usb_ehci *ehci; +#ifdef CONFIG_MX31 + u32 tmp; struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE;

tmp = __raw_readl(&sc_regs->ccmr); __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; +#endif

udelay(80);

/* Take USB2 */ +#ifdef CONFIG_MX25 + ehci = (struct usb_ehci *)(IMX_USB_BASE + +#else ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + +#endif (0x200 * CONFIG_MXC_USB_PORT)); hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); +#ifdef CONFIG_MX31 setbits_le32(&ehci->control, USB_EN);

__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - +#endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);

udelay(10000);

zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an optional NAND flash.

Signed-off-by: Matthias Weisser weisserm@arcor.de --- MAINTAINERS | 1 + board/syteco/zmx25/Makefile | 51 +++++++++ board/syteco/zmx25/lowlevel_init.S | 136 +++++++++++++++++++++++ board/syteco/zmx25/zmx25.c | 209 ++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/zmx25.h | 182 +++++++++++++++++++++++++++++++ 6 files changed, 580 insertions(+), 0 deletions(-) create mode 100644 board/syteco/zmx25/Makefile create mode 100644 board/syteco/zmx25/lowlevel_init.S create mode 100644 board/syteco/zmx25/zmx25.c create mode 100644 include/configs/zmx25.h

diff --git a/MAINTAINERS b/MAINTAINERS index 2bba7b4..5b633af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -892,6 +892,7 @@ Lei Wen leiwen@marvell.com Matthias Weisser weisserm@arcor.de

jadecpu ARM926EJS (MB86R01 SoC) + zmx25 ARM926EJS (imx25 SoC)

Richard Woodruff r-woodruff2@ti.com

diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile new file mode 100644 index 0000000..5a0e5b3 --- /dev/null +++ b/board/syteco/zmx25/Makefile @@ -0,0 +1,51 @@ +# +# (c) 2010 Graf-Syteco, Matthias Weisser +# weisserm@arcor.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += zmx25.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S new file mode 100644 index 0000000..4f3b756 --- /dev/null +++ b/board/syteco/zmx25/lowlevel_init.S @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2010 + * Matthias Weisser weisserm@arcor.de + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +.macro init_aips + write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777 +.endm + +.macro init_max + write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 + + write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 + + write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +.endm + +/* + * clocks + */ +.macro init_clocks + + /* disable clock output */ + write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 + write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff + write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff + write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff + + /* Devide NAND clock by 32 */ + write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F +.endm + +/* + * sdram controller init + */ +.macro init_lpddr + ldr r0, =IMX_ESDRAMC_BASE + ldr r2, =IMX_SDRAM_BANK0_BASE + + /* + * reset SDRAM controller + * then wait for initialization to complete + */ + ldr r1, =(1 << 1) | (1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] +1: ldr r3, [r0, #ESDRAMC_ESDMISC] + tst r3, #(1 << 31) + beq 1b + ldr r1, =(1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] + + ldr r1, =0x002a7420 + str r1, [r0, #ESDRAMC_ESDCFG0] + + /* control | precharge */ + ldr r1, =0x92216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* dram command encoded in address */ + str r1, [r2, #0x400] + + /* auto refresh */ + ldr r1, =0xa2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* read dram twice to auto refresh */ + ldr r3, [r2] + ldr r3, [r2] + + /* control | load mode */ + ldr r1, =0xb2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + + /* mode register of lpddram */ + strb r1, [r2, #0x33] + + /* extended mode register of lpddrram */ + ldr r2, =0x81000000 + strb r1, [r2] + + /* control | normal */ + ldr r1, =0x82216008 + str r1, [r0, #ESDRAMC_ESDCTL0] +.endm + +.globl lowlevel_init +lowlevel_init: + init_aips + init_max + init_clocks + init_lpddr + mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c new file mode 100644 index 0000000..c27ad20 --- /dev/null +++ b/board/syteco/zmx25/zmx25.c @@ -0,0 +1,209 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * weisserm@arcor.de + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx25-pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_FEC_MXC +void tx25_fec_init(void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 val; + u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; + + /* + * fec pin init is generic + */ + mx25_fec_init_pins(); + + /* + * Set up LAN-RESET and FEC_RX_ERR + * + * LAN-RESET: gpio3[16] is ALT 5 mode of pin U20 + * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); + writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); + + /* assert PHY reset (low) */ + val = readl(&gpio3->dr) & ~(1 << 16); + writel(val, &gpio3->dr); + val = readl(&gpio3->dir) | (1 << 16); + writel(val, &gpio3->dir); + + udelay(5000); + + /* deassert PHY reset */ + val = readl(&gpio3->dr) | 1 << 16; + writel(val, &gpio3->dr); + + udelay(5000); +} +#else +#define tx25_fec_init() +#endif + +int board_init() +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + struct iomuxc_pad_input_select *inputselect; + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6); + u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1); + u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2); + struct gpio_regs *gpio1 = (struct gpio_regs *)IMX_GPIO1_BASE; + struct gpio_regs *gpio3 = (struct gpio_regs *)IMX_GPIO3_BASE; + struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; + + icache_enable(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE; + + /* Setup of core volatage selection pin to run at 1.4V */ + writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ + writel(readl(&gpio1->dr) | (1 << 15), &gpio3->dr); + writel(readl(&gpio1->dir) | (1 << 15), &gpio3->dir); + + /* Setup of input daisy chains for SD card pins*/ + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3); + + /* Setup of digital output for USB power and OC */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ + writel(readl(&gpio1->dr) | (1 << 28), &gpio1->dr); + writel(readl(&gpio1->dir) | (1 << 28), &gpio1->dir); + writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[28] */ + writel(readl(&gpio1->dir) & ~(1 << 27), &gpio1->dir); + + /* Setup of digital output control pins */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/ + writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/ + + writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */ + writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ + + /* Setup of key input pin GPIO2[29]*/ + writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); + writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ + + /* Switch both output drivers off */ + writel(readl(&gpio1->dr) & ~(1 << 7), &gpio1->dr); + writel(readl(&gpio1->dir) | (1 << 7), &gpio1->dir); + writel(readl(&gpio1->dr) & ~(1 << 6), &gpio1->dr); + writel(readl(&gpio1->dir) | (1 << 6), &gpio1->dir); + + /* Setup of status LED outputs */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ + + /* Switch both LEDs off */ + writel(readl(&gpio4->dr) & ~(1 << 21), &gpio4->dr); + writel(readl(&gpio4->dir) | (1 << 21), &gpio4->dir); + writel(readl(&gpio1->dr) & ~(1 << 29), &gpio1->dr); + writel(readl(&gpio1->dir) | (1 << 29), &gpio1->dir); + + /* Setup of CAN1 and CAN2 signals */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */ + + /* Setup of input daisy chains for CAN signals*/ + writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */ + writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */ + + /* Setup of I2C3 signals */ + writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */ + writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */ + + /* Setup of input daisy chains for I2C3 signals*/ + writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */ + writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */ + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ZMX25; + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + struct gpio_regs *gpio1 = (struct gpio_regs *)IMX_GPIO1_BASE; + struct gpio_regs *gpio2 = (struct gpio_regs *)IMX_GPIO2_BASE; + struct gpio_regs *gpio4 = (struct gpio_regs *)IMX_GPIO4_BASE; + const char *e; + + tx25_fec_init(); + + e = getenv("gs_base_board"); + if (e != NULL) { + if (strcmp(e, "G283") == 0) { + int key = readl(&gpio2->dr) & (1<<29) ? 0 : 1; + + if (key) { + /* Switch on both LEDs to inidcate boot mode */ + writel(readl(&gpio1->dr) | (1 << 29), + &gpio1->dr); + writel(readl(&gpio4->dr) | (1 << 21), + &gpio4->dr); + setenv("preboot", "run gs_slow_boot"); + } else + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/boards.cfg b/boards.cfg index dfefc3f..5af3b88 100644 --- a/boards.cfg +++ b/boards.cfg @@ -127,6 +127,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 nhk8815 arm arm926ejs nhk8815 st nomadik diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h new file mode 100644 index 0000000..fae01ff --- /dev/null +++ b/include/configs/zmx25.h @@ -0,0 +1,182 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * weisserm@arcor.de + * + * Configuation settings for the zmx25 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX25 +#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ + "bootm 0x81000000; bootelf 0x81000000\0" \ + "" + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define BOARD_LATE_INIT 1 + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * Serial + */ +#define CONFIG_MXC_UART 1 +#define CONFIG_SYS_MX25_UART2 1 +#define CONFIG_CONS_INDEX 1 /* use UART2 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x00 +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE 1 +#define CONFIG_BOOTP_BOOTPATH 1 +#define CONFIG_BOOTP_GATEWAY 1 +#define CONFIG_BOOTP_HOSTNAME 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_CACHE +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_LOADS +#undef CONFIG_CMD_SOURCE +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Additional command + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MXC +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORT 2 +#define CONFIG_MXC_USB_PORTSC 0xC0000000 +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_SYS_PROMPT "zmx25> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP 1 +#define CONFIG_CMDLINE_EDITING 1 + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#endif /* __CONFIG_H */

Need this function for autoboot keyd

Signed-off-by: Matthias Weisser weisserm@arcor.de --- arch/arm/cpu/arm926ejs/mx25/timer.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx25/timer.c b/arch/arm/cpu/arm926ejs/mx25/timer.c index 14f0c2d..7c8a71b 100644 --- a/arch/arm/cpu/arm926ejs/mx25/timer.c +++ b/arch/arm/cpu/arm926ejs/mx25/timer.c @@ -187,3 +187,15 @@ void __udelay (unsigned long usec) while (get_ticks() < tmp) /* loop till event */ /*NOP*/; } + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + ulong tbclk; + + tbclk = CONFIG_MX25_CLK32; + return tbclk; +}

imx25 used the wrong reset.c from imx27

Signed-off-by: Matthias Weisser weisserm@arcor.de --- Changes in v2: - Removed unrelated change

arch/arm/cpu/arm926ejs/mx25/Makefile | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 38d7f03..3c2a65e 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -24,12 +24,10 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(SOC).o

-COBJS = generic.o timer.o -MX27OBJS = reset.o +COBJS = generic.o timer.o reset.o

SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) -SRCS += $(addprefix $(SRCTREE)/arch/arm/cpu/arm926ejs/mx27/,$(MX27OBJS:.o=.c)) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS) $(MX27OBJS)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))

all: $(obj).depend $(LIB)

Adding support for USB host on imx25 using the internal PHY. Changing the name of base address define for imx31 to get some unification.

Signed-off-by: Matthias Weisser weisserm@arcor.de --- Changes in v2: - Partially unified for imx25 and imx31

arch/arm/include/asm/arch-mx31/imx-regs.h | 2 +- drivers/usb/host/ehci-mxc.c | 33 ++++++++++++++++++++++------- 2 files changed, 26 insertions(+), 9 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h index 306f966..3c8d607 100644 --- a/arch/arm/include/asm/arch-mx31/imx-regs.h +++ b/arch/arm/include/asm/arch-mx31/imx-regs.h @@ -746,7 +746,7 @@ enum iomux_pins { #define IRAM_SIZE (16 * 1024)

#define MX31_AIPS1_BASE_ADDR 0x43f00000 -#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) +#define IMX_USB_BASE (MX31_AIPS1_BASE_ADDR + 0x88000)

/* USB portsc */ /* values for portsc field */ diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c index 6af35ab..a0cfbb7 100644 --- a/drivers/usb/host/ehci-mxc.c +++ b/drivers/usb/host/ehci-mxc.c @@ -29,6 +29,14 @@

#define USBCTRL_OTGBASE_OFFSET 0x600

+#ifdef CONFIG_MX25 +#define MX25_USB_CTRL_IP_PUE_DOWN_BIT (1<<6) +#define MX25_USB_CTRL_HSTD_BIT (1<<5) +#define MX25_USB_CTRL_USBTE_BIT (1<<4) +#define MX25_USB_CTRL_OCPOL_OTG_BIT (1<<3) +#endif + +#ifdef CONFIG_MX31 #define MX31_OTG_SIC_SHIFT 29 #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT) #define MX31_OTG_PM_BIT (1 << 24) @@ -42,12 +50,19 @@ #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT) #define MX31_H1_PM_BIT (1 << 8) #define MX31_H1_DT_BIT (1 << 4) +#endif

static int mxc_set_usbcontrol(int port, unsigned int flags) { unsigned int v; + +#ifdef CONFIG_MX25 + v = MX25_USB_CTRL_IP_PUE_DOWN_BIT | MX25_USB_CTRL_HSTD_BIT | + MX25_USB_CTRL_USBTE_BIT | MX25_USB_CTRL_OCPOL_OTG_BIT; +#endif + #ifdef CONFIG_MX31 - v = readl(MX31_OTG_BASE_ADDR + USBCTRL_OTGBASE_OFFSET); + v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);

switch (port) { case 0: /* OTG port */ @@ -85,36 +100,38 @@ static int mxc_set_usbcontrol(int port, unsigned int flags) default: return -EINVAL; } - - writel(v, MX31_OTG_BASE_ADDR + - USBCTRL_OTGBASE_OFFSET); #endif - return 0; + + writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); + return 0; }

int ehci_hcd_init(void) { - u32 tmp; struct usb_ehci *ehci; +#ifdef CONFIG_MX31 + u32 tmp; struct clock_control_regs *sc_regs = (struct clock_control_regs *)CCM_BASE;

tmp = __raw_readl(&sc_regs->ccmr); __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ; +#endif

udelay(80);

/* Take USB2 */ - ehci = (struct usb_ehci *)(MX31_OTG_BASE_ADDR + + ehci = (struct usb_ehci *)(IMX_USB_BASE + (0x200 * CONFIG_MXC_USB_PORT)); hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t) hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); +#ifdef CONFIG_MX31 setbits_le32(&ehci->control, USB_EN);

__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); - +#endif mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);

udelay(10000);

Offsets to registers may be needed in asm code. This patch adds automated generation of these offsets form C structures.

Signed-off-by: Matthias Weisser weisserm@arcor.de --- Changes in v2: - Added a change in Makefile which was in wrong patch of the patch set

arch/arm/cpu/arm926ejs/mx25/Makefile | 2 + arch/arm/cpu/arm926ejs/mx25/asm-offsets.c | 60 +++++++++++++++++++++++++++++ arch/arm/include/asm/arch-mx25/imx-regs.h | 39 +++++++++++++++++++ 3 files changed, 101 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/arm926ejs/mx25/asm-offsets.c

diff --git a/arch/arm/cpu/arm926ejs/mx25/Makefile b/arch/arm/cpu/arm926ejs/mx25/Makefile index 3c2a65e..9219c06 100644 --- a/arch/arm/cpu/arm926ejs/mx25/Makefile +++ b/arch/arm/cpu/arm926ejs/mx25/Makefile @@ -34,6 +34,8 @@ all: $(obj).depend $(LIB) $(LIB): $(OBJS) $(call cmd_link_o_target, $(OBJS))

+$(OBJS) : $(TOPDIR)/include/asm/arch/asm-offsets.h + #########################################################################

# defines $(obj).depend target diff --git a/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c new file mode 100644 index 0000000..ba8dfd4 --- /dev/null +++ b/arch/arm/cpu/arm926ejs/mx25/asm-offsets.c @@ -0,0 +1,60 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <common.h> +#include <asm/arch/imx-regs.h> + +#include <linux/kbuild.h> + +int main(void) +{ + /* Clock Control Module */ + DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl)); + DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0)); + DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1)); + DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2)); + DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2])); + DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr)); + + /* Enhanced SDRAM Controller */ + DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0)); + DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0)); + DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc)); + + /* Multi-Layer AHB Crossbar Switch */ + DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0)); + DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0)); + DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1)); + DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1)); + DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2)); + DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2)); + DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3)); + DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3)); + DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4)); + DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4)); + DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0)); + DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1)); + DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2)); + DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3)); + DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4)); + + /* AHB <-> IP-Bus Interface */ + DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7)); + DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15)); + + return 0; +} diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 55ad115..62ee4d5 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -141,6 +141,45 @@ struct fuse_bank0_regs { u32 mac_addr[6]; };

+/* Multi-Layer AHB Crossbar Switch (MAX) registers */ +struct max_regs { + u32 mpr0; + u32 pad00[3]; + u32 sgpcr0; + u32 pad01[59]; + u32 mpr1; + u32 pad02[3]; + u32 sgpcr1; + u32 pad03[59]; + u32 mpr2; + u32 pad04[3]; + u32 sgpcr2; + u32 pad05[59]; + u32 mpr3; + u32 pad06[3]; + u32 sgpcr3; + u32 pad07[59]; + u32 mpr4; + u32 pad08[3]; + u32 sgpcr4; + u32 pad09[251]; + u32 mgpcr0; + u32 pad10[63]; + u32 mgpcr1; + u32 pad11[63]; + u32 mgpcr2; + u32 pad12[63]; + u32 mgpcr3; + u32 pad13[63]; + u32 mgpcr4; +}; + +/* AHB <-> IP-Bus Interface (AIPS) */ +struct aips_regs { + u32 mpr_0_7; + u32 mpr_8_15; +}; + #endif

/* AIPS 1 */

Adding support for mxc_gpio driver for imx25 and fix names of registers in tx25 board.

Signed-off-by: Matthias Weisser weisserm@arcor.de --- Changes in v2: - New in patch set due to review of v1

arch/arm/include/asm/arch-mx25/imx-regs.h | 10 ++++++++-- board/karo/tx25/tx25.c | 26 +++++++++++++------------- include/mxc_gpio.h | 5 +++++ 3 files changed, 26 insertions(+), 15 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 62ee4d5..2ccb445 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -86,8 +86,8 @@ struct esdramc_regs {

/* GPIO registers */ struct gpio_regs { - u32 dr; /* data */ - u32 dir; /* direction */ + u32 gpio_dr; /* data */ + u32 gpio_dir; /* direction */ u32 psr; /* pad satus */ u32 icr1; /* interrupt config 1 */ u32 icr2; /* interrupt config 2 */ @@ -357,4 +357,10 @@ struct aips_regs { #define WSR_UNLOCK1 0x5555 #define WSR_UNLOCK2 0xAAAA

+/* Names used in GPIO driver */ +#define GPIO1_BASE_ADDR IMX_GPIO1_BASE +#define GPIO2_BASE_ADDR IMX_GPIO2_BASE +#define GPIO3_BASE_ADDR IMX_GPIO3_BASE +#define GPIO4_BASE_ADDR IMX_GPIO4_BASE + #endif /* _IMX_REGS_H */ diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 269858c..4088374 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -70,18 +70,18 @@ void tx25_fec_init(void) writel(0x0, &padctl->pad_d11);

/* drop PHY power and assert reset (low) */ - val = readl(&gpio4->dr) & ~((1 << 7) | (1 << 9)); - writel(val, &gpio4->dr); - val = readl(&gpio4->dir) | (1 << 7) | (1 << 9); - writel(val, &gpio4->dir); + val = readl(&gpio4->gpio_dr) & ~((1 << 7) | (1 << 9)); + writel(val, &gpio4->gpio_dr); + val = readl(&gpio4->gpio_dir) | (1 << 7) | (1 << 9); + writel(val, &gpio4->gpio_dir);

mdelay(5);

debug("resetting phy\n");

/* turn on PHY power leaving reset asserted */ - val = readl(&gpio4->dr) | 1 << 9; - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 9; + writel(val, &gpio4->gpio_dr);

mdelay(10);

@@ -111,19 +111,19 @@ void tx25_fec_init(void) /* * set each to 1 and make each an output */ - val = readl(&gpio3->dr) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dr); - val = readl(&gpio3->dir) | (1 << 10) | (1 << 11) | (1 << 12); - writel(val, &gpio3->dir); + val = readl(&gpio3->gpio_dr) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dr); + val = readl(&gpio3->gpio_dir) | (1 << 10) | (1 << 11) | (1 << 12); + writel(val, &gpio3->gpio_dir);

mdelay(22); /* this value came from RedBoot */

/* * deassert PHY reset */ - val = readl(&gpio4->dr) | 1 << 7; - writel(val, &gpio4->dr); - writel(val, &gpio4->dr); + val = readl(&gpio4->gpio_dr) | 1 << 7; + writel(val, &gpio4->gpio_dr); + writel(val, &gpio4->gpio_dr);

mdelay(5);

diff --git a/include/mxc_gpio.h b/include/mxc_gpio.h index 002ba61..f673dce 100644 --- a/include/mxc_gpio.h +++ b/include/mxc_gpio.h @@ -24,6 +24,11 @@ #ifndef __MXC_GPIO_H #define __MXC_GPIO_H

+/* Converts a GPIO port number and the internal bit position + * to the GPIO number + */ +#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f)) + enum mxc_gpio_direction { MXC_GPIO_DIRECTION_IN, MXC_GPIO_DIRECTION_OUT,

zmx25 is a board based on imx25 SoC, 64 Megs of LPDDR, 32 Megs of NOR flash, an optional NAND flash.

Signed-off-by: Matthias Weisser weisserm@arcor.de --- Changes in v2: - Using mxc_gpio now - Factored out asm macros

MAINTAINERS | 1 + arch/arm/include/asm/arch-mx25/macro.h | 64 ++++++++++ board/syteco/zmx25/Makefile | 51 ++++++++ board/syteco/zmx25/lowlevel_init.S | 110 +++++++++++++++++ board/syteco/zmx25/zmx25.c | 203 ++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/zmx25.h | 180 ++++++++++++++++++++++++++++ 7 files changed, 610 insertions(+), 0 deletions(-) create mode 100644 arch/arm/include/asm/arch-mx25/macro.h create mode 100644 board/syteco/zmx25/Makefile create mode 100644 board/syteco/zmx25/lowlevel_init.S create mode 100644 board/syteco/zmx25/zmx25.c create mode 100644 include/configs/zmx25.h

diff --git a/MAINTAINERS b/MAINTAINERS index 2bba7b4..5b633af 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -892,6 +892,7 @@ Lei Wen leiwen@marvell.com Matthias Weisser weisserm@arcor.de

jadecpu ARM926EJS (MB86R01 SoC) + zmx25 ARM926EJS (imx25 SoC)

Richard Woodruff r-woodruff2@ti.com

diff --git a/arch/arm/include/asm/arch-mx25/macro.h b/arch/arm/include/asm/arch-mx25/macro.h new file mode 100644 index 0000000..276c71c --- /dev/null +++ b/arch/arm/include/asm/arch-mx25/macro.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser weisserm@arcor.de + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * + * Common asm macros for imx25 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARM_ARCH_MACRO_H__ +#define __ASM_ARM_ARCH_MACRO_H__ +#ifdef __ASSEMBLY__ + +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +.macro init_aips + write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777 + write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777 +.endm + +.macro init_max + write32 IMX_MAX_BASE + MAX_MPR0, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR1, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR2, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR3, 0x43210 + write32 IMX_MAX_BASE + MAX_MPR4, 0x43210 + + write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10 + write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10 + + write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0 + write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0 +.endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARM_ARCH_MACRO_H__ */ diff --git a/board/syteco/zmx25/Makefile b/board/syteco/zmx25/Makefile new file mode 100644 index 0000000..5a0e5b3 --- /dev/null +++ b/board/syteco/zmx25/Makefile @@ -0,0 +1,51 @@ +# +# (c) 2010 Graf-Syteco, Matthias Weisser +# weisserm@arcor.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += zmx25.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/syteco/zmx25/lowlevel_init.S b/board/syteco/zmx25/lowlevel_init.S new file mode 100644 index 0000000..8e63de0 --- /dev/null +++ b/board/syteco/zmx25/lowlevel_init.S @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2011 + * Matthias Weisser weisserm@arcor.de + * + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * + * Based on U-Boot and RedBoot sources for several different i.mx + * platforms. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/macro.h> +#include <asm/arch/macro.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/asm-offsets.h> + +/* + * clocks + */ +.macro init_clocks + + /* disable clock output */ + write32 IMX_CCM_BASE + CCM_MCR, 0x00000000 + write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000 + + /* + * enable all implemented clocks in all three + * clock control registers + */ + write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff + write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff + write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff + + /* Devide NAND clock by 32 */ + write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F +.endm + +/* + * sdram controller init + */ +.macro init_lpddr + ldr r0, =IMX_ESDRAMC_BASE + ldr r2, =IMX_SDRAM_BANK0_BASE + + /* + * reset SDRAM controller + * then wait for initialization to complete + */ + ldr r1, =(1 << 1) | (1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] +1: ldr r3, [r0, #ESDRAMC_ESDMISC] + tst r3, #(1 << 31) + beq 1b + ldr r1, =(1 << 2) + str r1, [r0, #ESDRAMC_ESDMISC] + + ldr r1, =0x002a7420 + str r1, [r0, #ESDRAMC_ESDCFG0] + + /* control | precharge */ + ldr r1, =0x92216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* dram command encoded in address */ + str r1, [r2, #0x400] + + /* auto refresh */ + ldr r1, =0xa2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + /* read dram twice to auto refresh */ + ldr r3, [r2] + ldr r3, [r2] + + /* control | load mode */ + ldr r1, =0xb2216008 + str r1, [r0, #ESDRAMC_ESDCTL0] + + /* mode register of lpddram */ + strb r1, [r2, #0x33] + + /* extended mode register of lpddrram */ + ldr r2, =0x81000000 + strb r1, [r2] + + /* control | normal */ + ldr r1, =0x82216008 + str r1, [r0, #ESDRAMC_ESDCTL0] +.endm + +.globl lowlevel_init +lowlevel_init: + init_aips + init_max + init_clocks + init_lpddr + mov pc, lr diff --git a/board/syteco/zmx25/zmx25.c b/board/syteco/zmx25/zmx25.c new file mode 100644 index 0000000..f055038 --- /dev/null +++ b/board/syteco/zmx25/zmx25.c @@ -0,0 +1,203 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * weisserm@arcor.de + * + * Based on tx25.c: + * (C) Copyright 2009 DENX Software Engineering + * Author: John Rigby jrigby@gmail.com + * + * Based on imx27lite.c: + * Copyright (C) 2008,2009 Eric Jarrige jorasse@users.sourceforge.net + * Copyright (C) 2009 Ilya Yanok yanok@emcraft.com + * And: + * RedBoot tx25_misc.c Copyright (C) 2009 Red Hat + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ +#include <common.h> +#include <mxc_gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/imx25-pinmux.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init() +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + struct iomuxc_pad_input_select *inputselect; + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + u32 gpio_mux_mode1 = MX25_PIN_MUX_MODE(1); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode6 = MX25_PIN_MUX_MODE(6); + u32 input_select1 = MX25_PAD_INPUT_SELECT_DAISY(1); + u32 input_select2 = MX25_PAD_INPUT_SELECT_DAISY(2); + + icache_enable(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + inputselect = (struct iomuxc_pad_input_select *)IMX_IOPADINPUTSEL_BASE; + + /* Setup of core volatage selection pin to run at 1.4V */ + writel(gpio_mux_mode5, &muxctl->pad_ext_armclk); /* VCORE GPIO3[15] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 15), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 15), 1); + + /* Setup of input daisy chains for SD card pins*/ + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_cmd); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data0); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data1); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data2); + writel(gpio_mux_mode0_sion, &muxctl->pad_sd1_data3); + + /* Setup of digital output for USB power and OC */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d3); /* USB Power GPIO1[28] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 28), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 28), 1); + + writel(gpio_mux_mode5, &muxctl->pad_csi_d2); /* USB OC GPIO1[27] */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 18), MXC_GPIO_DIRECTION_IN); + + /* Setup of digital output control pins */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d8); /* Ouput 1 Ctrl GPIO1[7] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d7); /* Ouput 2 Ctrl GPIO1[6] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d6); /* Ouput 1 Stat GPIO1[31]*/ + writel(gpio_mux_mode5, &muxctl->pad_csi_d5); /* Ouput 2 Stat GPIO1[30]*/ + + writel(0, &padctl->pad_csi_d6); /* Ouput 1 Stat pull up off */ + writel(0, &padctl->pad_csi_d5); /* Ouput 2 Stat pull up off */ + + /* Switch both output drivers off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 7), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 7), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 6), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 6), MXC_GPIO_DIRECTION_OUT); + + /* Setup of key input pin GPIO2[29]*/ + writel(gpio_mux_mode5 | MX25_PIN_MUX_SION, &muxctl->pad_kpp_row0); + writel(0, &padctl->pad_kpp_row0); /* Key pull up off */ + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(2, 29), MXC_GPIO_DIRECTION_IN); + + /* Setup of status LED outputs */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d9); /* GPIO4[21] */ + writel(gpio_mux_mode5, &muxctl->pad_csi_d4); /* GPIO1[29] */ + + /* Switch both LEDs off */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(4, 21), MXC_GPIO_DIRECTION_OUT); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(1, 29), MXC_GPIO_DIRECTION_OUT); + + /* Setup of CAN1 and CAN2 signals */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_a); /* CAN1 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_b); /* CAN1 RX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_c); /* CAN2 TX */ + writel(gpio_mux_mode6, &muxctl->pad_gpio_d); /* CAN2 RX */ + + /* Setup of input daisy chains for CAN signals*/ + writel(input_select1, &inputselect->can1_ipp_ind_canrx); /* CAN1 RX */ + writel(input_select1, &inputselect->can2_ipp_ind_canrx); /* CAN2 RX */ + + /* Setup of I2C3 signals */ + writel(gpio_mux_mode1, &muxctl->pad_cspi1_ss1); /* I2C3 SDA */ + writel(gpio_mux_mode1, &muxctl->pad_gpio_e); /* I2C3 SCL */ + + /* Setup of input daisy chains for I2C3 signals*/ + writel(input_select1, &inputselect->i2c3_ipp_sda_in); /* I2C3 SDA */ + writel(input_select2, &inputselect->i2c3_ipp_scl_in); /* I2C3 SCL */ + + /* board id for linux */ + gd->bd->bi_arch_number = MACH_TYPE_ZMX25; + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int board_late_init(void) +{ + const char *e; + +#ifdef CONFIG_FEC_MXC + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode2 = MX25_PIN_MUX_MODE(2); + u32 gpio_mux_mode5 = MX25_PIN_MUX_MODE(5); + + /* + * fec pin init is generic + */ + mx25_fec_init_pins(); + + /* + * Set up LAN-RESET and FEC_RX_ERR + * + * LAN-RESET: GPIO3[16] is ALT 5 mode of pin U20 + * FEC_RX_ERR: FEC_RX_ERR is ALT 2 mode of pin R2 + */ + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + + writel(gpio_mux_mode5, &muxctl->pad_upll_bypclk); + writel(gpio_mux_mode2, &muxctl->pad_uart2_cts); + + /* assert PHY reset (low) */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 0); + mxc_gpio_direction(MXC_GPIO_PORT_TO_NUM(3, 16), MXC_GPIO_DIRECTION_OUT); + + udelay(5000); + + /* deassert PHY reset */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(3, 16), 1); + + udelay(5000); +#endif + + e = getenv("gs_base_board"); + if (e != NULL) { + if (strcmp(e, "G283") == 0) { + int key = mxc_gpio_get(MXC_GPIO_PORT_TO_NUM(2, 29)); + + if (key) { + /* Switch on both LEDs to inidcate boot mode */ + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(1, 29), 0); + mxc_gpio_set(MXC_GPIO_PORT_TO_NUM(4, 21), 0); + + setenv("preboot", "run gs_slow_boot"); + } else + setenv("preboot", "run gs_fast_boot"); + } + } + + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = gd->ram_size; +} diff --git a/boards.cfg b/boards.cfg index dfefc3f..5af3b88 100644 --- a/boards.cfg +++ b/boards.cfg @@ -127,6 +127,7 @@ rd6281a arm arm926ejs - Marvell sheevaplug arm arm926ejs - Marvell kirkwood dockstar arm arm926ejs - Seagate kirkwood jadecpu arm arm926ejs jadecpu syteco mb86r0x +zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 nhk8815 arm arm926ejs nhk8815 st nomadik diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h new file mode 100644 index 0000000..374c88a --- /dev/null +++ b/include/configs/zmx25.h @@ -0,0 +1,180 @@ +/* + * (c) 2011 Graf-Syteco, Matthias Weisser + * weisserm@arcor.de + * + * Configuation settings for the zmx25 board + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_MX25 +#define CONFIG_MX25_CLK32 32768 /* OSC32K frequency */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_TEXT_BASE 0xA0000000 + +/* + * Environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "gs_fast_boot=setenv bootdelay 5\0" \ + "gs_slow_boot=setenv bootdelay 10\0" \ + "bootcmd=dcache off; mw.l 0x81000000 0 1024; usb start;" \ + "fatls usb 0; fatload usb 0 0x81000000 zmx25-init.bin;" \ + "bootm 0x81000000; bootelf 0x81000000\0" + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define BOARD_LATE_INIT + +/* + * Compressions + */ +#define CONFIG_LZO + +/* + * Hardware drivers + */ + +/* + * GPIO + */ +#define CONFIG_MXC_GPIO + +/* + * Serial + */ +#define CONFIG_MXC_UART +#define CONFIG_SYS_MX25_UART2 +#define CONFIG_CONS_INDEX 1 /* use UART2 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Ethernet + */ +#define CONFIG_FEC_MXC +#define CONFIG_FEC_MXC_PHYADDR 0x00 +#define CONFIG_MII +#define CONFIG_NET_MULTI + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> +#define CONFIG_CMD_NET +#define CONFIG_CMD_CACHE + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* + * Additional command + */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_USB + +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* + * USB + */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MXC +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_MXC_USB_PORT 2 +#define CONFIG_MXC_USB_PORTSC 0xC0000000 +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION +#define CONFIG_SUPPORT_VFAT +#endif /* CONFIG_CMD_USB */ + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM 0x80000000 /* start address of LPDDRRAM */ +#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x78020000 /* end of internal SRAM */ + +/* + * FLASH and environment organization + */ +#define CONFIG_SYS_FLASH_BASE 0xA0000000 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_MAX_FLASH_SECT 256 + +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (128 * 1024) + +/* + * CFI FLASH driver setup + */ +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* ~10x faster */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + +#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) +#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) + +#define CONFIG_SYS_PROMPT "zmx25> " +#define CONFIG_SYS_CBSIZE 256 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_LONGHELP +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_PREBOOT "" + +#define CONFIG_BOOTDELAY 5 +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" +#define CONFIG_AUTOBOOT_STOP_STR "stopgs" + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (0x400000 - 0x8000) +#define CONFIG_STACKSIZE (32*1024) /* regular stack */ + +#endif /* __CONFIG_H */