We can built 'make sh7785lcr_32bit_config'. And add new command "pmb" for this mode. This command changes PMB for using 512MB system memory.

Signed-off-by: Yoshihiro Shimoda shimoda.yoshihiro@renesas.com --- Makefile | 15 +++- board/renesas/sh7785lcr/config.mk | 4 + board/renesas/sh7785lcr/lowlevel_init.S | 94 ++++++++++++++++++++ board/renesas/sh7785lcr/sh7785lcr.c | 32 +++++++ board/renesas/sh7785lcr/u-boot.lds | 4 +- .../renesas/sh7785lcr/{u-boot.lds => u-boot_29bit} | 0 .../renesas/sh7785lcr/{u-boot.lds => u-boot_32bit} | 4 +- include/configs/sh7785lcr.h | 21 ++++- 8 files changed, 168 insertions(+), 6 deletions(-) copy board/renesas/sh7785lcr/{u-boot.lds => u-boot_29bit} (100%) copy board/renesas/sh7785lcr/{u-boot.lds => u-boot_32bit} (93%)

diff --git a/Makefile b/Makefile index 3d0b986..e1ec906 100644 --- a/Makefile +++ b/Makefile @@ -3394,10 +3394,23 @@ sh7763rdp_config : unconfig @echo "#define CONFIG_SH7763RDP 1" > $(obj)include/config.h @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7763rdp renesas

+xtract_sh7785lcr = $(subst _32bit,,$(subst _config,,$1)) +sh7785lcr_32bit_config \ sh7785lcr_config : unconfig @ >include/config.h @echo "#define CONFIG_SH7785LCR 1" >> include/config.h - @$(MKCONFIG) -a $(@:_config=) sh sh4 sh7785lcr renesas + @if [ "$(findstring 32bit, $@)" ] ; then \ + echo "#define CONFIG_SH_32BIT 1" >> $(obj)include/config.h ; \ + cp $(obj)board/renesas/sh7785lcr/u-boot_32bit \ + $(obj)board/renesas/sh7785lcr/u-boot.lds ; \ + echo "TEXT_BASE = 0x8ff80000" > \ + $(obj)board/renesas/sh7785lcr/config.tmp ; \ + $(XECHO) " ... enable 32-Bit Address Extended Mode" ; \ + else \ + cp $(obj)board/renesas/sh7785lcr/u-boot_29bit \ + $(obj)board/renesas/sh7785lcr/u-boot.lds ; \ + fi + @$(MKCONFIG) -a $(call xtract_sh7785lcr,$@) sh sh4 sh7785lcr renesas

ap325rxa_config : unconfig @mkdir -p $(obj)include diff --git a/board/renesas/sh7785lcr/config.mk b/board/renesas/sh7785lcr/config.mk index 20807df..66d35cb 100644 --- a/board/renesas/sh7785lcr/config.mk +++ b/board/renesas/sh7785lcr/config.mk @@ -22,4 +22,8 @@ # # NOTE: Must match value used in u-boot.lds (in this directory). # +sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp + +ifndef TEXT_BASE TEXT_BASE = 0x0ff80000 +endif diff --git a/board/renesas/sh7785lcr/lowlevel_init.S b/board/renesas/sh7785lcr/lowlevel_init.S index f5ebeb9..97920df 100644 --- a/board/renesas/sh7785lcr/lowlevel_init.S +++ b/board/renesas/sh7785lcr/lowlevel_init.S @@ -130,6 +130,46 @@ lbsc_29bit: write32 CS6WCR_A, CS_SD_WCR_D

lbsc_end: +#if defined(CONFIG_SH_32BIT) + /*------- set PMB -------*/ + write32 PASCR_A, PASCR_29BIT_D + write32 MMUCR_A, MMUCR_D + + /***************************************************************** + * ent virt phys v sz c wt + * 0 0xa0000000 0x00000000 1 64M 0 0 + * 1 0xa4000000 0x04000000 1 16M 0 0 + * 2 0xa6000000 0x08000000 1 16M 0 0 + * 9 0x88000000 0x48000000 1 128M 1 1 + * 10 0x90000000 0x50000000 1 128M 1 1 + * 11 0x98000000 0x58000000 1 128M 1 1 + * 13 0xa8000000 0x48000000 1 128M 0 0 + * 14 0xb0000000 0x50000000 1 128M 0 0 + * 15 0xb8000000 0x58000000 1 128M 0 0 + */ + write32 PMB_ADDR_FLASH_A, PMB_ADDR_FLASH_D + write32 PMB_DATA_FLASH_A, PMB_DATA_FLASH_D + write32 PMB_ADDR_CPLD_A, PMB_ADDR_CPLD_D + write32 PMB_DATA_CPLD_A, PMB_DATA_CPLD_D + write32 PMB_ADDR_USB_A, PMB_ADDR_USB_D + write32 PMB_DATA_USB_A, PMB_DATA_USB_D + write32 PMB_ADDR_DDR_C1_A, PMB_ADDR_DDR_C1_D + write32 PMB_DATA_DDR_C1_A, PMB_DATA_DDR_C1_D + write32 PMB_ADDR_DDR_C2_A, PMB_ADDR_DDR_C2_D + write32 PMB_DATA_DDR_C2_A, PMB_DATA_DDR_C2_D + write32 PMB_ADDR_DDR_C3_A, PMB_ADDR_DDR_C3_D + write32 PMB_DATA_DDR_C3_A, PMB_DATA_DDR_C3_D + write32 PMB_ADDR_DDR_N1_A, PMB_ADDR_DDR_N1_D + write32 PMB_DATA_DDR_N1_A, PMB_DATA_DDR_N1_D + write32 PMB_ADDR_DDR_N2_A, PMB_ADDR_DDR_N2_D + write32 PMB_DATA_DDR_N2_A, PMB_DATA_DDR_N2_D + write32 PMB_ADDR_DDR_N3_A, PMB_ADDR_DDR_N3_D + write32 PMB_DATA_DDR_N3_A, PMB_DATA_DDR_N3_D + + write32 PASCR_A, PASCR_INIT + mov.l DUMMY_ADDR, r0 + icbi @r0 +#endif

write32 CCR_A, CCR_D

@@ -140,7 +180,11 @@ lbsc_end:

/*------- LBSC -------*/ MMSELR_A: .long 0xfc400020 +#if defined(CONFIG_SH_32BIT) +MMSELR_D: .long 0xa5a50005 +#else MMSELR_D: .long 0xa5a50002 +#endif

/*------- DBSC2 -------*/ #define DBSC2_BASE 0xfe800000 @@ -287,5 +331,55 @@ CS_SD_WCR_D: .long 0x00030108 CS_I2C_BCR_D: .long 0x11111100 CS_I2C_WCR_D: .long 0x00000003

+#if defined(CONFIG_SH_32BIT) +/*------- set PMB -------*/ +PMB_ADDR_FLASH_A: .long PMB_ADDR_BASE(0) +PMB_ADDR_CPLD_A: .long PMB_ADDR_BASE(1) +PMB_ADDR_USB_A: .long PMB_ADDR_BASE(2) +PMB_ADDR_DDR_C1_A: .long PMB_ADDR_BASE(9) +PMB_ADDR_DDR_C2_A: .long PMB_ADDR_BASE(10) +PMB_ADDR_DDR_C3_A: .long PMB_ADDR_BASE(11) +PMB_ADDR_DDR_N1_A: .long PMB_ADDR_BASE(13) +PMB_ADDR_DDR_N2_A: .long PMB_ADDR_BASE(14) +PMB_ADDR_DDR_N3_A: .long PMB_ADDR_BASE(15) + +PMB_ADDR_FLASH_D: .long mk_pmb_addr_val(0xa0) +PMB_ADDR_CPLD_D: .long mk_pmb_addr_val(0xa4) +PMB_ADDR_USB_D: .long mk_pmb_addr_val(0xa6) +PMB_ADDR_DDR_C1_D: .long mk_pmb_addr_val(0x88) +PMB_ADDR_DDR_C2_D: .long mk_pmb_addr_val(0x90) +PMB_ADDR_DDR_C3_D: .long mk_pmb_addr_val(0x98) +PMB_ADDR_DDR_N1_D: .long mk_pmb_addr_val(0xa8) +PMB_ADDR_DDR_N2_D: .long mk_pmb_addr_val(0xb0) +PMB_ADDR_DDR_N3_D: .long mk_pmb_addr_val(0xb8) + +PMB_DATA_FLASH_A: .long PMB_DATA_BASE(0) +PMB_DATA_CPLD_A: .long PMB_DATA_BASE(1) +PMB_DATA_USB_A: .long PMB_DATA_BASE(2) +PMB_DATA_DDR_C1_A: .long PMB_DATA_BASE(9) +PMB_DATA_DDR_C2_A: .long PMB_DATA_BASE(10) +PMB_DATA_DDR_C3_A: .long PMB_DATA_BASE(11) +PMB_DATA_DDR_N1_A: .long PMB_DATA_BASE(13) +PMB_DATA_DDR_N2_A: .long PMB_DATA_BASE(14) +PMB_DATA_DDR_N3_A: .long PMB_DATA_BASE(15) + +/* ppn ub v s1 s0 c wt */ +PMB_DATA_FLASH_D: .long mk_pmb_data_val(0x00, 1, 1, 0, 1, 0, 1) +PMB_DATA_CPLD_D: .long mk_pmb_data_val(0x04, 1, 1, 0, 0, 0, 1) +PMB_DATA_USB_D: .long mk_pmb_data_val(0x08, 1, 1, 0, 0, 0, 1) +PMB_DATA_DDR_C1_D: .long mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C2_D: .long mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_C3_D: .long mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1) +PMB_DATA_DDR_N1_D: .long mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N2_D: .long mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1) +PMB_DATA_DDR_N3_D: .long mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1) + +DUMMY_ADDR: .long 0xa0000000 +PASCR_29BIT_D: .long 0x00000000 +PASCR_INIT: .long 0x80000080 /* check booting mode */ +MMUCR_A: .long 0xff000010 +MMUCR_D: .long 0x00000004 /* clear ITLB */ +#endif /* CONFIG_SH_32BIT */ + CCR_A: .long 0xff00001c CCR_D: .long 0x0000090b diff --git a/board/renesas/sh7785lcr/sh7785lcr.c b/board/renesas/sh7785lcr/sh7785lcr.c index 786c758..1d81688 100644 --- a/board/renesas/sh7785lcr/sh7785lcr.c +++ b/board/renesas/sh7785lcr/sh7785lcr.c @@ -54,3 +54,35 @@ int board_eth_init(bd_t *bis) { return pci_eth_init(bis); } + +#if defined(CONFIG_SH_32BIT) +int do_pmb(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + /* clear ITLB */ + writel(0x00000004, 0xff000010); + + /* delete PMB for peripheral */ + writel(0, PMB_ADDR_BASE(0)); + writel(0, PMB_DATA_BASE(0)); + writel(0, PMB_ADDR_BASE(1)); + writel(0, PMB_DATA_BASE(1)); + writel(0, PMB_ADDR_BASE(2)); + writel(0, PMB_DATA_BASE(2)); + + /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */ + writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(8)); + writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(8)); + writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(12)); + writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(12)); + + return 0; +} + +U_BOOT_CMD( + pmb, 1, 1, do_pmb, + "pmb - PMB setting\n", + "\n" + " - PMB setting for all SDRAM mapping\n" +); +#endif + diff --git a/board/renesas/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot.lds index 231769f..446fb93 100644 --- a/board/renesas/sh7785lcr/u-boot.lds +++ b/board/renesas/sh7785lcr/u-boot.lds @@ -1,7 +1,7 @@ /* * Copyrigth (c) 2007 * Nobuhiro Iwamatsu iwamatsu@nigauri.org - * Copyrigth (c) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com + * Copyrigth (c) 2008-2009 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com * * See file CREDITS for list of people who contributed to this * project. @@ -28,7 +28,7 @@ ENTRY(_start)

SECTIONS { - . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024); + . = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);

PROVIDE (reloc_dst = .);

diff --git a/board/renesas/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot_29bit similarity index 100% copy from board/renesas/sh7785lcr/u-boot.lds copy to board/renesas/sh7785lcr/u-boot_29bit diff --git a/board/renesas/sh7785lcr/u-boot.lds b/board/renesas/sh7785lcr/u-boot_32bit similarity index 93% copy from board/renesas/sh7785lcr/u-boot.lds copy to board/renesas/sh7785lcr/u-boot_32bit index 231769f..446fb93 100644 --- a/board/renesas/sh7785lcr/u-boot.lds +++ b/board/renesas/sh7785lcr/u-boot_32bit @@ -1,7 +1,7 @@ /* * Copyrigth (c) 2007 * Nobuhiro Iwamatsu iwamatsu@nigauri.org - * Copyrigth (c) 2008 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com + * Copyrigth (c) 2008-2009 Yoshihiro Shimoda shimoda.yoshihiro@renesas.com * * See file CREDITS for list of people who contributed to this * project. @@ -28,7 +28,7 @@ ENTRY(_start)

SECTIONS { - . = 0x08000000 + (128 * 1024 * 1024) - (512 * 1024); + . = 0x88000000 + (128 * 1024 * 1024) - (512 * 1024);

PROVIDE (reloc_dst = .);

diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index 94c8d6b..21c3f70 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -61,11 +61,20 @@ #undef CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */ +#if defined(CONFIG_SH_32BIT) +#define SH7785LCR_SDRAM_PHYS_BASE (0x48000000) +#define SH7785LCR_SDRAM_BASE (0x88000000) +#define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) +#define SH7785LCR_FLASH_BASE_1 (0xa0000000) +#define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) +#define SH7785LCR_USB_BASE (0xa6000000) +#else #define SH7785LCR_SDRAM_BASE (0x08000000) #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) #define SH7785LCR_FLASH_BASE_1 (0xa0000000) #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) #define SH7785LCR_USB_BASE (0xb4000000) +#endif

#define CONFIG_SYS_LONGHELP #define CONFIG_SYS_PROMPT "=> " @@ -133,9 +142,15 @@ #define CONFIG_PCI #define CONFIG_SH4_PCI #define CONFIG_SH7780_PCI +#if defined(CONFIG_SH_32BIT) +#define CONFIG_SH7780_PCI_LSR 0x1ff00001 +#define CONFIG_SH7780_PCI_LAR 0x5f000000 +#define CONFIG_SH7780_PCI_BAR 0x5f000000 +#else #define CONFIG_SH7780_PCI_LSR 0x07f00001 #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE +#endif #define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW 1

@@ -147,8 +162,12 @@ #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */

-#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE +#if defined(CONFIG_SH_32BIT) +#define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE +#else #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE +#endif +#define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE

/* Network device (RTL8169) support */