[U-Boot] Multiple chip support in ndfc driver
Hi,
On a custom 460EX board I have a 2Gbyte NAND device, 1Gbyte per chip select. I'm trying to enable support for the second NAND CS, so far without success.
U-Boot properly detects both devices, (manufacturer, size, bus width). First device works as expected, on second device bad blocks are reported correctly, but attempt to erase the device results in I/O errors on every block. The bank settings are identical for both chips.
What am I missing ?
BTW, I was wandering why NAND TLB window size on Canyonlands is 16Mbytes. Also, why NAND start address for TLB mapping is calculated as CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS
Thanks in advance.
Felix.
Hi Felix,
On Sunday 05 December 2010 15:27:02 Felix Radensky wrote:
On a custom 460EX board I have a 2Gbyte NAND device, 1Gbyte per chip select. I'm trying to enable support for the second NAND CS, so far without success.
U-Boot properly detects both devices, (manufacturer, size, bus width). First device works as expected, on second device bad blocks are reported correctly, but attempt to erase the device results in I/O errors on every block. The bank settings are identical for both chips.
What am I missing ?
Perhaps a misconfiguration in your board config header? How did you configure the NAND driver? Take a look at DU440.h or bamboo.h for example. Those boards use multiple NAND devices.
BTW, I was wandering why NAND TLB window size on Canyonlands is 16Mbytes.
Yes. This TLB could be smaller. 1KiB should be enough. Patch welcome. ;)
Also, why NAND start address for TLB mapping is calculated as CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS
This is because of the NAND booting config option. NOR booting Canyonlands has NAND conntected to chip-select 3 and NAND booting has it connected to chip- select 0. And the lower 2 bits (value 0...3) of CONFIG_SYS_NAND_BASE are used to configure the chip-select the NAND device is connected to (see ndfc.c for more details).
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Hi Stefan,
Thanks for a prompt reply.
Stefan Roese wrote:
Hi Felix,
On Sunday 05 December 2010 15:27:02 Felix Radensky wrote:
On a custom 460EX board I have a 2Gbyte NAND device, 1Gbyte per chip select. I'm trying to enable support for the second NAND CS, so far without success.
U-Boot properly detects both devices, (manufacturer, size, bus width). First device works as expected, on second device bad blocks are reported correctly, but attempt to erase the device results in I/O errors on every block. The bank settings are identical for both chips.
What am I missing ?
Perhaps a misconfiguration in your board config header? How did you configure the NAND driver? Take a look at DU440.h or bamboo.h for example. Those boards use multiple NAND devices.
Thanks for the hint. I've looked at these boards, and I cannot see what's wrong with my configuration. Since second chip is properly detected, I think configuration is correct. Read also works, only erase and program fail. Looks like a hardware problem to me.
BTW, I was wandering why NAND TLB window size on Canyonlands is 16Mbytes.
Yes. This TLB could be smaller. 1KiB should be enough. Patch welcome. ;)
OK, I'll send the patch.
Felix.
participants (2)
-
Felix Radensky -
Stefan Roese