[U-Boot] [PATCH V2 0/5] ARM: OMAP5: Add support for OMAP543x ES2.0 Socs

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[U-Boot] [PATCH v3 1/4] nand: mxc:...

R Sricharan

4 Feb 2013 4 Feb '13

3:29 p.m.

ES2.0 is the latest silicon revision for OMAP543X socs. The SOC supports enhanced opps for MPU (up to 1.5GHz). This series essentially adds the support for both 5430 and 5432 versions.

This is on top of the below U-Boot cleanup series. http://comments.gmane.org/gmane.comp.boot-loaders.u-boot/152834

Lokesh Vutla (2): ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup

R Sricharan (3): ARM: OMAP5: Add silicon id support for ES2.0 revision. ARM: OMAP5: clock: Add the prcm register changes required for ES2.0 ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 ++++++------ arch/arm/cpu/armv7/omap5/hw_data.c | 261 ++++++++++++++------- arch/arm/cpu/armv7/omap5/hwinit.c | 129 ++++++++++- arch/arm/cpu/armv7/omap5/prcm-regs.c | 286 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/sdram.c | 75 ++++++- arch/arm/include/asm/arch-omap5/clocks.h | 8 + arch/arm/include/asm/arch-omap5/omap.h | 27 +++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/emif.h | 1 + arch/arm/include/asm/omap_common.h | 14 +- 13 files changed, 794 insertions(+), 161 deletions(-)

-- 1.7.9.5

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R Sricharan

4 Feb 4 Feb

3:29 p.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..0d8c95d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -216,8 +216,17 @@ void init_omap_revision(void) break; } break; - default: - *omap_si_rev = OMAP5430_SILICON_ID_INVALID; + case MIDR_CORTEX_A15_R2P2: + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5430_ES2_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES2_0: + *omap_si_rev = OMAP5432_ES2_0; + break; + default: + *omap_si_rev = OMAP5430_SILICON_ID_INVALID; + } } }

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 873ccd7..71935d8 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -57,7 +57,9 @@

/* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F

/* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index ad9a875..a73630b 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -33,6 +33,7 @@

/* Cortex-A15 revisions */ #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2 0x412FC0F2

/* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2115687..4599167 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -542,4 +542,6 @@ static inline u32 omap_revision(void) #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 #define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200 #endif /* _OMAP_COMMON_H_ */

-- 1.7.9.5

Tom Rini

4:43 p.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

On Mon, Feb 04, 2013 at 07:59:20PM +0530, R Sricharan wrote:

...

Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com

[snip]

...

/* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F

[snip]

...

+#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200

These all have whitespace problems, but git am --whitespace=fix will fix them.

Reviewed-by: Tom Rini trini@ti.com

-- Tom

Nishanth Menon

8:41 p.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

On 19:59-20130204, R Sricharan wrote:

...

Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..0d8c95d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -216,8 +216,17 @@ void init_omap_revision(void) break; } break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
case MIDR_CORTEX_A15_R2P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5430_ES2_0;
	break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5432_ES2_0;
	break;
default:
	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}

A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse ID fused in, why would we want to make it a standard to check ARM revision *and then* cross verify against control fuse verification, *and then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks entirely.

...

} }

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 873ccd7..71935d8 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -57,7 +57,9 @@

/* To be verified */ #define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES2_0 0x1B94202F #define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F +#define OMAP5432_CONTROL_ID_CODE_ES2_0 0x1B99802F

/* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index ad9a875..a73630b 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -33,6 +33,7 @@

/* Cortex-A15 revisions */ #define MIDR_CORTEX_A15_R0P0 0x410FC0F0 +#define MIDR_CORTEX_A15_R2P2 0x412FC0F2

/* CCSIDR */ #define CCSIDR_LINE_SIZE_OFFSET 0 diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 2115687..4599167 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -542,4 +542,6 @@ static inline u32 omap_revision(void) #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 #define OMAP5432_ES1_0 0x54320100 +#define OMAP5430_ES2_0 0x54300200 +#define OMAP5432_ES2_0 0x54320200

#endif /* _OMAP_COMMON_H_ */

1.7.9.5

U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

-- Regards, Nishanth Menon

R Sricharan

5 Feb 5 Feb

1:32 p.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:

...

On 19:59-20130204, R Sricharan wrote:

...
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..0d8c95d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -216,8 +216,17 @@ void init_omap_revision(void) break; } break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
case MIDR_CORTEX_A15_R2P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5430_ES2_0;
	break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5432_ES2_0;
	break;
default:
	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse ID fused in, why would we want to make it a standard to check ARMsilicon revision *and then* cross verify against control fuse verification, *and then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks entirely.

In the same context, for some boards in past even in the actual samples the CONTROL ID code was reading the older revision. So in those cases ARM revision will help to differentiate them.

But then it should have been in the opposite way, like reading the CONTROL_CODE first and then reading the ARM revision if required in those cases where is it broken. I will change this logic here.

Regards, Sricharan

Nishanth Menon

4:19 p.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

On 18:02-20130205, R Sricharan wrote:

...

On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:

...
On 19:59-20130204, R Sricharan wrote:

...
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..0d8c95d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -216,8 +216,17 @@ void init_omap_revision(void) break; } break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
case MIDR_CORTEX_A15_R2P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5430_ES2_0;
	break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5432_ES2_0;
	break;
default:
	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse ID fused in, why would we want to make it a standard to check ARMsilicon revision *and then* cross verify against control fuse verification, *and then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks entirely.
In the same context, for some boards in past even in the actual samples the CONTROL ID code was reading the older revision. So in those cases ARM revision will help to differentiate them.

which boards? Almost as a rule the first few samples on almost all revisions on production floor had messed up control ID, however, beyond that, all runs are properly updated.

...

But then it should have been in the opposite way, like reading the CONTROL_CODE first and then reading the ARM revision if required in those cases where is it broken. I will change this logic here.

Having cortex check is just redundant - IMHO, switching it over might be better, but dropping it is more inline with expectation of the silicon spec.

-- Regards, Nishanth Menon

R Sricharan

6 Feb 6 Feb

7:10 a.m.

New subject: [U-Boot] [PATCH V2 1/5] ARM: OMAP5: Add silicon id support for ES2.0 revision.

Hi, On Tuesday 05 February 2013 08:49 PM, Nishanth Menon wrote:

...

On 18:02-20130205, R Sricharan wrote:

...
On Tuesday 05 February 2013 01:11 AM, Nishanth Menon wrote:

...
On 19:59-20130204, R Sricharan wrote:

...
Adding the CPU detection suport for OMAP5430 and OMAP5432 ES2.0 SOCs.

Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap5/hwinit.c | 13 +++++++++++-- arch/arm/include/asm/arch-omap5/omap.h | 2 ++ arch/arm/include/asm/armv7.h | 1 + arch/arm/include/asm/omap_common.h | 2 ++ 4 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index dfc0e44..0d8c95d 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -216,8 +216,17 @@ void init_omap_revision(void) break; } break;
default:
*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
case MIDR_CORTEX_A15_R2P2:
switch (readl(CONTROL_ID_CODE)) {
case OMAP5430_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5430_ES2_0;
	break;
case OMAP5432_CONTROL_ID_CODE_ES2_0:
	*omap_si_rev = OMAP5432_ES2_0;
	break;
default:
	*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
}
A first few samples of both ES1.0 and ES2.0 (in the few 10s of samples) came with wrong efuse ID fused in, why would we want to make it a standard to check ARMsilicon revision *and then* cross verify against control fuse verification, *and then* give up saying we dont support it?

Looks like an over check for me -> IMHO, we should drop the MIDR checks entirely.
In the same context, for some boards in past even in the actual samples the CONTROL ID code was reading the older revision. So in those cases ARM revision will help to differentiate them.
which boards? Almost as a rule the first few samples on almost all revisions on production floor had messed up control ID, however, beyond that, all runs are properly updated.

...

I have seen this issue on some OMAP4 revisions as well. It was only after that we introduced this logic of double checking using ARM revision ID.

...

...
But then it should have been in the opposite way, like reading the CONTROL_CODE first and then reading the ARM revision if required in those cases where is it broken. I will change this logic here.

Having cortex check is just redundant - IMHO, switching it over might be better, but dropping it is more inline with expectation of the silicon spec.

According to me the best way to do it is, use CONTROL_ID first and then use ARM revision for those which has wrong IDs. This will always be a fool proof even for those non-working boards.

Regards, Sricharan

R Sricharan

4 Feb 4 Feb

3:29 p.m.

New subject: [U-Boot] [PATCH V2 2/5] ARM: OMAP5: clock: Add the prcm register changes required for ES2.0

PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 5 + arch/arm/cpu/armv7/omap5/prcm-regs.c | 283 ++++++++++++++++++++++++++++++++++ arch/arm/include/asm/omap_common.h | 4 + 3 files changed, 292 insertions(+)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 6b039f5..e319dc5 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -451,6 +451,11 @@ void hw_data_init(void) *omap_vcores = &omap5432_volts; break;

+ case OMAP5430_ES2_0: + case OMAP5432_ES2_0: + *prcm = &omap5_es2_prcm; + break; + default: printf("\n INVALID OMAP REVISION "); } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 0f58b2f..58c9d50 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -378,3 +378,286 @@ struct omap_sys_ctrl_regs const omap5_ctrl = { .control_efuse_12 = 0x4AE0CDF4, .control_efuse_13 = 0x4AE0CDF8, }; + +struct prcm_regs const omap5_es2_prcm = { + /* cm1.ckgen */ + .cm_clksel_core = 0x4a004100, + .cm_clksel_abe = 0x4a004108, + .cm_dll_ctrl = 0x4a004110, + .cm_clkmode_dpll_core = 0x4a004120, + .cm_idlest_dpll_core = 0x4a004124, + .cm_autoidle_dpll_core = 0x4a004128, + .cm_clksel_dpll_core = 0x4a00412c, + .cm_div_m2_dpll_core = 0x4a004130, + .cm_div_m3_dpll_core = 0x4a004134, + .cm_div_h11_dpll_core = 0x4a004138, + .cm_div_h12_dpll_core = 0x4a00413c, + .cm_div_h13_dpll_core = 0x4a004140, + .cm_div_h14_dpll_core = 0x4a004144, + .cm_ssc_deltamstep_dpll_core = 0x4a004148, + .cm_ssc_modfreqdiv_dpll_core = 0x4a00414c, + .cm_div_h21_dpll_core = 0x4a004150, + .cm_div_h22_dpllcore = 0x4a004154, + .cm_div_h23_dpll_core = 0x4a004158, + .cm_div_h24_dpll_core = 0x4a00415c, + .cm_clkmode_dpll_mpu = 0x4a004160, + .cm_idlest_dpll_mpu = 0x4a004164, + .cm_autoidle_dpll_mpu = 0x4a004168, + .cm_clksel_dpll_mpu = 0x4a00416c, + .cm_div_m2_dpll_mpu = 0x4a004170, + .cm_ssc_deltamstep_dpll_mpu = 0x4a004188, + .cm_ssc_modfreqdiv_dpll_mpu = 0x4a00418c, + .cm_bypclk_dpll_mpu = 0x4a00419c, + .cm_clkmode_dpll_iva = 0x4a0041a0, + .cm_idlest_dpll_iva = 0x4a0041a4, + .cm_autoidle_dpll_iva = 0x4a0041a8, + .cm_clksel_dpll_iva = 0x4a0041ac, + .cm_div_h11_dpll_iva = 0x4a0041b8, + .cm_div_h12_dpll_iva = 0x4a0041bc, + .cm_ssc_deltamstep_dpll_iva = 0x4a0041c8, + .cm_ssc_modfreqdiv_dpll_iva = 0x4a0041cc, + .cm_bypclk_dpll_iva = 0x4a0041dc, + .cm_clkmode_dpll_abe = 0x4a0041e0, + .cm_idlest_dpll_abe = 0x4a0041e4, + .cm_autoidle_dpll_abe = 0x4a0041e8, + .cm_clksel_dpll_abe = 0x4a0041ec, + .cm_div_m2_dpll_abe = 0x4a0041f0, + .cm_div_m3_dpll_abe = 0x4a0041f4, + .cm_ssc_deltamstep_dpll_abe = 0x4a004208, + .cm_ssc_modfreqdiv_dpll_abe = 0x4a00420c, + .cm_clkmode_dpll_ddrphy = 0x4a004220, + .cm_idlest_dpll_ddrphy = 0x4a004224, + .cm_autoidle_dpll_ddrphy = 0x4a004228, + .cm_clksel_dpll_ddrphy = 0x4a00422c, + .cm_div_m2_dpll_ddrphy = 0x4a004230, + .cm_div_h11_dpll_ddrphy = 0x4a004238, + .cm_div_h12_dpll_ddrphy = 0x4a00423c, + .cm_div_h13_dpll_ddrphy = 0x4a004240, + .cm_ssc_deltamstep_dpll_ddrphy = 0x4a004248, + .cm_shadow_freq_config1 = 0x4a004260, + .cm_mpu_mpu_clkctrl = 0x4a004320, + + /* cm1.dsp */ + .cm_dsp_clkstctrl = 0x4a004400, + .cm_dsp_dsp_clkctrl = 0x4a004420, + + /* cm1.abe */ + .cm1_abe_clkstctrl = 0x4a004500, + .cm1_abe_l4abe_clkctrl = 0x4a004520, + .cm1_abe_aess_clkctrl = 0x4a004528, + .cm1_abe_pdm_clkctrl = 0x4a004530, + .cm1_abe_dmic_clkctrl = 0x4a004538, + .cm1_abe_mcasp_clkctrl = 0x4a004540, + .cm1_abe_mcbsp1_clkctrl = 0x4a004548, + .cm1_abe_mcbsp2_clkctrl = 0x4a004550, + .cm1_abe_mcbsp3_clkctrl = 0x4a004558, + .cm1_abe_slimbus_clkctrl = 0x4a004560, + .cm1_abe_timer5_clkctrl = 0x4a004568, + .cm1_abe_timer6_clkctrl = 0x4a004570, + .cm1_abe_timer7_clkctrl = 0x4a004578, + .cm1_abe_timer8_clkctrl = 0x4a004580, + .cm1_abe_wdt3_clkctrl = 0x4a004588, + + + + /* cm2.ckgen */ + .cm_clksel_mpu_m3_iss_root = 0x4a008100, + .cm_clksel_usb_60mhz = 0x4a008104, + .cm_scale_fclk = 0x4a008108, + .cm_core_dvfs_perf1 = 0x4a008110, + .cm_core_dvfs_perf2 = 0x4a008114, + .cm_core_dvfs_perf3 = 0x4a008118, + .cm_core_dvfs_perf4 = 0x4a00811c, + .cm_core_dvfs_current = 0x4a008124, + .cm_iva_dvfs_perf_tesla = 0x4a008128, + .cm_iva_dvfs_perf_ivahd = 0x4a00812c, + .cm_iva_dvfs_perf_abe = 0x4a008130, + .cm_iva_dvfs_current = 0x4a008138, + .cm_clkmode_dpll_per = 0x4a008140, + .cm_idlest_dpll_per = 0x4a008144, + .cm_autoidle_dpll_per = 0x4a008148, + .cm_clksel_dpll_per = 0x4a00814c, + .cm_div_m2_dpll_per = 0x4a008150, + .cm_div_m3_dpll_per = 0x4a008154, + .cm_div_h11_dpll_per = 0x4a008158, + .cm_div_h12_dpll_per = 0x4a00815c, + .cm_div_h13_dpll_per = 0x4a008160, + .cm_div_h14_dpll_per = 0x4a008164, + .cm_ssc_deltamstep_dpll_per = 0x4a008168, + .cm_ssc_modfreqdiv_dpll_per = 0x4a00816c, + .cm_emu_override_dpll_per = 0x4a008170, + .cm_clkmode_dpll_usb = 0x4a008180, + .cm_idlest_dpll_usb = 0x4a008184, + .cm_autoidle_dpll_usb = 0x4a008188, + .cm_clksel_dpll_usb = 0x4a00818c, + .cm_div_m2_dpll_usb = 0x4a008190, + .cm_ssc_deltamstep_dpll_usb = 0x4a0081a8, + .cm_ssc_modfreqdiv_dpll_usb = 0x4a0081ac, + .cm_clkdcoldo_dpll_usb = 0x4a0081b4, + .cm_clkmode_dpll_unipro = 0x4a0081c0, + .cm_idlest_dpll_unipro = 0x4a0081c4, + .cm_autoidle_dpll_unipro = 0x4a0081c8, + .cm_clksel_dpll_unipro = 0x4a0081cc, + .cm_div_m2_dpll_unipro = 0x4a0081d0, + .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, + .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, + .cm_coreaon_bandgap_clkctrl = 0x4a008648, + + + /* cm2.core */ + .cm_l3_1_clkstctrl = 0x4a008700, + .cm_l3_1_dynamicdep = 0x4a008708, + .cm_l3_1_l3_1_clkctrl = 0x4a008720, + .cm_l3_2_clkstctrl = 0x4a008800, + .cm_l3_2_dynamicdep = 0x4a008808, + .cm_l3_2_l3_2_clkctrl = 0x4a008820, + .cm_l3_2_gpmc_clkctrl = 0x4a008828, + .cm_l3_2_ocmc_ram_clkctrl = 0x4a008830, + .cm_mpu_m3_clkstctrl = 0x4a008900, + .cm_mpu_m3_staticdep = 0x4a008904, + .cm_mpu_m3_dynamicdep = 0x4a008908, + .cm_mpu_m3_mpu_m3_clkctrl = 0x4a008920, + .cm_sdma_clkstctrl = 0x4a008a00, + .cm_sdma_staticdep = 0x4a008a04, + .cm_sdma_dynamicdep = 0x4a008a08, + .cm_sdma_sdma_clkctrl = 0x4a008a20, + .cm_memif_clkstctrl = 0x4a008b00, + .cm_memif_dmm_clkctrl = 0x4a008b20, + .cm_memif_emif_fw_clkctrl = 0x4a008b28, + .cm_memif_emif_1_clkctrl = 0x4a008b30, + .cm_memif_emif_2_clkctrl = 0x4a008b38, + .cm_memif_dll_clkctrl = 0x4a008b40, + .cm_memif_emif_h1_clkctrl = 0x4a008b50, + .cm_memif_emif_h2_clkctrl = 0x4a008b58, + .cm_memif_dll_h_clkctrl = 0x4a008b60, + .cm_c2c_clkstctrl = 0x4a008c00, + .cm_c2c_staticdep = 0x4a008c04, + .cm_c2c_dynamicdep = 0x4a008c08, + .cm_c2c_sad2d_clkctrl = 0x4a008c20, + .cm_c2c_modem_icr_clkctrl = 0x4a008c28, + .cm_c2c_sad2d_fw_clkctrl = 0x4a008c30, + .cm_l4cfg_clkstctrl = 0x4a008d00, + .cm_l4cfg_dynamicdep = 0x4a008d08, + .cm_l4cfg_l4_cfg_clkctrl = 0x4a008d20, + .cm_l4cfg_hw_sem_clkctrl = 0x4a008d28, + .cm_l4cfg_mailbox_clkctrl = 0x4a008d30, + .cm_l4cfg_sar_rom_clkctrl = 0x4a008d38, + .cm_l3instr_clkstctrl = 0x4a008e00, + .cm_l3instr_l3_3_clkctrl = 0x4a008e20, + .cm_l3instr_l3_instr_clkctrl = 0x4a008e28, + .cm_l3instr_intrconn_wp1_clkctrl = 0x4a008e40, + .cm_l4per_clkstctrl = 0x4a009000, + .cm_l4per_dynamicdep = 0x4a009008, + .cm_l4per_adc_clkctrl = 0x4a009020, + .cm_l4per_gptimer10_clkctrl = 0x4a009028, + .cm_l4per_gptimer11_clkctrl = 0x4a009030, + .cm_l4per_gptimer2_clkctrl = 0x4a009038, + .cm_l4per_gptimer3_clkctrl = 0x4a009040, + .cm_l4per_gptimer4_clkctrl = 0x4a009048, + .cm_l4per_gptimer9_clkctrl = 0x4a009050, + .cm_l4per_elm_clkctrl = 0x4a009058, + .cm_l4per_gpio2_clkctrl = 0x4a009060, + .cm_l4per_gpio3_clkctrl = 0x4a009068, + .cm_l4per_gpio4_clkctrl = 0x4a009070, + .cm_l4per_gpio5_clkctrl = 0x4a009078, + .cm_l4per_gpio6_clkctrl = 0x4a009080, + .cm_l4per_hdq1w_clkctrl = 0x4a009088, + .cm_l4per_hecc1_clkctrl = 0x4a009090, + .cm_l4per_hecc2_clkctrl = 0x4a009098, + .cm_l4per_i2c1_clkctrl = 0x4a0090a0, + .cm_l4per_i2c2_clkctrl = 0x4a0090a8, + .cm_l4per_i2c3_clkctrl = 0x4a0090b0, + .cm_l4per_i2c4_clkctrl = 0x4a0090b8, + .cm_l4per_l4per_clkctrl = 0x4a0090c0, + .cm_l4per_mcasp2_clkctrl = 0x4a0090d0, + .cm_l4per_mcasp3_clkctrl = 0x4a0090d8, + .cm_l4per_mgate_clkctrl = 0x4a0090e8, + .cm_l4per_mcspi1_clkctrl = 0x4a0090f0, + .cm_l4per_mcspi2_clkctrl = 0x4a0090f8, + .cm_l4per_mcspi3_clkctrl = 0x4a009100, + .cm_l4per_mcspi4_clkctrl = 0x4a009108, + .cm_l4per_gpio7_clkctrl = 0x4a009110, + .cm_l4per_gpio8_clkctrl = 0x4a009118, + .cm_l4per_mmcsd3_clkctrl = 0x4a009120, + .cm_l4per_mmcsd4_clkctrl = 0x4a009128, + .cm_l4per_msprohg_clkctrl = 0x4a009130, + .cm_l4per_slimbus2_clkctrl = 0x4a009138, + .cm_l4per_uart1_clkctrl = 0x4a009140, + .cm_l4per_uart2_clkctrl = 0x4a009148, + .cm_l4per_uart3_clkctrl = 0x4a009150, + .cm_l4per_uart4_clkctrl = 0x4a009158, + .cm_l4per_mmcsd5_clkctrl = 0x4a009160, + .cm_l4per_i2c5_clkctrl = 0x4a009168, + .cm_l4per_uart5_clkctrl = 0x4a009170, + .cm_l4per_uart6_clkctrl = 0x4a009178, + .cm_l4sec_clkstctrl = 0x4a009180, + .cm_l4sec_staticdep = 0x4a009184, + .cm_l4sec_dynamicdep = 0x4a009188, + .cm_l4sec_aes1_clkctrl = 0x4a0091a0, + .cm_l4sec_aes2_clkctrl = 0x4a0091a8, + .cm_l4sec_des3des_clkctrl = 0x4a0091b0, + .cm_l4sec_pkaeip29_clkctrl = 0x4a0091b8, + .cm_l4sec_rng_clkctrl = 0x4a0091c0, + .cm_l4sec_sha2md51_clkctrl = 0x4a0091c8, + .cm_l4sec_cryptodma_clkctrl = 0x4a0091d8, + + /* cm2.ivahd */ + .cm_ivahd_clkstctrl = 0x4a009200, + .cm_ivahd_ivahd_clkctrl = 0x4a009220, + .cm_ivahd_sl2_clkctrl = 0x4a009228, + + /* cm2.cam */ + .cm_cam_clkstctrl = 0x4a009300, + .cm_cam_iss_clkctrl = 0x4a009320, + .cm_cam_fdif_clkctrl = 0x4a009328, + + /* cm2.dss */ + .cm_dss_clkstctrl = 0x4a009400, + .cm_dss_dss_clkctrl = 0x4a009420, + + /* cm2.sgx */ + .cm_sgx_clkstctrl = 0x4a009500, + .cm_sgx_sgx_clkctrl = 0x4a009520, + + /* cm2.l3init */ + .cm_l3init_clkstctrl = 0x4a009600, + + /* cm2.l3init */ + .cm_l3init_hsmmc1_clkctrl = 0x4a009628, + .cm_l3init_hsmmc2_clkctrl = 0x4a009630, + .cm_l3init_hsi_clkctrl = 0x4a009638, + .cm_l3init_hsusbhost_clkctrl = 0x4a009658, + .cm_l3init_hsusbotg_clkctrl = 0x4a009660, + .cm_l3init_hsusbtll_clkctrl = 0x4a009668, + .cm_l3init_p1500_clkctrl = 0x4a009678, + .cm_l3init_fsusb_clkctrl = 0x4a0096d0, + .cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0, + + /* l4 wkup regs */ + .cm_abe_pll_ref_clksel = 0x4ae0610c, + .cm_sys_clksel = 0x4ae06110, + .cm_wkup_clkstctrl = 0x4ae07900, + .cm_wkup_l4wkup_clkctrl = 0x4ae07920, + .cm_wkup_wdtimer1_clkctrl = 0x4ae07928, + .cm_wkup_wdtimer2_clkctrl = 0x4ae07930, + .cm_wkup_gpio1_clkctrl = 0x4ae07938, + .cm_wkup_gptimer1_clkctrl = 0x4ae07940, + .cm_wkup_gptimer12_clkctrl = 0x4ae07948, + .cm_wkup_synctimer_clkctrl = 0x4ae07950, + .cm_wkup_usim_clkctrl = 0x4ae07958, + .cm_wkup_sarram_clkctrl = 0x4ae07960, + .cm_wkup_keyboard_clkctrl = 0x4ae07978, + .cm_wkup_rtc_clkctrl = 0x4ae07980, + .cm_wkup_bandgap_clkctrl = 0x4ae07988, + .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .prm_vc_val_bypass = 0x4ae07ca0, + .prm_vc_cfg_i2c_mode = 0x4ae07cb4, + .prm_vc_cfg_i2c_clk = 0x4ae07cb8, + + .prm_sldo_core_setup = 0x4ae07cc4, + .prm_sldo_core_ctrl = 0x4ae07cc8, + .prm_sldo_mpu_setup = 0x4ae07ccc, + .prm_sldo_mpu_ctrl = 0x4ae07cd0, + .prm_sldo_mm_setup = 0x4ae07cd4, + .prm_sldo_mm_ctrl = 0x4ae07cd8, +}; diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 4599167..08395ca 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -44,6 +44,8 @@ struct prcm_regs { u32 cm_div_h12_dpll_core; u32 cm_div_h13_dpll_core; u32 cm_div_h14_dpll_core; + u32 cm_div_h21_dpll_core; + u32 cm_div_h24_dpll_core; u32 cm_ssc_deltamstep_dpll_core; u32 cm_ssc_modfreqdiv_dpll_core; u32 cm_emu_override_dpll_core; @@ -128,6 +130,7 @@ struct prcm_regs { u32 cm_div_m3_dpll_per; u32 cm_div_h11_dpll_per; u32 cm_div_h12_dpll_per; + u32 cm_div_h13_dpll_per; u32 cm_div_h14_dpll_per; u32 cm_ssc_deltamstep_dpll_per; u32 cm_ssc_modfreqdiv_dpll_per; @@ -474,6 +477,7 @@ struct vcores_data {

extern struct prcm_regs const **prcm; extern struct prcm_regs const omap5_es1_prcm; +extern struct prcm_regs const omap5_es2_prcm; extern struct prcm_regs const omap4_prcm; extern struct dplls const **dplls_data; extern struct vcores_data const **omap_vcores;

-- 1.7.9.5

Tom Rini

4:43 p.m.

New subject: [U-Boot] [PATCH V2 2/5] ARM: OMAP5: clock: Add the prcm register changes required for ES2.0

On Mon, Feb 04, 2013 at 07:59:21PM +0530, R Sricharan wrote:

...

PRCM register addresses are changed from ES1.0 to ES2.0 due to PER power domain getting moved to CORE power domain.

So adding the nessecary register changes for the same.

Signed-off-by: R Sricharan r.sricharan@ti.com

Reviewed-by: Tom Rini trini@ti.com

-- Tom

R Sricharan

3:29 p.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

Change OPP settings as per the latest 0.4 version of addendum for OMAP5430 ES2.0

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 +++++++------- arch/arm/cpu/armv7/omap5/hw_data.c | 242 +++++++++++++++--------- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/omap_common.h | 6 +- 5 files changed, 241 insertions(+), 157 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336..164253c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll); + if (params->h21 >= 0) + writel(params->h21, &dpll_regs->cm_div_h21_dpll); if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll); + if (params->h24 >= 0) + writel(params->h24, &dpll_regs->cm_div_h24_dpll); }

static inline void do_bypass_dpll(u32 const base) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 892d016..b01bf5d 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -51,113 +51,113 @@ struct omap_sys_ctrl_regs const **ctrl =

/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */ static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = { - {175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */ static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* dpll locked at 1200 MHz - MPU clk at 600 MHz */ static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = { - {50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = { - {200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = { - {127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = { - {200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */ - {800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */ - {619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */ - {125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */ - {800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */ - {125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */ + {200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */ + {800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */ + {619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */ + {800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */ + {125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = { - {64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */ - {768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */ - {320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */ - {40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */ - {384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */ - {256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */ - {20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */ + {64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */ + {768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */ + {320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */ + {40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */ + {384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */ + {256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */ + {20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = { - {931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */ - {931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */ - {665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */ - {727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */ - {931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */ - {931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */ - {291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */ + {931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = { - 750, 0, 1, 1, -1, -1, -1, -1, -1, -1 + 750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 };

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

struct dplls omap4430_dplls_es1 = { diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e319dc5..13ea07e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -44,134 +44,177 @@ struct omap_sys_ctrl_regs const **ctrl = (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;

static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = { - {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = { - {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = { - {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = { - {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = { - {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = { - {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {275, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {550, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = { - {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */ - {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */ - {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */ + {266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */ + {665, 11, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */ + {532, 12, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = { + {266, 2, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 16.8 MHz */ + {277, 4, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 19.2 MHz */ + {368, 8, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = { - {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */ - {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */ - {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */ + {266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {570, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */ + {665, 11, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */ + {532, 12, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {665, 23, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params + core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = { + {266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */ + {277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */ + {368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ };

static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = { - {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */ - {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */ - {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */ + {32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = { + {32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */ + {20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */ + {192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = { - {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */ - {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */ - {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */ + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ +}; + +static const struct dpll_params iva_dpll_params_2330mhz_es2[NUM_SYS_CLKS] = { + {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = { - {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = { - {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ - {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ - {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ - {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ - {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ - {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ + {400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */ + {400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */ + {400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */ + {480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */ + {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */ + {400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

+ struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -185,6 +228,19 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz };

+struct dplls omap5_dplls_es2 = { + .mpu = mpu_dpll_params_1100mhz, + .core = core_dpll_params_2128mhz_ddr532_es2, + .per = per_dpll_params_768mhz_es2, + .iva = iva_dpll_params_2330mhz_es2, +#ifdef CONFIG_SYS_OMAP_ABE_SYSCK + .abe = abe_dpll_params_sysclk_196608khz, +#else + .abe = &abe_dpll_params_32k_196608khz, +#endif + .usb = usb_dpll_params_1920mhz +}; + struct pmic_data palmas = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */ @@ -223,6 +279,20 @@ struct vcores_data omap5432_volts = { .mm.pmic = &palmas, };

+struct vcores_data omap5430_volts_es2 = { + .mpu.value = VDD_MPU_ES2, + .mpu.addr = SMPS_REG_ADDR_12_MPU, + .mpu.pmic = &palmas, + + .core.value = VDD_CORE_ES2, + .core.addr = SMPS_REG_ADDR_8_CORE, + .core.pmic = &palmas, + + .mm.value = VDD_MM_ES2, + .mm.addr = SMPS_REG_ADDR_45_IVA, + .mm.pmic = &palmas, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -454,6 +524,8 @@ void hw_data_init(void) case OMAP5430_ES2_0: case OMAP5432_ES2_0: *prcm = &omap5_es2_prcm; + *dplls_data = &omap5_dplls_es2; + *omap_vcores = &omap5430_volts_es2; break;

default: diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..685aad5 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -208,6 +208,10 @@ #define VDD_MM_5432 1150 #define VDD_CORE_5432 1150

+#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040 + /* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 08395ca..8a886ec 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -426,8 +426,10 @@ struct dpll_params { s8 m5_h12; s8 m6_h13; s8 m7_h14; + s8 h21; s8 h22; s8 h23; + s8 h24; };

struct dpll_regs { @@ -441,9 +443,11 @@ struct dpll_regs { u32 cm_div_m5_h12_dpll; u32 cm_div_m6_h13_dpll; u32 cm_div_m7_h14_dpll; - u32 reserved[3]; + u32 reserved[2]; + u32 cm_div_h21_dpll; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll; + u32 cm_div_h24_dpll; };

struct dplls {

-- 1.7.9.5

Tom Rini

4:44 p.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

On Mon, Feb 04, 2013 at 07:59:22PM +0530, R Sricharan wrote:

...

Change OPP settings as per the latest 0.4 version of addendum for OMAP5430 ES2.0

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com

Reviewed-by: Tom Rini trini@ti.com

-- Tom

Nishanth Menon

9:16 p.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

On 19:59-20130204, R Sricharan wrote:

...

Change OPP settings as per the latest 0.4 version of addendum for OMAP5430 ES2.0

-->please be clear that these are for OPP_NOM. FYI, latest documentation is 0.5 rev which was released in Jan, considering this patch was send in Feb, might be good to cross verify any updates.

in addition, I suspect TRM was referred for certain DPLLs as well?

...

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 +++++++------- arch/arm/cpu/armv7/omap5/hw_data.c | 242 +++++++++++++++--------- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/omap_common.h | 6 +- 5 files changed, 241 insertions(+), 157 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336..164253c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
if (params->h21 >= 0)
writel(params->h21, &dpll_regs->cm_div_h21_dpll);
if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll);
if (params->h24 >= 0)
writel(params->h24, &dpll_regs->cm_div_h24_dpll);
}

static inline void do_bypass_dpll(u32 const base) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 892d016..b01bf5d 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -51,113 +51,113 @@ struct omap_sys_ctrl_regs const **ctrl =

/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */

this: equivalent to OPP_SB?

...

static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */

Do we even support this? there is no OPP Turbo for OMAP5, we have OPP_HIGH which needs DCC and AVS etc..

...

static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* dpll locked at 1200 MHz - MPU clk at 600 MHz */

Please correct this.

...

static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

Follow on question: if we are dropping ES1.0 support entirely - we should drop it's support in id detection as well! ES1.0 and ES2.0 DPLL configurations are different unfortunately.

...

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {

OPP_LOW is not supported on OMAP5 es2.0? Supported core DPLL locked frequency is 2127.36MHz?

...

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {

dumb question: what is running at 1600MHz?

...

{200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {

not sure about these frequencies if verified for ES2.0

...

{64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */

{768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */

{320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */

{40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */

{384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */

{256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */

{20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */

{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */

{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */

{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */

{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */

{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {

I might be mistaken, but i think the frequencies need an update?

...

{931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */

{931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */

{665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */

{727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */

{931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */

{931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */

{291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */

{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

We do not intend to support 32K ABE source except when doing DPLL cascading - so this is in effect an configuration which is un-used in any s/w line.

...

750, 0, 1, 1, -1, -1, -1, -1, -1, -1

750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1

};

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

struct dplls omap4430_dplls_es1 = { diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e319dc5..13ea07e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -44,134 +44,177 @@ struct omap_sys_ctrl_regs const **ctrl = (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;

static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {

I am not sure we'd like to do this.

...

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

...

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

...

{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

...

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

...

{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {

{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{275, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {

{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */

{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */

{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */

{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */

{665, 11, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */

{532, 12, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */

+};

+static const struct dpll_params
	core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{443, 6, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 16.8 MHz */

{277, 4, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 19.2 MHz */

{368, 8, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{277, 9, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6} /* 38.4 MHz */
};

static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {

{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */

{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */

{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */

{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */

{665, 11, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */

{532, 12, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */

+};

+static const struct dpll_params
	core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */

{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */

{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */
};

static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {

{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */

{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */

+};

+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {

{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */

{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */

{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

+};

+static const struct dpll_params iva_dpll_params_2330mhz_es2[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

750, 0, 1, 1, -1, -1, -1, -1, -1, -1

750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1

};

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

spurious EOL

...

struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -185,6 +228,19 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz };

+struct dplls omap5_dplls_es2 = {

.mpu = mpu_dpll_params_1100mhz,

.core = core_dpll_params_2128mhz_ddr532_es2,

.per = per_dpll_params_768mhz_es2,

.iva = iva_dpll_params_2330mhz_es2,

+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK

.abe = abe_dpll_params_sysclk_196608khz,

+#else

.abe = &abe_dpll_params_32k_196608khz,

+#endif

I strongly suggest dumping ABE sourcing from 32K clock - the code is just a nuisance waiting to exercise an unsupported silicon feature waiting to happen.

...

.usb = usb_dpll_params_1920mhz

+};

struct pmic_data palmas = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */ @@ -223,6 +279,20 @@ struct vcores_data omap5432_volts = { .mm.pmic = &palmas, };

+struct vcores_data omap5430_volts_es2 = {

.mpu.value = VDD_MPU_ES2,

.mpu.addr = SMPS_REG_ADDR_12_MPU,

.mpu.pmic = &palmas,

.core.value = VDD_CORE_ES2,

.core.addr = SMPS_REG_ADDR_8_CORE,

.core.pmic = &palmas,

.mm.value = VDD_MM_ES2,

.mm.addr = SMPS_REG_ADDR_45_IVA,

.mm.pmic = &palmas,

+};

/*

Enable essential clock domains, modules and

do some additional special settings needed

@@ -454,6 +524,8 @@ void hw_data_init(void) case OMAP5430_ES2_0: case OMAP5432_ES2_0: *prcm = &omap5_es2_prcm;

*dplls_data = &omap5_dplls_es2;

*omap_vcores = &omap5430_volts_es2; break;

default:

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..685aad5 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -208,6 +208,10 @@ #define VDD_MM_5432 1150 #define VDD_CORE_5432 1150

+#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040

^^^ these are meant only for OPP_NOM - considering that you have DPLLs for OPP_SB added in, do you even expect these devices to bootup at anything *but* OPP_NOM??

...

/* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 08395ca..8a886ec 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -426,8 +426,10 @@ struct dpll_params { s8 m5_h12; s8 m6_h13; s8 m7_h14;

s8 h21; s8 h22; s8 h23;

s8 h24;

};

struct dpll_regs { @@ -441,9 +443,11 @@ struct dpll_regs { u32 cm_div_m5_h12_dpll; u32 cm_div_m6_h13_dpll; u32 cm_div_m7_h14_dpll;

u32 reserved[3];

u32 reserved[2];

u32 cm_div_h21_dpll; u32 cm_div_h22_dpll; u32 cm_div_h23_dpll;

u32 cm_div_h24_dpll;

};

struct dplls {

Sadly Naked-by: Nishanth Menon nm@ti.com

-- Regards, Nishanth Menon

R Sricharan

5 Feb 5 Feb

1:02 p.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

Hi Nishanth,

On Tuesday 05 February 2013 01:46 AM, Nishanth Menon wrote:

...

On 19:59-20130204, R Sricharan wrote:

...
Change OPP settings as per the latest 0.4 version of addendum for OMAP5430 ES2.0

-->please be clear that these are for OPP_NOM. FYI, latest documentation is 0.5 rev which was released in Jan, considering this patch was send in Feb, might be good to cross verify any updates.

Thanks for the info, i was not aware of 0.5 version. I will recheck if something is different here.

...

in addition, I suspect TRM was referred for certain DPLLs as well?

...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 +++++++------- arch/arm/cpu/armv7/omap5/hw_data.c | 242 +++++++++++++++--------- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/omap_common.h | 6 +- 5 files changed, 241 insertions(+), 157 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336..164253c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
if (params->h21 >= 0)
writel(params->h21, &dpll_regs->cm_div_h21_dpll);
if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll);
if (params->h24 >= 0)
writel(params->h24, &dpll_regs->cm_div_h24_dpll);
}

static inline void do_bypass_dpll(u32 const base)
diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 892d016..b01bf5d 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -51,113 +51,113 @@ struct omap_sys_ctrl_regs const **ctrl =

/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
this: equivalent to OPP_SB?

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static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */

Do we even support this? there is no OPP Turbo for OMAP5, we have OPP_HIGH which needs DCC and AVS etc..

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static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* dpll locked at 1200 MHz - MPU clk at 600 MHz */

Please correct this.

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static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

Follow on question: if we are dropping ES1.0 support entirely - we should drop it's support in id detection as well! ES1.0 and ES2.0 DPLL configurations are different unfortunately.

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{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {

OPP_LOW is not supported on OMAP5 es2.0? Supported core DPLL locked frequency is 2127.36MHz?

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{200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

Answering all of your above questions here. The above data is for OMAP4 and not OMAP5. This file was modified here just to include dummy dividers. Because we were now using a common dpll_params structure, there was no functional change in this file. I think the problem was commit log was missing this info. I will update to clarify this.

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static const struct dpll_params core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {

dumb question: what is running at 1600MHz?

DPLL_CORE is locked at 1600 MHz in OMAP4

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{200, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{800, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{619, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{125, 2, 2, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{400, 12, 2, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{800, 26, 2, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{125, 5, 2, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{200, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 2, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {

not sure about these frequencies if verified for ES2.0

Again this is OMAP4 frequency

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{64, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 12 MHz */

{768, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 13 MHz */

{320, 6, 8, 6, 12, 9, 4, 5, -1, -1}, /* 16.8 MHz */

{40, 0, 8, 6, 12, 9, 4, 5, -1, -1}, /* 19.2 MHz */

{384, 12, 8, 6, 12, 9, 4, 5, -1, -1}, /* 26 MHz */

{256, 8, 8, 6, 12, 9, 4, 5, -1, -1}, /* 27 MHz */

{20, 0, 8, 6, 12, 9, 4, 5, -1, -1} /* 38.4 MHz */

{64, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 12 MHz */

{768, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 13 MHz */

{320, 6, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{40, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{384, 12, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 26 MHz */

{256, 8, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1}, /* 27 MHz */

{20, 0, 8, 6, 12, 9, 4, 5, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {

I might be mistaken, but i think the frequencies need an update?

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{931, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 12 MHz */

{931, 12, -1, -1, 4, 7, -1, -1, -1, -1}, /* 13 MHz */

{665, 11, -1, -1, 4, 7, -1, -1, -1, -1}, /* 16.8 MHz */

{727, 14, -1, -1, 4, 7, -1, -1, -1, -1}, /* 19.2 MHz */

{931, 25, -1, -1, 4, 7, -1, -1, -1, -1}, /* 26 MHz */

{931, 26, -1, -1, 4, 7, -1, -1, -1, -1}, /* 27 MHz */

{291, 11, -1, -1, 4, 7, -1, -1, -1, -1} /* 38.4 MHz */

{931, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{931, 12, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{665, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{727, 14, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{931, 25, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{931, 26, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{291, 11, -1, -1, 4, 7, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{68, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{29, 7, 1, 1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{49, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{68, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{29, 7, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

We do not intend to support 32K ABE source except when doing DPLL cascading - so this is in effect an configuration which is un-used in any s/w line.

1) In fact we not locking ABE, IVA, USB DPLLs any more in bootloader unless some one enable a CLOCKS_ENABLE_ALL config. But we still have there data, so that we can quickly experiment when needed.

2) I remember that locking with 32K source was considered better because, we can cut sys_clk when audio is still running. Also i think that the jitter was not a real problem for audio even when running with 32Khz clock. I have to check this point again.

The reason we had both the sources supported was just from an experiment motive. I have seen that during pre silicon, we have to switch the clock source from default to get locking. So having support for both helps in those cases.

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750, 0, 1, 1, -1, -1, -1, -1, -1, -1

750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 };

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{80, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{960, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{50, 0, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{320, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{25, 0, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{80, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{960, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{50, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{320, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{25, 0, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

struct dplls omap4430_dplls_es1 = {

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index e319dc5..13ea07e 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -44,134 +44,177 @@ struct omap_sys_ctrl_regs const **ctrl = (struct omap_sys_ctrl_regs const **)OMAP5_SRAM_SCRATCH_SYS_CTRL;

static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {

I am not sure we'd like to do this.

This file is common for ES1.0 as well. Also i have added frequency tables for OPP_HIGH and OPP_LOW as well. We some times find it nessecary to boot with a different than OPP_NOM to do experiments. So this is useful from that point. But what is missing is the VDDs which I usually add manually while testing. But now to complete this, i will add that as well.

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{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

This file is common for ES1.0 as well.

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{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

MPU runs at 1100 MHZ in OPP_NOM on 2.0

...

...

{275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{275, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

MPU runs at 800 MHZ in OPP_NOM on 1.0

...

...

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

MPU runs at 400 MHZ in OPP_LOW on 1.0

...

...
{200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1000, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{375, 8, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{375, 17, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {

{275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{275, 2, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{1375, 20, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1375, 23, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{550, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1375, 47, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {

{266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */

{665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */

{532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */

{266, 2, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 16.8 MHz */

{665, 11, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 19.2 MHz */

{532, 12, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 2, 5, 8, 4, 62, 5, -1, 5, 7, -1} /* 38.4 MHz */

+};

+static const struct dpll_params
	core_dpll_params_2128mhz_ddr532_es2[NUM_SYS_CLKS] = {
{266, 2, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{443, 6, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 16.8 MHz */

{277, 4, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 19.2 MHz */

{368, 8, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{277, 9, 2, 5, 8, 4, 62, 5, 6, 5, 7, 6} /* 38.4 MHz */ };

static const struct dpll_params core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
{266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */

{665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */

{532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */

{266, 2, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{570, 8, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 16.8 MHz */

{665, 11, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 19.2 MHz */

{532, 12, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{665, 23, 4, 8, 8, 8, 62, 10, -1, 10, 14, -1} /* 38.4 MHz */

+};

+static const struct dpll_params
	core_dpll_params_2128mhz_ddr266_es2[NUM_SYS_CLKS] = {
{266, 2, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{443, 6, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 16.8 MHz */

{277, 4, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 19.2 MHz */

{368, 8, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{277, 9, 4, 8, 8, 8, 62, 5, 12, 10, 14, 12} /* 38.4 MHz */ };

static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
{32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */

{32, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 6, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */

+};

+static const struct dpll_params per_dpll_params_768mhz_es2[NUM_SYS_CLKS] = {

{32, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{160, 6, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 16.8 MHz */

{20, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 19.2 MHz */

{192, 12, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{10, 0, 4, 3, 3, 4, -1, 2, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */

{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */

{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2011, 28, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{1881, 30, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1165, 25, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{1972, 64, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

+};

+static const struct dpll_params iva_dpll_params_2330mhz_es2[NUM_SYS_CLKS] = {

{1165, 11, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{208, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{182, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{224, 4, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{91, 2, -1, -1, 5, 6, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with sys_clk as source */ static const struct dpll_params abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {

{49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{49, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{35, 5, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{46, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{34, 8, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{64, 24, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

750, 0, 1, 1, -1, -1, -1, -1, -1, -1

750, 0, 1, 1, -1, -1, -1, -1, -1, -1, -1, -1 };

static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {

{400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{400, 4, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{400, 6, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{400, 7, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{480, 12, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{400, 15, 2, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };
spurious EOL

Ok, will correct this.

...

...
struct dplls omap5_dplls_es1 = { .mpu = mpu_dpll_params_800mhz, .core = core_dpll_params_2128mhz_ddr532, @@ -185,6 +228,19 @@ struct dplls omap5_dplls_es1 = { .usb = usb_dpll_params_1920mhz };

+struct dplls omap5_dplls_es2 = {

.mpu = mpu_dpll_params_1100mhz,

.core = core_dpll_params_2128mhz_ddr532_es2,

.per = per_dpll_params_768mhz_es2,

.iva = iva_dpll_params_2330mhz_es2,

+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK

.abe = abe_dpll_params_sysclk_196608khz,

+#else

.abe = &abe_dpll_params_32k_196608khz,

+#endif

I strongly suggest dumping ABE sourcing from 32K clock - the code is just a nuisance waiting to exercise an unsupported silicon feature waiting to happen.

...

...

.usb = usb_dpll_params_1920mhz

+};

struct pmic_data palmas = { .base_offset = PALMAS_SMPS_BASE_VOLT_UV, .step = 10000, /* 10 mV represented in uV */

@@ -223,6 +279,20 @@ struct vcores_data omap5432_volts = { .mm.pmic = &palmas, };

+struct vcores_data omap5430_volts_es2 = {

.mpu.value = VDD_MPU_ES2,

.mpu.addr = SMPS_REG_ADDR_12_MPU,

.mpu.pmic = &palmas,

.core.value = VDD_CORE_ES2,

.core.addr = SMPS_REG_ADDR_8_CORE,

.core.pmic = &palmas,

.mm.value = VDD_MM_ES2,

.mm.addr = SMPS_REG_ADDR_45_IVA,

.mm.pmic = &palmas,

+};

/*

Enable essential clock domains, modules and

do some additional special settings needed

@@ -454,6 +524,8 @@ void hw_data_init(void) case OMAP5430_ES2_0: case OMAP5432_ES2_0: *prcm = &omap5_es2_prcm;

*dplls_data = &omap5_dplls_es2;

*omap_vcores = &omap5430_volts_es2; break;

default:

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..685aad5 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -208,6 +208,10 @@ #define VDD_MM_5432 1150 #define VDD_CORE_5432 1150

+#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040

^^^ these are meant only for OPP_NOM - considering that you have DPLLs for OPP_SB added in, do you even expect these devices to bootup at anything *but* OPP_NOM??

I agree. I add it manually while doing experiments. I will add these here.

Regards, Sricharan

Nishanth Menon

4:29 p.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

On 17:32-20130205, R Sricharan wrote:

...

Hi Nishanth,

On Tuesday 05 February 2013 01:46 AM, Nishanth Menon wrote:

...
On 19:59-20130204, R Sricharan wrote:

...
Change OPP settings as per the latest 0.4 version of addendum for OMAP5430 ES2.0

-->please be clear that these are for OPP_NOM. FYI, latest documentation is 0.5 rev which was released in Jan, considering this patch was send in Feb, might be good to cross verify any updates.

Thanks for the info, i was not aware of 0.5 version. I will recheck if something is different here.

...
in addition, I suspect TRM was referred for certain DPLLs as well?

...
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com Signed-off-by: R Sricharan r.sricharan@ti.com

arch/arm/cpu/armv7/omap-common/clocks-common.c | 4 + arch/arm/cpu/armv7/omap4/hw_data.c | 142 +++++++------- arch/arm/cpu/armv7/omap5/hw_data.c | 242 +++++++++++++++--------- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/omap_common.h | 6 +- 5 files changed, 241 insertions(+), 157 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 88e5336..164253c 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -103,10 +103,14 @@ void setup_post_dividers(u32 const base, const struct dpll_params *params) writel(params->m6_h13, &dpll_regs->cm_div_m6_h13_dpll); if (params->m7_h14 >= 0) writel(params->m7_h14, &dpll_regs->cm_div_m7_h14_dpll);
if (params->h21 >= 0)
writel(params->h21, &dpll_regs->cm_div_h21_dpll);
if (params->h22 >= 0) writel(params->h22, &dpll_regs->cm_div_h22_dpll); if (params->h23 >= 0) writel(params->h23, &dpll_regs->cm_div_h23_dpll);
if (params->h24 >= 0)
writel(params->h24, &dpll_regs->cm_div_h24_dpll);
}

static inline void do_bypass_dpll(u32 const base) diff --git a/arch/arm/cpu/armv7/omap4/hw_data.c b/arch/arm/cpu/armv7/omap4/hw_data.c index 892d016..b01bf5d 100644 --- a/arch/arm/cpu/armv7/omap4/hw_data.c +++ b/arch/arm/cpu/armv7/omap4/hw_data.c @@ -51,113 +51,113 @@ struct omap_sys_ctrl_regs const **ctrl =

/* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
this: equivalent to OPP_SB?

...
static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{175, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{700, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{401, 10, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{350, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{700, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{638, 34, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */

Do we even support this? there is no OPP Turbo for OMAP5, we have OPP_HIGH which needs DCC and AVS etc..

...
static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{200, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

/* dpll locked at 1200 MHz - MPU clk at 600 MHz */

Please correct this.

...
static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

Follow on question: if we are dropping ES1.0 support entirely - we should drop it's support in id detection as well! ES1.0 and ES2.0 DPLL configurations are different unfortunately.
...
...

{50, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{600, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{250, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 3, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{300, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{200, 8, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{125, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {

OPP_LOW is not supported on OMAP5 es2.0? Supported core DPLL locked frequency is 2127.36MHz?

...

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{200, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{800, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{619, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{125, 2, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{400, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{800, 26, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{125, 5, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1} /* 38.4 MHz */

{127, 1, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 12 MHz */

{762, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 13 MHz */

{635, 13, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 16.8 MHz */

{635, 15, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 19.2 MHz */

{381, 12, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 26 MHz */

{254, 8, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1}, /* 27 MHz */

{496, 24, 1, 5, 8, 4, 6, 5, -1, -1, -1, -1} /* 38.4 MHz */

};

Answering all of your above questions here. The above data is for OMAP4 and not OMAP5. This file was modified here just to include dummy dividers. Because we were now using a common dpll_params structure, there was no functional change in this file. I think the problem was commit log was missing this info. I will update to clarify this.

I dont think updating commit log alone is the right solution -> renaming the variables make more sense - making ones meant for OMAP4 as _omap4430, 60 etc help readability of code. [...]

...

...
...
/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

We do not intend to support 32K ABE source except when doing DPLL cascading - so this is in effect an configuration which is un-used in any s/w line.

In fact we not locking ABE, IVA, USB DPLLs any more in bootloader unless some one enable a CLOCKS_ENABLE_ALL config. But we still have there data, so that we can quickly experiment when needed.

it is no longer supported on OMAP5. If you have doubts on the silicon usecase specification, I recommend you do read the TI internal documentation for the same.

...

I remember that locking with 32K source was considered better because, we can cut sys_clk when audio is still running. Also i think that the jitter was not a real problem for audio even when running with 32Khz clock. I have to check this point again.

please check again.

...

 The reason we had both the sources supported was just from an
 experiment motive. I have seen that during pre silicon, we have

As a rule, experimentation code should NOT be in mainline. only recommended operation code should ever be put in mainline - real products are supposed to ramp with this code.

...

 to switch the clock source from default to get locking. So having
 support for both helps in those cases.

not if the silicon is neither validated NOR expected to be supported at this. [...]

...

...
...
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {

I am not sure we'd like to do this.
This file is common for ES1.0 as well. Also i have added frequency
tables for OPP_HIGH and OPP_LOW as well. We some times find it
nessecary to boot with a different than OPP_NOM to do experiments.
So this is useful from that point.  But what is missing is the VDDs
which I usually add manually while testing. But now to complete
this, i will add that as well.

Why? Es1.0 will never be publically released, it never was meant to be public. ES2.0 is the only one meant to go out. Supporting ES1.0 and ES2.0 means a ton of redundant code being maintained in mainline with no product lines meant to actively using it - ever! Do we really want to do this??

...

...
...

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

This file is common for ES1.0 as well.

ES1.0 DOES NOT run at 2GHz!

...

...
...

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

};

static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?

MPU runs at 1100 MHZ in OPP_NOM on 2.0

1099MHz - I suggest latest spec to be clear on this - i suggest reviewing further based on update. [...]

...

...
...

.iva = iva_dpll_params_2330mhz_es2,

+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK

.abe = abe_dpll_params_sysclk_196608khz,

+#else

.abe = &abe_dpll_params_32k_196608khz,

+#endif

I strongly suggest dumping ABE sourcing from 32K clock - the code is just a nuisance waiting to exercise an unsupported silicon feature waiting to happen.

[...]

...

...
...
default: diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..685aad5 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -208,6 +208,10 @@ #define VDD_MM_5432 1150 #define VDD_CORE_5432 1150

+#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040

^^^ these are meant only for OPP_NOM - considering that you have DPLLs for OPP_SB added in, do you even expect these devices to bootup at anything *but* OPP_NOM??

I agree. I add it manually while doing experiments. I will add these here.

As a rule we want maintainable s/w in mainline, not experimental code. maintainable s/w implies s/w that adheres to SoC's specified operational ranges unfortunately :(.

-- Regards, Nishanth Menon

R Sricharan

6 Feb 6 Feb

8:12 a.m.

New subject: [U-Boot] [PATCH V2 3/5] ARM: OMAP5: clocks: Add OPP settings required for OMAP543X ES2.0 soc

On Tuesday 05 February 2013 08:59 PM, Nishanth Menon wrote: [..]

...

...
...
...
Answering all of your above questions here.
The above data is for OMAP4 and not OMAP5. This file was modified
here just to include dummy dividers. Because we were now using a
common dpll_params structure, there was no functional change in this
file. I think the problem was commit log was missing this info.
 I will update to clarify this.
I dont think updating commit log alone is the right solution -> renaming the variables make more sense - making ones meant for OMAP4 as _omap4430, 60 etc help readability of code.

omap4/hw_data.c has separate arrays to represent 4430, 4460 dplls data.

...

[...]

...
...
...
/* ABE M & N values with 32K clock as source */ static const struct dpll_params abe_dpll_params_32k_196608khz = {

We do not intend to support 32K ABE source except when doing DPLL cascading - so this is in effect an configuration which is un-used in any s/w line.

In fact we not locking ABE, IVA, USB DPLLs any more in bootloader unless some one enable a CLOCKS_ENABLE_ALL config. But we still have there data, so that we can quickly experiment when needed.

it is no longer supported on OMAP5. If you have doubts on the silicon usecase specification, I recommend you do read the TI internal documentation for the same.

...

I remember that locking with 32K source was considered better because, we can cut sys_clk when audio is still running. Also i think that the jitter was not a real problem for audio even when running with 32Khz clock. I have to check this point again.

please check again.

...

I even checked the latest version of ES2.0 TRM. M, N specified are 750, 0. So these are ones used to lock at 32KHZ.

...

...
  The reason we had both the sources supported was just from an
  experiment motive. I have seen that during pre silicon, we have
As a rule, experimentation code should NOT be in mainline. only recommended operation code should ever be put in mainline - real products are supposed to ramp with this code.

Yes, by default we have set it to OPP_NOM. There where many situations where there was a need to boot with higher OPPs for performance measurements with mainline. So it was better to change just one variable than to add the full data for that OPP in those cases. This has helped many times in the past.

...

...
  to switch the clock source from default to get locking. So having
  support for both helps in those cases.
not if the silicon is neither validated NOR expected to be supported at this. [...]

...
...
...
static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {

I am not sure we'd like to do this.
 This file is common for ES1.0 as well. Also i have added frequency
 tables for OPP_HIGH and OPP_LOW as well. We some times find it
 nessecary to boot with a different than OPP_NOM to do experiments.
 So this is useful from that point.  But what is missing is the VDDs
 which I usually add manually while testing. But now to complete
this, i will add that as well.
Why? Es1.0 will never be publically released, it never was meant to be public. ES2.0 is the only one meant to go out. Supporting ES1.0 and ES2.0 means a ton of redundant code being maintained in mainline with no product lines meant to actively using it - ever! Do we really want to do this??

Ok, i will clean up ES1.0 data in a separate patch series after this.

...

...
...
...

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{125, 0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{625, 6, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 7, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{750, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 15, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?
This file is common for ES1.0 as well.
ES1.0 DOES NOT run at 2GHz!

...

Ok, i will clean up ES1.0 data separately.

...

...
...
...

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */

{500, 2, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */

{2024, 16, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */

{625, 5, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */

{1000, 12, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */

{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */

{625, 11, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */ };

static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {

again, frequency is wrong for es2.0?
MPU runs at 1100 MHZ in OPP_NOM on 2.0
1099MHz - I suggest latest spec to be clear on this - i suggest reviewing further based on update.

MPU runs at 1099.9 MHZ

...

[...]

...
...
...

.iva = iva_dpll_params_2330mhz_es2,

+#ifdef CONFIG_SYS_OMAP_ABE_SYSCK

.abe = abe_dpll_params_sysclk_196608khz,

+#else

.abe = &abe_dpll_params_32k_196608khz,

+#endif

I strongly suggest dumping ABE sourcing from 32K clock - the code is just a nuisance waiting to exercise an unsupported silicon feature waiting to happen.

[...]

...
...
...
default: diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 15362ae..685aad5 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -208,6 +208,10 @@ #define VDD_MM_5432 1150 #define VDD_CORE_5432 1150

+#define VDD_MPU_ES2 1060 +#define VDD_MM_ES2 1025 +#define VDD_CORE_ES2 1040

^^^ these are meant only for OPP_NOM - considering that you have DPLLs for OPP_SB added in, do you even expect these devices to bootup at anything *but* OPP_NOM??

I agree. I add it manually while doing experiments. I will add these here.

As a rule we want maintainable s/w in mainline, not experimental code. maintainable s/w implies s/w that adheres to SoC's specified operational ranges unfortunately :(.

Regards, Sricharan

R Sricharan

4 Feb 4 Feb

3:29 p.m.

New subject: [U-Boot] [PATCH V2 4/5] ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs

From: Lokesh Vutla lokeshvutla@ti.com

Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for OMAP543X SOCs here.

Signed-off-by: R Sricharan r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hw_data.c | 14 ++++++ arch/arm/cpu/armv7/omap5/sdram.c | 75 +++++++++++++++++++++++++++++++- arch/arm/include/asm/arch-omap5/omap.h | 6 +++ arch/arm/include/asm/emif.h | 1 + 4 files changed, 94 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index 13ea07e..fd12b62 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -503,6 +503,16 @@ const struct ctrl_ioregs ioregs_omap5432_es1 = { .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, };

+const struct ctrl_ioregs ioregs_omap5432_es2 = { + .ctrl_ddrch = DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_lpddr2ch = 0x0, + .ctrl_ddr3ch = DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2, + .ctrl_ddrio_0 = DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_1 = DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_ddrio_2 = DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2, + .ctrl_emif_sdram_config_ext = SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, +}; + void hw_data_init(void) { u32 omap_rev = omap_revision(); @@ -541,11 +551,15 @@ void get_ioregs(const struct ctrl_ioregs **regs)

switch (omap_rev) { case OMAP5430_ES1_0: + case OMAP5430_ES2_0: *regs = &ioregs_omap5430; break; case OMAP5432_ES1_0: *regs = &ioregs_omap5432_es1; break; + case OMAP5432_ES2_0: + *regs = &ioregs_omap5432_es2; + break;

default: printf("\n INVALID OMAP REVISION "); diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 687800f..2ef7fcd 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -67,6 +67,25 @@ const struct emif_regs emif_regs_532_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 };

+const struct emif_regs emif_regs_532_mhz_2cs_es2 = { + .sdram_config_init = 0x80800EBA, + .sdram_config = 0x808022BA, + .ref_ctrl = 0x0000081A, + .sdram_tim1 = 0x772F6873, + .sdram_tim2 = 0x304a129a, + .sdram_tim3 = 0x02f7e45f, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x100b3215, + .temp_alert_config = 0x08000a05, + .emif_ddr_phy_ctlr_1_init = 0x0E30400d, + .emif_ddr_phy_ctlr_1 = 0x0E30400d, + .emif_ddr_ext_phy_ctrl_1 = 0x04020080, + .emif_ddr_ext_phy_ctrl_2 = 0x28C518A3, + .emif_ddr_ext_phy_ctrl_3 = 0x518A3146, + .emif_ddr_ext_phy_ctrl_4 = 0x0014628C, + .emif_ddr_ext_phy_ctrl_5 = 0xC330CC33, +}; + const struct emif_regs emif_regs_266_mhz_2cs = { .sdram_config_init = 0x80800EBA, .sdram_config = 0x808022BA, @@ -109,6 +128,29 @@ const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { .emif_rd_wr_exec_thresh = 0x00000305 };

+const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x1007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0030400A, + .emif_ddr_phy_ctlr_1 = 0x0034400A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x4350D435, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x40000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0x0, @@ -125,8 +167,12 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) case OMAP5432_ES1_0: *regs = &emif_regs_ddr3_532_mhz_1cs; break; + case OMAP5430_ES2_0: + *regs = &emif_regs_532_mhz_2cs_es2; + break; + case OMAP5432_ES2_0: default: - *regs = &emif_regs_ddr3_532_mhz_1cs; + *regs = &emif_regs_ddr3_532_mhz_1cs_es2; } }

@@ -210,6 +256,28 @@ const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000057 };

+const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x50D4350D, + 0x00000D43, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; + const struct lpddr2_mr_regs mr_regs = { .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, .mr2 = 0x6, @@ -222,13 +290,16 @@ static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs) { switch (omap_revision()) { case OMAP5430_ES1_0: + case OMAP5430_ES2_0: *regs = ext_phy_ctrl_const_base; break; case OMAP5432_ES1_0: *regs = ddr3_ext_phy_ctrl_const_base_es1; break; + case OMAP5432_ES2_0: default: - *regs = ddr3_ext_phy_ctrl_const_base_es1; + *regs = ddr3_ext_phy_ctrl_const_base_es2; + } }

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 71935d8..ba2775b 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -168,6 +168,12 @@ struct s32ktimer { #define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0

+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100 diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index fd530bb..9d72fe3 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -519,6 +519,7 @@

#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 #define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES_ES2 0x0000C1C7

/* DMM */ #define DMM_BASE 0x4E000040

-- 1.7.9.5

Tom Rini

4:44 p.m.

New subject: [U-Boot] [PATCH V2 4/5] ARM: OMAP5: Add DDR changes required for OMAP543X ES2.0 SOCs

On Mon, Feb 04, 2013 at 07:59:23PM +0530, R Sricharan wrote:

...

From: Lokesh Vutla lokeshvutla@ti.com

Add pre calculated timing settings of LPDDR2 and DDR3 memories present in OMAP5430 and OMAP5432 ES2.0 versions.

Also adding the DDR pad io settings required for OMAP543X SOCs here.

Signed-off-by: R Sricharan r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com

Reviewed-by: Tom Rini trini@ti.com

-- Tom

R Sricharan

3:29 p.m.

New subject: [U-Boot] [PATCH V2 5/5] ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup

From: Lokesh Vutla lokeshvutla@ti.com

After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code.

Signed-off-by: R Sricharan r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/hwinit-common.c | 6 ++ arch/arm/cpu/armv7/omap5/hwinit.c | 116 ++++++++++++++++++++++++ arch/arm/cpu/armv7/omap5/prcm-regs.c | 5 +- arch/arm/include/asm/arch-omap5/clocks.h | 4 + arch/arm/include/asm/arch-omap5/omap.h | 19 ++++ arch/arm/include/asm/arch-omap5/sys_proto.h | 1 + arch/arm/include/asm/omap_common.h | 2 + 7 files changed, 152 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 2aec2ea..00e246b 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -35,6 +35,7 @@ #include <asm/cache.h> #include <asm/system.h> #include <asm/omap_common.h> +#include <linux/compiler.h>

#define ARMV7_DCACHE_WRITEBACK 0xe #define ARMV7_DOMAIN_CLIENT 1 @@ -106,6 +107,10 @@ void spl_display_print(void) } #endif

+void __weak srcomp_enable(void) +{ +} + /* * Routine: s_init * Description: Does early system init of watchdog, muxing, andclocks @@ -132,6 +137,7 @@ void s_init(void) watchdog_init(); set_mux_conf_regs(); #ifdef CONFIG_SPL_BUILD + srcomp_enable(); setup_clocks_for_console();

gd = &gdata; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 0d8c95d..620b99a 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -32,6 +32,7 @@ #include <asm/armv7.h> #include <asm/arch/cpu.h> #include <asm/arch/sys_proto.h> +#include <asm/arch/clocks.h> #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> @@ -182,6 +183,121 @@ void do_io_settings(void) writel(EFUSE_3, (*ctrl)->control_efuse_3); writel(EFUSE_4, (*ctrl)->control_efuse_4); } + +static const struct srcomp_params srcomp_parameters[NUM_SYS_CLKS] = { + {0x45, 0x1}, /* 12 MHz */ + {-1, -1}, /* 13 MHz */ + {0x63, 0x2}, /* 16.8 MHz */ + {0x57, 0x2}, /* 19.2 MHz */ + {0x20, 0x1}, /* 26 MHz */ + {-1, -1}, /* 27 MHz */ + {0x41, 0x3} /* 38.4 MHz */ +}; + +void srcomp_enable(void) +{ + u32 srcomp_value, mul_factor, div_factor, clk_val, i; + u32 sysclk_ind = get_sys_clk_index(); + u32 omap_rev = omap_revision(); + + mul_factor = srcomp_parameters[sysclk_ind].multiply_factor; + div_factor = srcomp_parameters[sysclk_ind].divide_factor; + + for (i = 0; i < 4; i++) { + srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= + ~(MULTIPLY_FACTOR_XS_MASK | DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_north_side + i*4); + } + + if ((omap_rev == OMAP5430_ES1_0) || (omap_rev == OMAP5432_ES1_0)) { + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~PWRDWN_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + } else { + srcomp_value = readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~(MULTIPLY_FACTOR_XS_MASK | + DIVIDE_FACTOR_XS_MASK); + srcomp_value |= (mul_factor << MULTIPLY_FACTOR_XS_SHIFT) | + (div_factor << DIVIDE_FACTOR_XS_SHIFT); + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + for (i = 0; i < 4; i++) { + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value |= SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~OVERRIDE_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + + clk_val = readl((*prcm)->cm_coreaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_coreaon_io_srcomp_clkctrl); + + clk_val = readl((*prcm)->cm_wkupaon_io_srcomp_clkctrl); + clk_val |= OPTFCLKEN_SRCOMP_FCLK_MASK; + writel(clk_val, (*prcm)->cm_wkupaon_io_srcomp_clkctrl); + + for (i = 0; i < 4; i++) { + while (((readl((*ctrl)->control_srcomp_north_side + i*4) + & SRCODE_READ_XS_MASK) >> + SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_north_side + i*4); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, + (*ctrl)->control_srcomp_north_side + i*4); + } + + while (((readl((*ctrl)->control_srcomp_east_side_wkup) & + SRCODE_READ_XS_MASK) >> SRCODE_READ_XS_SHIFT) == 0) + ; + + srcomp_value = + readl((*ctrl)->control_srcomp_east_side_wkup); + srcomp_value &= ~SRCODE_OVERRIDE_SEL_XS_MASK; + writel(srcomp_value, (*ctrl)->control_srcomp_east_side_wkup); + } +} #endif

void config_data_eye_leveling_samples(u32 emif_base) diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 58c9d50..5e5abcc 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -149,6 +149,7 @@ struct prcm_regs const omap5_es1_prcm = {

/* cm2.core */ .cm_coreaon_bandgap_clkctrl = 0x4a008648, + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650, .cm_l3_1_clkstctrl = 0x4a008700, .cm_l3_1_dynamicdep = 0x4a008708, .cm_l3_1_l3_1_clkctrl = 0x4a008720, @@ -294,6 +295,7 @@ struct prcm_regs const omap5_es1_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07880, .cm_wkup_bandgap_clkctrl = 0x4ae07888, .cm_wkupaon_scrm_clkctrl = 0x4ae07890, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07898, .prm_vc_val_bypass = 0x4ae07ba0, .prm_vc_cfg_i2c_mode = 0x4ae07bb4, .prm_vc_cfg_i2c_clk = 0x4ae07bb8, @@ -502,7 +504,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_ssc_deltamstep_dpll_unipro = 0x4a0081e8, .cm_ssc_modfreqdiv_dpll_unipro = 0x4a0081ec, .cm_coreaon_bandgap_clkctrl = 0x4a008648, - + .cm_coreaon_io_srcomp_clkctrl = 0x4a008650,

/* cm2.core */ .cm_l3_1_clkstctrl = 0x4a008700, @@ -650,6 +652,7 @@ struct prcm_regs const omap5_es2_prcm = { .cm_wkup_rtc_clkctrl = 0x4ae07980, .cm_wkup_bandgap_clkctrl = 0x4ae07988, .cm_wkupaon_scrm_clkctrl = 0x4ae07990, + .cm_wkupaon_io_srcomp_clkctrl = 0x4ae07998, .prm_vc_val_bypass = 0x4ae07ca0, .prm_vc_cfg_i2c_mode = 0x4ae07cb4, .prm_vc_cfg_i2c_clk = 0x4ae07cb8, diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 685aad5..6f64186 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -186,6 +186,10 @@ #define OPTFCLKEN_SCRM_CORE_SHIFT 8 #define OPTFCLKEN_SCRM_CORE_MASK (1 << 8)

+/* CM_COREAON_IO_SRCOMP_CLKCTRL */ +#define OPTFCLKEN_SRCOMP_FCLK_SHIFT 8 +#define OPTFCLKEN_SRCOMP_FCLK_MASK (1 << 8) + /* Clock frequencies */ #define OMAP_SYS_CLK_FREQ_38_4_MHZ 38400000 #define OMAP_SYS_CLK_IND_38_4_MHZ 6 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index ba2775b..d29be93 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -229,7 +229,26 @@ struct s32ktimer { #define CH_FLAGS_CHFLASH (0x1 << 2) #define CH_FLAGS_CHMMCSD (0x1 << 3)

+/* CONTROL_SRCOMP_XXX_SIDE */ +#define OVERRIDE_XS_SHIFT 30 +#define OVERRIDE_XS_MASK (1 << 30) +#define SRCODE_READ_XS_SHIFT 12 +#define SRCODE_READ_XS_MASK (0xff << 12) +#define PWRDWN_XS_SHIFT 11 +#define PWRDWN_XS_MASK (1 << 11) +#define DIVIDE_FACTOR_XS_SHIFT 4 +#define DIVIDE_FACTOR_XS_MASK (0x7f << 4) +#define MULTIPLY_FACTOR_XS_SHIFT 1 +#define MULTIPLY_FACTOR_XS_MASK (0x7 << 1) +#define SRCODE_OVERRIDE_SEL_XS_SHIFT 0 +#define SRCODE_OVERRIDE_SEL_XS_MASK (1 << 0) + #ifndef __ASSEMBLY__ +struct srcomp_params { + s8 divide_factor; + s8 multiply_factor; +}; + struct omap_boot_parameters { char *boot_message; unsigned int mem_boot_descriptor; diff --git a/arch/arm/include/asm/arch-omap5/sys_proto.h b/arch/arm/include/asm/arch-omap5/sys_proto.h index 201ed6f..b8d841d 100644 --- a/arch/arm/include/asm/arch-omap5/sys_proto.h +++ b/arch/arm/include/asm/arch-omap5/sys_proto.h @@ -59,6 +59,7 @@ int omap_vc_bypass_send_value(u8 sa, u8 reg_addr, u8 reg_data); u32 warm_reset(void); void force_emif_self_refresh(void); void get_ioregs(const struct ctrl_ioregs **regs); +void srcomp_enable(void);

/* * This is used to verify if the configuration header diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 8a886ec..0af0c33 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -153,6 +153,7 @@ struct prcm_regs {

/* cm2.core */ u32 cm_coreaon_bandgap_clkctrl; + u32 cm_coreaon_io_srcomp_clkctrl; u32 cm_l3_1_clkstctrl; u32 cm_l3_1_dynamicdep; u32 cm_l3_1_l3_1_clkctrl; @@ -300,6 +301,7 @@ struct prcm_regs { u32 cm_wkup_rtc_clkctrl; u32 cm_wkup_bandgap_clkctrl; u32 cm_wkupaon_scrm_clkctrl; + u32 cm_wkupaon_io_srcomp_clkctrl; u32 prm_vc_val_bypass; u32 prm_vc_cfg_i2c_mode; u32 prm_vc_cfg_i2c_clk;

-- 1.7.9.5

Tom Rini

4:44 p.m.

New subject: [U-Boot] [PATCH V2 5/5] ARM: OMAP5: srcomp: enable slew rate compensation cells after powerup

On Mon, Feb 04, 2013 at 07:59:24PM +0530, R Sricharan wrote:

...

From: Lokesh Vutla lokeshvutla@ti.com

After power-up SRCOMP cells are by-passed by default in OMAP5. Software has to enable these SRCOMP sells. For ES2: All 5 SRCOMP cells needs to be enabled. For ES1: Only 4 SRCOMP cells in core power domain are enabled. The 1 in wkup domain is not enabled because smart i/os of wkup domain work with default compensation code.

Signed-off-by: R Sricharan r.sricharan@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com

Reviewed-by: Tom Rini trini@ti.com

-- Tom

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Nishanth Menon
R Sricharan
Tom Rini