From: Patrice Chotard patrice.chotard@st.com

In order to retrieve the clk_hse fixed clock phandle in clk_stm32f driver, add "u-boot,dm-pre-reloc" property in Uboot specific DT file.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/stm32f7-u-boot.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/stm32f7-u-boot.dtsi b/arch/arm/dts/stm32f7-u-boot.dtsi index a56ae93..9a9e4e5 100644 --- a/arch/arm/dts/stm32f7-u-boot.dtsi +++ b/arch/arm/dts/stm32f7-u-boot.dtsi @@ -26,3 +26,7 @@ &pwrcfg { u-boot,dm-pre-reloc; }; + +&clk_hse { + u-boot,dm-pre-reloc; +};

From: Patrice Chotard patrice.chotard@st.com

All current STM32F4 supported boards uses a 8MHz external oscillator. All current STM32F7 supported boards uses a 25MHz external oscillator.

In order to introduce the new stm32f429-evaluation board which uses a 25MHz external oscillator without creating a dedicated struct stm32_clk_info for this board, retrieve the external oscillator frequency from DT and set pll_m accordingly to obtain 1MHz for the VCO.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- drivers/clk/clk_stm32f.c | 78 +++++++++++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 63116e0..ebe1ce6 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -93,10 +93,9 @@ enum periph_clock { STMMAC_CLOCK_CFG, };

-struct stm32_clk_info stm32f4_clk_info = { +static const struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { - .pll_m = 8, .pll_n = 360, .pll_p = 2, .pll_q = 8, @@ -108,10 +107,9 @@ struct stm32_clk_info stm32f4_clk_info = { .v2 = false, };

-struct stm32_clk_info stm32f7_clk_info = { +static const struct stm32_clk_info stm32f7_clk_info = { /* 200 MHz */ .sys_pll_psc = { - .pll_m = 25, .pll_n = 400, .pll_p = 2, .pll_q = 8, @@ -126,7 +124,8 @@ struct stm32_clk_info stm32f7_clk_info = { struct stm32_clk { struct stm32_rcc_regs *base; struct stm32_pwr_regs *pwr_regs; - struct stm32_clk_info *info; + struct stm32_clk_info info; + unsigned long hse_rate; };

static int configure_clocks(struct udevice *dev) @@ -134,7 +133,7 @@ static int configure_clocks(struct udevice *dev) struct stm32_clk *priv = dev_get_priv(dev); struct stm32_rcc_regs *regs = priv->base; struct stm32_pwr_regs *pwr = priv->pwr_regs; - struct pll_psc sys_pll_psc = priv->info->sys_pll_psc; + struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc; u32 pllsaicfgr = 0;

/* Reset RCC configuration */ @@ -152,20 +151,20 @@ static int configure_clocks(struct udevice *dev) ;

setbits_le32(&regs->cfgr, (( - sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT) - | (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT) - | (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT))); + sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT) + | (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT) + | (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));

/* Configure the main PLL */ setbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */ clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLM_MASK, - sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT); + sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT); clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLN_MASK, - sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT); + sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT); clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLP_MASK, - ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); + ((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT); clrsetbits_le32(&regs->pllcfgr, RCC_PLLCFGR_PLLQ_MASK, - sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT); + sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);

/* Configure the SAI PLL to get a 48 MHz source */ pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 | @@ -178,7 +177,7 @@ static int configure_clocks(struct udevice *dev) while (!(readl(&regs->cr) & RCC_CR_PLLRDY)) ;

- if (priv->info->v2) { /*stm32f7 case */ + if (priv->info.v2) { /*stm32f7 case */ /* select PLLSAI as 48MHz clock source */ setbits_le32(&regs->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);

@@ -202,7 +201,7 @@ static int configure_clocks(struct udevice *dev)

setbits_le32(&regs->apb1enr, RCC_APB1ENR_PWREN);

- if (priv->info->has_overdrive) { + if (priv->info.has_overdrive) { /* * Enable high performance mode * System frequency up to 200 MHz @@ -241,7 +240,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, pllq = (readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK) >> RCC_PLLCFGR_PLLQ_SHIFT;

- if (priv->info->v2) /*stm32f7 case */ + if (priv->info.v2) /*stm32f7 case */ pllsai = readl(&regs->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL; else pllsai = readl(&regs->dckcfgr) & RCC_DCKCFGRX_CK48MSEL; @@ -253,7 +252,7 @@ static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv, >> RCC_PLLSAICFGR_PLLSAIN_SHIFT); pllsaip = ((((readl(&regs->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK) >> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1); - return ((CONFIG_STM32_HSE_HZ / pllm) * pllsain) / pllsaip; + return ((priv->hse_rate / pllm) * pllsain) / pllsaip; } /* PLL48CLK is selected from PLLQ */ return sysclk / pllq; @@ -281,7 +280,7 @@ static unsigned long stm32_clk_get_rate(struct clk *clk) >> RCC_PLLCFGR_PLLN_SHIFT); pllp = ((((readl(&regs->pllcfgr) & RCC_PLLCFGR_PLLP_MASK) >> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1); - sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp; + sysclk = ((priv->hse_rate / pllm) * plln) / pllp; } else { return -EINVAL; } @@ -372,6 +371,8 @@ void clock_setup(int peripheral) static int stm32_clk_probe(struct udevice *dev) { struct ofnode_phandle_args args; + struct udevice *fixed_clock_dev = NULL; + struct clk clk; int err;

debug("%s\n", __func__); @@ -387,16 +388,51 @@ static int stm32_clk_probe(struct udevice *dev)

switch (dev_get_driver_data(dev)) { case STM32F4: - priv->info = &stm32f4_clk_info; + memcpy(&priv->info, &stm32f4_clk_info, + sizeof(struct stm32_clk_info)); break; case STM32F7: - priv->info = &stm32f7_clk_info; + memcpy(&priv->info, &stm32f7_clk_info, + sizeof(struct stm32_clk_info)); break; default: return -EINVAL; }

- if (priv->info->has_overdrive) { + /* retrieve HSE frequency (external oscillator) */ + err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse", + &fixed_clock_dev); + + if (err) { + pr_err("Can't find fixed clock (%d)", err); + return err; + } + + err = clk_request(fixed_clock_dev, &clk); + if (err) { + pr_err("Can't request %s clk (%d)", fixed_clock_dev->name, + err); + return err; + } + + /* + * set pllm factor accordingly to the external oscillator + * frequency (HSE). For STM32F4 and STM32F7, we want VCO + * freq at 1MHz + * if input PLL frequency is 25Mhz, divide it by 25 + */ + clk.id = 0; + priv->hse_rate = clk_get_rate(&clk); + + if (priv->hse_rate < 1000000) { + pr_err("%s: unexpected HSE clock rate = %ld "n", __func__, + priv->hse_rate); + return -EINVAL; + } + + priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000; + + if (priv->info.has_overdrive) { err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, &args); if (err) {

From: Patrice Chotard patrice.chotard@st.com

As clk_stm32f driver is able to retrieve HSE frequency from DT, CONFIG_STM32_HSE_HZ becomes useless.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- include/configs/stm32f429-discovery.h | 2 -- include/configs/stm32f469-discovery.h | 1 - include/configs/stm32f746-disco.h | 1 - 3 files changed, 4 deletions(-)

diff --git a/include/configs/stm32f429-discovery.h b/include/configs/stm32f429-discovery.h index 1ad3698..af9daad 100644 --- a/include/configs/stm32f429-discovery.h +++ b/include/configs/stm32f429-discovery.h @@ -43,8 +43,6 @@

#define CONFIG_STM32_FLASH

-#define CONFIG_STM32_HSE_HZ 8000000 - #define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */

#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ diff --git a/include/configs/stm32f469-discovery.h b/include/configs/stm32f469-discovery.h index 1409999..c290a66 100644 --- a/include/configs/stm32f469-discovery.h +++ b/include/configs/stm32f469-discovery.h @@ -39,7 +39,6 @@

#define CONFIG_STM32_FLASH

-#define CONFIG_STM32_HSE_HZ 8000000 #define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */

diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index d12b1d8..301ab0f 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -37,7 +37,6 @@ #define CONFIG_MII #define CONFIG_PHY_SMSC

-#define CONFIG_STM32_HSE_HZ 25000000 #define CONFIG_SYS_CLK_FREQ 200000000 /* 200 MHz */ #define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */

From: Patrice Chotard patrice.chotard@st.com

Add stm32f429-evaluation board support. For more information, please visit: http://www.st.com/en/evaluation-tools/stm32429i-eval.html

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/mach-stm32/stm32f4/Kconfig | 4 ++ board/st/stm32f429-evaluation/Kconfig | 19 ++++++ board/st/stm32f429-evaluation/MAINTAINERS | 6 ++ board/st/stm32f429-evaluation/Makefile | 8 +++ .../st/stm32f429-evaluation/stm32f429-evaluation.c | 74 ++++++++++++++++++++++ configs/stm32f429-evaluation_defconfig | 31 +++++++++ include/configs/stm32f429-evaluation.h | 65 +++++++++++++++++++ 7 files changed, 207 insertions(+) create mode 100644 board/st/stm32f429-evaluation/Kconfig create mode 100644 board/st/stm32f429-evaluation/MAINTAINERS create mode 100644 board/st/stm32f429-evaluation/Makefile create mode 100644 board/st/stm32f429-evaluation/stm32f429-evaluation.c create mode 100644 configs/stm32f429-evaluation_defconfig create mode 100644 include/configs/stm32f429-evaluation.h

diff --git a/arch/arm/mach-stm32/stm32f4/Kconfig b/arch/arm/mach-stm32/stm32f4/Kconfig index 7005c65..e8fae4d 100644 --- a/arch/arm/mach-stm32/stm32f4/Kconfig +++ b/arch/arm/mach-stm32/stm32f4/Kconfig @@ -3,10 +3,14 @@ if STM32F4 config TARGET_STM32F429_DISCOVERY bool "STM32F429 Discovery board"

+config TARGET_STM32F429_EVALUATION + bool "STM32F429 Evaluation board" + config TARGET_STM32F469_DISCOVERY bool "STM32F469 Discovery board"

source "board/st/stm32f429-discovery/Kconfig" +source "board/st/stm32f429-evaluation/Kconfig" source "board/st/stm32f469-discovery/Kconfig"

endif diff --git a/board/st/stm32f429-evaluation/Kconfig b/board/st/stm32f429-evaluation/Kconfig new file mode 100644 index 0000000..ca4bb3d --- /dev/null +++ b/board/st/stm32f429-evaluation/Kconfig @@ -0,0 +1,19 @@ +if TARGET_STM32F429_EVALUATION + +config SYS_BOARD + string + default "stm32f429-evaluation" + +config SYS_VENDOR + string + default "st" + +config SYS_SOC + string + default "stm32f4" + +config SYS_CONFIG_NAME + string + default "stm32f429-evaluation" + +endif diff --git a/board/st/stm32f429-evaluation/MAINTAINERS b/board/st/stm32f429-evaluation/MAINTAINERS new file mode 100644 index 0000000..8b7b312 --- /dev/null +++ b/board/st/stm32f429-evaluation/MAINTAINERS @@ -0,0 +1,6 @@ +STM32F429-EVALUATION BOARD +M: Patrice Chotard patrice.chotard@st.com +S: Maintained +F: board/st/stm32f429-evaluation/ +F: include/configs/stm32f429-evaluation.h +F: configs/stm32f429-evaluation_defconfig diff --git a/board/st/stm32f429-evaluation/Makefile b/board/st/stm32f429-evaluation/Makefile new file mode 100644 index 0000000..3efba3a --- /dev/null +++ b/board/st/stm32f429-evaluation/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# Author(s): Patrice CHOTARD, patrice.chotard@st.com for STMicroelectronics. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := stm32f429-evaluation.o diff --git a/board/st/stm32f429-evaluation/stm32f429-evaluation.c b/board/st/stm32f429-evaluation/stm32f429-evaluation.c new file mode 100644 index 0000000..25e0207 --- /dev/null +++ b/board/st/stm32f429-evaluation/stm32f429-evaluation.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, patrice.chotard@st.com for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> + +#include <asm/io.h> +#include <asm/arch/stm32.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int rv; + struct udevice *dev; + + rv = uclass_get_device(UCLASS_RAM, 0, &dev); + if (rv) { + debug("DRAM init failed: %d\n", rv); + return rv; + } + + if (fdtdec_setup_memory_size() != 0) + rv = -EINVAL; + + return rv; +} + +int dram_init_banksize(void) +{ + fdtdec_setup_memory_banksize(); + + return 0; +} + +u32 get_board_rev(void) +{ + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + char serialno[25]; + u32 u_id_low, u_id_mid, u_id_high; + + if (!env_get("serial#")) { + u_id_low = readl(&STM32_U_ID->u_id_low); + u_id_mid = readl(&STM32_U_ID->u_id_mid); + u_id_high = readl(&STM32_U_ID->u_id_high); + sprintf(serialno, "%08x%08x%08x", + u_id_high, u_id_mid, u_id_low); + env_set("serial#", serialno); + } + + return 0; +} +#endif diff --git a/configs/stm32f429-evaluation_defconfig b/configs/stm32f429-evaluation_defconfig new file mode 100644 index 0000000..0d12fdb --- /dev/null +++ b/configs/stm32f429-evaluation_defconfig @@ -0,0 +1,31 @@ +CONFIG_ARM=y +CONFIG_STM32=y +CONFIG_SYS_MALLOC_F_LEN=0xF00 +CONFIG_STM32F4=y +CONFIG_TARGET_STM32F429_EVALUATION=y +CONFIG_DEFAULT_DEVICE_TREE="stm32429i-eval" +CONFIG_BOOTDELAY=3 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot > " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set +CONFIG_CMD_IMLS=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_DOS_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_OF_EMBED=y +# CONFIG_BLK is not set +CONFIG_DM_MMC=y +CONFIG_ARM_PL180_MMCI=y +CONFIG_MTD_NOR_FLASH=y diff --git a/include/configs/stm32f429-evaluation.h b/include/configs/stm32f429-evaluation.h new file mode 100644 index 0000000..ab33d0f --- /dev/null +++ b/include/configs/stm32f429-evaluation.h @@ -0,0 +1,65 @@ +/* + * Copyright (C) STMicroelectronics SA 2017 + * Author(s): Patrice CHOTARD, patrice.chotard@st.com for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_MISC_INIT_R + +#define CONFIG_SYS_FLASH_BASE 0x08000000 + +#define CONFIG_SYS_INIT_SP_ADDR 0x10010000 +#define CONFIG_SYS_TEXT_BASE 0x08000000 + +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * Configuration of the external SDRAM memory + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_RAM_FREQ_DIV 2 +#define CONFIG_SYS_RAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE +#define CONFIG_SYS_LOAD_ADDR 0x00400000 +#define CONFIG_LOADADDR 0x00400000 + +#define CONFIG_SYS_MAX_FLASH_SECT 12 +#define CONFIG_SYS_MAX_FLASH_BANKS 2 + +#define CONFIG_ENV_OFFSET (256 << 10) +#define CONFIG_ENV_SECT_SIZE (128 << 10) +#define CONFIG_ENV_SIZE (8 << 10) + +#define CONFIG_STM32_FLASH + +#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */ +#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_SYS_CBSIZE 1024 + +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) + +#define CONFIG_BOOTCOMMAND \ + "run boot_sd" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32429i-eval.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000" + +/* + * Command line configuration. + */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#endif /* __CONFIG_H */

From: Patrice Chotard patrice.chotard@st.com

This DT file comes from kernel v4.15, this board offers :

_ STM32F429NIH6 microcontroller _ 4.3” color TFT LCD with resistive touchscreen (480 x 272 pixels) _ Six 5 V power supply options: Power jack ST-LINK/V2 USB connector User USB HS connector User USB FS1 connector User USB FS2 connector Daughterboard _ SAI Audio DAC, stereo audio jack which supports headset with microphone _ Stereo digital microphone, audio terminal connector used to connect external speakers _ 2 GBytes (or more) SDIO interface MicroSD card _ RF EEPROM on I2 C compatible serial interface _ RS-232 communication _ IrDA transceiver _ JTAG/SWD and ETM trace debug support, ST-LINK/V2 embedded _ IEEE-802.3-2002 compliant Ethernet connector _ Camera module _ 8M x 32-bit SDRAM, 1M x 16-bit SRAM and 8M x 16-bit NOR Flash _ Joystick with 4-directional control and selector _ Reset, Wakeup and Tamper buttons _ 4 color user LEDs _ Extension connectors & memory connectors for daughterboard or wrapping board _ USB OTG HS and FS with Micro-AB connectors _ RTC with backup battery _ CAN2.0A/B compliant connection _ Potentiometer _ Motor control connector

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/stm32429i-eval.dts | 276 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 277 insertions(+) create mode 100644 arch/arm/dts/stm32429i-eval.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index f10482e..0626c76 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -214,6 +214,7 @@ dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \ dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb

dtb-$(CONFIG_STM32F4) += stm32f429-disco.dtb \ + stm32429i-eval.dtb \ stm32f469-disco.dtb

dtb-$(CONFIG_STM32F7) += stm32f746-disco.dtb \ diff --git a/arch/arm/dts/stm32429i-eval.dts b/arch/arm/dts/stm32429i-eval.dts new file mode 100644 index 0000000..362ea42 --- /dev/null +++ b/arch/arm/dts/stm32429i-eval.dts @@ -0,0 +1,276 @@ +/* + * Copyright (C) 2015, STMicroelectronics - All Rights Reserved + * Author: Maxime Coquelin mcoquelin.stm32@gmail.com for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +#include "stm32f429.dtsi" +#include "stm32f429-pinctrl.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "STMicroelectronics STM32429i-EVAL board"; + compatible = "st,stm32429i-eval", "st,stm32f429"; + + chosen { + bootargs = "root=/dev/ram"; + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0x00000000 0x2000000>; + }; + + aliases { + serial0 = &usart1; + }; + + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + dma-ranges = <0xc0000000 0x0 0x10000000>; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_vref: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + regulator-name = "vref"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + + leds { + compatible = "gpio-leds"; + green { + gpios = <&gpiog 6 1>; + linux,default-trigger = "heartbeat"; + }; + orange { + gpios = <&gpiog 7 1>; + }; + red { + gpios = <&gpiog 10 1>; + }; + blue { + gpios = <&gpiog 12 1>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + #address-cells = <1>; + #size-cells = <0>; + autorepeat; + button@0 { + label = "Wake up"; + linux,code = <KEY_WAKEUP>; + gpios = <&gpioa 0 0>; + }; + button@1 { + label = "Tamper"; + linux,code = <KEY_RESTART>; + gpios = <&gpioc 13 0>; + }; + }; + + usbotg_hs_phy: usbphy { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>; + clock-names = "main_clk"; + }; + + panel_rgb: panel-rgb { + compatible = "ampire,am-480272h3tmqw-t01h"; + status = "okay"; + port { + panel_in_rgb: endpoint { + remote-endpoint = <&ltdc_out_rgb>; + }; + }; + }; + + mmc_vcard: mmc_vcard { + compatible = "regulator-fixed"; + regulator-name = "mmc_vcard"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc { + pinctrl-names = "default"; + pinctrl-0 = <&adc3_in8_pin>; + vref-supply = <&reg_vref>; + status = "okay"; + adc3: adc@200 { + st,adc-channels = <8>; + status = "okay"; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +&crc { + status = "okay"; +}; + +&dcmi { + status = "okay"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&ov2640_0>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <1>; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + status = "okay"; + + ov2640: camera@30 { + compatible = "ovti,ov2640"; + reg = <0x30>; + resetb-gpios = <&stmpegpio 2 GPIO_ACTIVE_HIGH>; + pwdn-gpios = <&stmpegpio 0 GPIO_ACTIVE_LOW>; + clocks = <&clk_ext_camera>; + clock-names = "xvclk"; + status = "okay"; + + port { + ov2640_0: endpoint { + remote-endpoint = <&dcmi_0>; + }; + }; + }; + + stmpe1600: stmpe1600@42 { + compatible = "st,stmpe1600"; + reg = <0x42>; + interrupts = <8 3>; + interrupt-parent = <&gpioi>; + interrupt-controller; + wakeup-source; + + stmpegpio: stmpe_gpio { + compatible = "st,stmpe-gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +}; + +&iwdg { + status = "okay"; + timeout-sec = <32>; +}; + +&ltdc { + status = "okay"; + pinctrl-0 = <&ltdc_pins>; + pinctrl-names = "default"; + dma-ranges; + + port { + ltdc_out_rgb: endpoint { + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + +&mac { + status = "okay"; + pinctrl-0 = <&ethernet_mii>; + pinctrl-names = "default"; + phy-mode = "mii"; + phy-handle = <&phy1>; + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + +&rtc { + status = "okay"; +}; + +&sdio { + status = "okay"; + vmmc-supply = <&mmc_vcard>; + cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>; + cd-inverted; + pinctrl-names = "default", "opendrain"; + pinctrl-0 = <&sdio_pins>; + pinctrl-1 = <&sdio_pins_od>; + bus-width = <4>; +}; + +&timers1 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@0 { + status = "okay"; + }; +}; + +&timers3 { + status = "okay"; + + pwm { + pinctrl-0 = <&pwm3_pins>; + pinctrl-names = "default"; + status = "okay"; + }; + + timer@2 { + status = "okay"; + }; +}; + +&usart1 { + pinctrl-0 = <&usart1_pins_a>; + pinctrl-names = "default"; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + phys = <&usbotg_hs_phy>; + phy-names = "usb2-phy"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + status = "okay"; +};

From: Patrice Chotard patrice.chotard@st.com

_ Add gpio compatible and aliases for stm32f469 _ Add FMC sdram node _ Add "u-boot,dm-pre-reloc" for rcc, fmc, fixed-clock, pinctrl, pwrcfg and gpio nodes.

Signed-off-by: Patrice Chotard patrice.chotard@st.com --- arch/arm/dts/stm32429i-eval-u-boot.dtsi | 231 ++++++++++++++++++++++++++++++++ 1 file changed, 231 insertions(+) create mode 100644 arch/arm/dts/stm32429i-eval-u-boot.dtsi

diff --git a/arch/arm/dts/stm32429i-eval-u-boot.dtsi b/arch/arm/dts/stm32429i-eval-u-boot.dtsi new file mode 100644 index 0000000..826c942 --- /dev/null +++ b/arch/arm/dts/stm32429i-eval-u-boot.dtsi @@ -0,0 +1,231 @@ +/* + * Copyright (C) 2018, STMicroelectronics - All Rights Reserved + * Author(s): Patrice Chotard, patrice.chotard@st.com for STMicroelectronics. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/memory/stm32-sdram.h> +/{ + clocks { + u-boot,dm-pre-reloc; + }; + + aliases { + /* Aliases for gpios so as to use sequence */ + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + }; + + soc { + u-boot,dm-pre-reloc; + pin-controller { + u-boot,dm-pre-reloc; + }; + + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>; + st,syscfg = <&syscfg>; + pinctrl-0 = <&fmc_pins_d32>; + pinctrl-names = "default"; + st,mem_remap = <4>; + u-boot,dm-pre-reloc; + + /* + * Memory configuration from sdram + * MICRON MT48LC4M32B2B5-7 + */ + bank0: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_9 + NO_ROW_12 + MWIDTH_32 + BANKS_4 + CAS_3 + SDCLK_2 + RD_BURST_EN + RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_2 + TXSR_6 + TRAS_4 + TRC_6 + TWR_2 + TRP_2 + TRCD_2>; + st,sdram-refcount = < 2812 >; + }; + }; + }; +}; + +&clk_hse { + u-boot,dm-pre-reloc; +}; + +&clk_lse { + u-boot,dm-pre-reloc; +}; + +&clk_i2s_ckin { + u-boot,dm-pre-reloc; +}; + +&pwrcfg { + u-boot,dm-pre-reloc; +}; + +&syscfg { + u-boot,dm-pre-reloc; +}; + +&rcc { + u-boot,dm-pre-reloc; +}; + +&gpioa { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiob { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioc { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiod { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioe { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiof { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiog { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioh { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioi { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpioj { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&gpiok { + compatible = "st,stm32-gpio"; + u-boot,dm-pre-reloc; +}; + +&pinctrl { + usart1_pins_a: usart1@0 { + u-boot,dm-pre-reloc; + pins1 { + u-boot,dm-pre-reloc; + }; + pins2 { + u-boot,dm-pre-reloc; + }; + }; + + fmc_pins_d32: fmc_d32@0 { + u-boot,dm-pre-reloc; + pins + { + pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */ + <STM32_PINMUX('I', 9, AF12)>, /* D30 */ + <STM32_PINMUX('I', 7, AF12)>, /* D29 */ + <STM32_PINMUX('I', 6, AF12)>, /* D28 */ + <STM32_PINMUX('I', 3, AF12)>, /* D27 */ + <STM32_PINMUX('I', 2, AF12)>, /* D26 */ + <STM32_PINMUX('I', 1, AF12)>, /* D25 */ + <STM32_PINMUX('I', 0, AF12)>, /* D24 */ + <STM32_PINMUX('H',15, AF12)>, /* D23 */ + <STM32_PINMUX('H',14, AF12)>, /* D22 */ + <STM32_PINMUX('H',13, AF12)>, /* D21 */ + <STM32_PINMUX('H',12, AF12)>, /* D20 */ + <STM32_PINMUX('H',11, AF12)>, /* D19 */ + <STM32_PINMUX('H',10, AF12)>, /* D18 */ + <STM32_PINMUX('H', 9, AF12)>, /* D17 */ + <STM32_PINMUX('H', 8, AF12)>, /* D16 */ + + <STM32_PINMUX('D',10, AF12)>, /* D15 */ + <STM32_PINMUX('D', 9, AF12)>, /* D14 */ + <STM32_PINMUX('D', 8, AF12)>, /* D13 */ + <STM32_PINMUX('E',15, AF12)>, /* D12 */ + <STM32_PINMUX('E',14, AF12)>, /* D11 */ + <STM32_PINMUX('E',13, AF12)>, /* D10 */ + <STM32_PINMUX('E',12, AF12)>, /* D09 */ + <STM32_PINMUX('E',11, AF12)>, /* D08 */ + <STM32_PINMUX('E',10, AF12)>, /* D07 */ + <STM32_PINMUX('E', 9, AF12)>, /* D06 */ + <STM32_PINMUX('E', 8, AF12)>, /* D05 */ + <STM32_PINMUX('E', 7, AF12)>, /* D04 */ + <STM32_PINMUX('D', 1, AF12)>, /* D03 */ + <STM32_PINMUX('D', 0, AF12)>, /* D02 */ + <STM32_PINMUX('D',15, AF12)>, /* D01 */ + <STM32_PINMUX('D',14, AF12)>, /* D00 */ + + <STM32_PINMUX('E', 0, AF12)>, /* NBL0 */ + <STM32_PINMUX('E', 1, AF12)>, /* NBL1 */ + <STM32_PINMUX('I', 4, AF12)>, /* NBL2 */ + <STM32_PINMUX('I', 5, AF12)>, /* NBL3 */ + + <STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */ + <STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */ + <STM32_PINMUX('G', 3, AF12)>, /* A13 */ + <STM32_PINMUX('G', 2, AF12)>, /* A12 */ + <STM32_PINMUX('G', 1, AF12)>, /* A11 */ + <STM32_PINMUX('G', 0, AF12)>, /* A10 */ + <STM32_PINMUX('F',15, AF12)>, /* A09 */ + <STM32_PINMUX('F',14, AF12)>, /* A08 */ + <STM32_PINMUX('F',13, AF12)>, /* A07 */ + <STM32_PINMUX('F',12, AF12)>, /* A06 */ + <STM32_PINMUX('F', 5, AF12)>, /* A05 */ + <STM32_PINMUX('F', 4, AF12)>, /* A04 */ + <STM32_PINMUX('F', 3, AF12)>, /* A03 */ + <STM32_PINMUX('F', 2, AF12)>, /* A02 */ + <STM32_PINMUX('F', 1, AF12)>, /* A01 */ + <STM32_PINMUX('F', 0, AF12)>, /* A00 */ + + <STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */ + <STM32_PINMUX('H', 5, AF12)>, /* SDNWE */ + <STM32_PINMUX('F',11, AF12)>, /* SDNRAS */ + <STM32_PINMUX('G',15, AF12)>, /* SDNCAS */ + <STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */ + <STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */ + slew-rate = <2>; + u-boot,dm-pre-reloc; + }; + }; +};