[U-Boot] [PATCH v4 00/17] Add Intel Agilex SoC support
This is 4th version of patchset to add Intel Agilex SoC[1] support. Most of changes are related to _SOC64 prefix change and use base address from DT for managers access. Detail changelog can find in commit message.
This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion.
Patch status: No change: Patch 1, 4, 6, 7, 10, 11, 14, 17 Have changes: Patch 2, 3, 5, 8, 9, 12, 13, 15, 16
Detail change log is in patch commit message.
Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10.
Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/...
v3->v4: ------- - Rename _S10 to _SOC64 perfix for S10 and Agilex common defines. - Use base address from DT for managers access. - Add u-boot,dm-pre-reloc to sysmgr node in dts
History: --------- [v1]: https://patchwork.ozlabs.org/cover/1097830/ [v2]: https://patchwork.ozlabs.org/cover/1127440/ [v3]: https://patchwork.ozlabs.org/cover/1149863/
[1]: https://www.intel.com/content/www/us/en/products/programmable/fpga/agilex.ht... [2]: https://patchwork.ozlabs.org/cover/1160079/
Ley Foon Tan (17): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support arm: socfpga: Move Stratix10 and Agilex clock manager common code clk: agilex: Add clock driver for Agilex arm: socfpga: agilex: Add clock wrapper functions arm: socfpga: agilex: Add CCU support for Agilex arm: agilex: Add clock handoff offset for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts arm: socfpga: agilex: Enable Agilex SoC build
arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 +++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 75 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 ++++ arch/arm/mach-socfpga/Kconfig | 15 + arch/arm/mach-socfpga/Makefile | 18 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++ arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++ arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- .../mach-socfpga/{spl_s10.c => firewall.c} | 122 +--- .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/ccu_agilex.h | 67 ++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 + .../include/mach/clock_manager_s10.h | 16 +- .../include/mach/clock_manager_soc64.h | 23 + .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/handoff_s10.h | 9 +- .../mach-socfpga/include/mach/reset_manager.h | 2 + .../include/mach/reset_manager_agilex.h | 11 + .../include/mach/reset_manager_s10.h | 87 +-- .../include/mach/reset_manager_soc64.h | 38 ++ .../include/mach/system_manager.h | 2 + .../include/mach/system_manager_agilex.h | 11 + .../include/mach/system_manager_s10.h | 116 +--- .../include/mach/system_manager_soc64.h | 123 ++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc.c | 4 + arch/arm/mach-socfpga/misc_s10.c | 4 +- arch/arm/mach-socfpga/reset_manager_s10.c | 34 +- arch/arm/mach-socfpga/spl_agilex.c | 95 +++ arch/arm/mach-socfpga/spl_s10.c | 95 +-- arch/arm/mach-socfpga/system_manager_s10.c | 26 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 13 +- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 59 ++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 168 +++++ drivers/ddr/altera/sdram_s10.c | 298 +-------- drivers/ddr/altera/sdram_s10.h | 148 +---- drivers/ddr/altera/sdram_soc64.c | 304 +++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 71 ++- include/configs/socfpga_agilex_socdk.h | 207 +++++++ .../dt-bindings/clock/socfpga-soc64-clock.h | 84 +++ 51 files changed, 3105 insertions(+), 940 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (54%) create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%) create mode 100644 include/configs/socfpga_agilex_socdk.h create mode 100644 include/dt-bindings/clock/socfpga-soc64-clock.h
Add base address for Intel Agilex SoC.
Reuse base_addr_s10.h for Agilex, only one base address is different from S10.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
--- v2: - Reuse base_addr_s10.h and add #ifdef Agilex for SOCFPGA_FW_MPU_DDR_SCR_ADDRESS --- arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h index 1f549d7e70..d3eca65e97 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h @@ -10,7 +10,11 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000 #define SOCFPGA_SDR_ADDRESS 0xf8011000 +#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 +#else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 +#endif #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Move SYSMGR_DMA* to firewall.c
v3: - Move SOCFPGA_FIREWALL_TCU to firewall.c --- arch/arm/mach-socfpga/Makefile | 1 + .../mach-socfpga/{spl_s10.c => firewall.c} | 120 +++--------------- .../mach/{firewall_s10.h => firewall.h} | 10 +- arch/arm/mach-socfpga/spl_s10.c | 93 +------------- drivers/ddr/altera/sdram_s10.c | 2 +- 5 files changed, 26 insertions(+), 200 deletions(-) copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (56%) rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index fc1181cb27..dab34d0ef2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -51,6 +51,7 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += firewall.o obj-y += spl_s10.o endif endif diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/firewall.c similarity index 56% copy from arch/arm/mach-socfpga/spl_s10.c copy to arch/arm/mach-socfpga/firewall.c index 16f19f901d..7c9d317896 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -1,45 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> * */
#include <asm/io.h> -#include <asm/u-boot.h> -#include <asm/utils.h> #include <common.h> -#include <debug_uart.h> -#include <image.h> -#include <spl.h> -#include <asm/arch/clock_manager.h> -#include <asm/arch/firewall_s10.h> -#include <asm/arch/mailbox_s10.h> -#include <asm/arch/misc.h> -#include <asm/arch/reset_manager.h> +#include <asm/arch/firewall.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> -#include <dm/uclass.h>
-DECLARE_GLOBAL_DATA_PTR; - -u32 spl_boot_device(void) -{ - /* TODO: Get from SDM or handoff */ - return BOOT_DEVICE_MMC1; -} - -#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) - return MMCSD_MODE_FS; -#else - return MMCSD_MODE_RAW; -#endif -} -#endif - -void spl_disable_firewall_l4_per(void) +static void firewall_l4_per_disable(void) { const struct socfpga_firwall_l4_per *firwall_l4_per_base = (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; @@ -79,7 +49,7 @@ void spl_disable_firewall_l4_per(void) writel(FIREWALL_L4_DISABLE_ALL, addr[i]); }
-void spl_disable_firewall_l4_sys(void) +static void firewall_l4_sys_disable(void) { const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; @@ -113,83 +83,25 @@ void spl_disable_firewall_l4_sys(void) writel(FIREWALL_L4_DISABLE_ALL, addr[i]); }
-void board_init_f(ulong dummy) +static void firewall_bridge_disable(void) { - const struct cm_config *cm_default_cfg = cm_get_default_config(); - int ret; - - ret = spl_early_init(); - if (ret) - hang(); - - socfpga_get_manager_addr(); - -#ifdef CONFIG_HW_WATCHDOG - /* Ensure watchdog is paused when debugging is happening */ - writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, - socfpga_sysmgr_base + SYSMGR_S10_WDDBG); - - /* Enable watchdog before initializing the HW */ - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); - socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); - hw_watchdog_init(); -#endif - - /* ensure all processors are not released prior Linux boot */ - writeq(0, CPU_RELEASE_ADDR); - - socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0); - timer_init(); - - sysmgr_pinmux_init(); - - /* configuring the HPS clocks */ - cm_basic_init(cm_default_cfg); + /* disable lwsocf2fpga and soc2fpga bridge security */ + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); + writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); +}
-#ifdef CONFIG_DEBUG_UART - socfpga_per_reset(SOCFPGA_RESET(UART0), 0); - debug_uart_init(); -#endif +void firewall_setup(void) +{ + firewall_l4_per_disable(); + firewall_l4_sys_disable(); + firewall_bridge_disable();
- preloader_console_init(); - cm_print_clock_quick_summary(); + /* disable SMMU security */ + writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
/* enable non-secure interface to DMA330 DMA and peripherals */ writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, socfpga_sysmgr_base + SYSMGR_S10_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS, socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH); - - spl_disable_firewall_l4_per(); - - spl_disable_firewall_l4_sys(); - - /* disable lwsocf2fpga and soc2fpga bridge security */ - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); - - /* disable SMMU security */ - writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); - - /* disable ocram security at CCU for non secure access */ - clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), - CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); - clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0), - CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK); - -#if CONFIG_IS_ENABLED(ALTERA_SDRAM) - struct udevice *dev; - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - debug("DRAM init failed: %d\n", ret); - hang(); - } -#endif - - mbox_init(); - -#ifdef CONFIG_CADENCE_QSPI - mbox_qspi_open(); -#endif } diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall.h similarity index 94% rename from arch/arm/mach-socfpga/include/mach/firewall_s10.h rename to arch/arm/mach-socfpga/include/mach/firewall.h index b96f779f14..516bd1c0e1 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> * */
-#ifndef _FIREWALL_S10_ -#define _FIREWALL_S10_ +#ifndef _FIREWALL_H_ +#define _FIREWALL_H_
struct socfpga_firwall_l4_per { u32 nand; /* 0x00 */ @@ -117,4 +117,6 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
-#endif /* _FIREWALL_S10_ */ +void firewall_setup(void); + +#endif /* _FIREWALL_H_ */ diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 16f19f901d..cdfbd06327 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -12,7 +12,7 @@ #include <image.h> #include <spl.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/firewall_s10.h> +#include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> @@ -39,80 +39,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif
-void spl_disable_firewall_l4_per(void) -{ - const struct socfpga_firwall_l4_per *firwall_l4_per_base = - (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; - u32 i; - const u32 *addr[] = { - &firwall_l4_per_base->nand, - &firwall_l4_per_base->nand_data, - &firwall_l4_per_base->usb0, - &firwall_l4_per_base->usb1, - &firwall_l4_per_base->spim0, - &firwall_l4_per_base->spim1, - &firwall_l4_per_base->emac0, - &firwall_l4_per_base->emac1, - &firwall_l4_per_base->emac2, - &firwall_l4_per_base->sdmmc, - &firwall_l4_per_base->gpio0, - &firwall_l4_per_base->gpio1, - &firwall_l4_per_base->i2c0, - &firwall_l4_per_base->i2c1, - &firwall_l4_per_base->i2c2, - &firwall_l4_per_base->i2c3, - &firwall_l4_per_base->i2c4, - &firwall_l4_per_base->timer0, - &firwall_l4_per_base->timer1, - &firwall_l4_per_base->uart0, - &firwall_l4_per_base->uart1 - }; - - /* - * The following lines of code will enable non-secure access - * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This - * is needed as most OS run in non-secure mode. Thus we need to - * enable non-secure access to these peripherals in order for the - * OS to use these peripherals. - */ - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - -void spl_disable_firewall_l4_sys(void) -{ - const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = - (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; - u32 i; - const u32 *addr[] = { - &firwall_l4_sys_base->dma_ecc, - &firwall_l4_sys_base->emac0rx_ecc, - &firwall_l4_sys_base->emac0tx_ecc, - &firwall_l4_sys_base->emac1rx_ecc, - &firwall_l4_sys_base->emac1tx_ecc, - &firwall_l4_sys_base->emac2rx_ecc, - &firwall_l4_sys_base->emac2tx_ecc, - &firwall_l4_sys_base->nand_ecc, - &firwall_l4_sys_base->nand_read_ecc, - &firwall_l4_sys_base->nand_write_ecc, - &firwall_l4_sys_base->ocram_ecc, - &firwall_l4_sys_base->sdmmc_ecc, - &firwall_l4_sys_base->usb0_ecc, - &firwall_l4_sys_base->usb1_ecc, - &firwall_l4_sys_base->clock_manager, - &firwall_l4_sys_base->io_manager, - &firwall_l4_sys_base->reset_manager, - &firwall_l4_sys_base->system_manager, - &firwall_l4_sys_base->watchdog0, - &firwall_l4_sys_base->watchdog1, - &firwall_l4_sys_base->watchdog2, - &firwall_l4_sys_base->watchdog3 - }; - - for (i = 0; i < ARRAY_SIZE(addr); i++) - writel(FIREWALL_L4_DISABLE_ALL, addr[i]); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -154,22 +80,7 @@ void board_init_f(ulong dummy) preloader_console_init(); cm_print_clock_quick_summary();
- /* enable non-secure interface to DMA330 DMA and peripherals */ - writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, - socfpga_sysmgr_base + SYSMGR_S10_DMA); - writel(SYSMGR_DMAPERIPH_ALL_NS, - socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH); - - spl_disable_firewall_l4_per(); - - spl_disable_firewall_l4_sys(); - - /* disable lwsocf2fpga and soc2fpga bridge security */ - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA); - writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA); - - /* disable SMMU security */ - writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); + firewall_setup();
/* disable ocram security at CCU for non secure access */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0), diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d5812f2fd7..8948c31f45 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -13,7 +13,7 @@ #include <reset.h> #include "sdram_s10.h" #include <wait_bit.h> -#include <asm/arch/firewall_s10.h> +#include <asm/arch/firewall.h> #include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> #include <asm/io.h>
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Move firewall related code to new firewall.c, to share code in Stratix 10 and Agilex.
SDMMC will transfer data to OCRAM in SPL. So, enable privilege for SDMMC to allow DMA transfer to OCRAM.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Move SYSMGR_DMA* to firewall.c
v3:
- Move SOCFPGA_FIREWALL_TCU to firewall.c
arch/arm/mach-socfpga/Makefile | 1 + .../mach-socfpga/{spl_s10.c => firewall.c} | 120 +++--------------- .../mach/{firewall_s10.h => firewall.h} | 10 +- arch/arm/mach-socfpga/spl_s10.c | 93 +------------- drivers/ddr/altera/sdram_s10.c | 2 +- 5 files changed, 26 insertions(+), 200 deletions(-) copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (56%) rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index fc1181cb27..dab34d0ef2 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -51,6 +51,7 @@ ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 obj-y += spl_a10.o endif ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 +obj-y += firewall.o obj-y += spl_s10.o endif endif diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/firewall.c similarity index 56% copy from arch/arm/mach-socfpga/spl_s10.c copy to arch/arm/mach-socfpga/firewall.c index 16f19f901d..7c9d317896 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -1,45 +1,15 @@ // SPDX-License-Identifier: GPL-2.0 /*
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
#include <asm/io.h> -#include <asm/u-boot.h> -#include <asm/utils.h> #include <common.h> -#include <debug_uart.h> -#include <image.h> -#include <spl.h> -#include <asm/arch/clock_manager.h> -#include <asm/arch/firewall_s10.h> -#include <asm/arch/mailbox_s10.h> -#include <asm/arch/misc.h> -#include <asm/arch/reset_manager.h> +#include <asm/arch/firewall.h> #include <asm/arch/system_manager.h> -#include <watchdog.h> -#include <dm/uclass.h>
-DECLARE_GLOBAL_DATA_PTR;
-u32 spl_boot_device(void) -{
/* TODO: Get from SDM or handoff */return BOOT_DEVICE_MMC1;-}
-#ifdef CONFIG_SPL_MMC_SUPPORT -u32 spl_boot_mode(const u32 boot_device) -{ -#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
return MMCSD_MODE_FS;-#else
return MMCSD_MODE_RAW;-#endif -} -#endif
-void spl_disable_firewall_l4_per(void) +static void firewall_l4_per_disable(void) { const struct socfpga_firwall_l4_per *firwall_l4_per_base = (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER; @@ -79,7 +49,7 @@ void spl_disable_firewall_l4_per(void) writel(FIREWALL_L4_DISABLE_ALL, addr[i]); }
-void spl_disable_firewall_l4_sys(void) +static void firewall_l4_sys_disable(void) { const struct socfpga_firwall_l4_sys *firwall_l4_sys_base = (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS; @@ -113,83 +83,25 @@ void spl_disable_firewall_l4_sys(void) writel(FIREWALL_L4_DISABLE_ALL, addr[i]); }
-void board_init_f(ulong dummy) +static void firewall_bridge_disable(void) {
const struct cm_config *cm_default_cfg = cm_get_default_config();int ret;ret = spl_early_init();if (ret)hang();socfpga_get_manager_addr();-#ifdef CONFIG_HW_WATCHDOG
/* Ensure watchdog is paused when debugging is happening */writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,socfpga_sysmgr_base + SYSMGR_S10_WDDBG);/* Enable watchdog before initializing the HW */socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);hw_watchdog_init();-#endif
/* ensure all processors are not released prior Linux boot */writeq(0, CPU_RELEASE_ADDR);socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);timer_init();sysmgr_pinmux_init();/* configuring the HPS clocks */cm_basic_init(cm_default_cfg);
/* disable lwsocf2fpga and soc2fpga bridge security */writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);+}
-#ifdef CONFIG_DEBUG_UART
socfpga_per_reset(SOCFPGA_RESET(UART0), 0);debug_uart_init();-#endif +void firewall_setup(void) +{
firewall_l4_per_disable();firewall_l4_sys_disable();firewall_bridge_disable();
preloader_console_init();cm_print_clock_quick_summary();
/* disable SMMU security */writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU); /* enable non-secure interface to DMA330 DMA and peripherals */ writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, socfpga_sysmgr_base + SYSMGR_S10_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS, socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
spl_disable_firewall_l4_per();spl_disable_firewall_l4_sys();/* disable lwsocf2fpga and soc2fpga bridge security */writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);/* disable SMMU security */writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);/* disable ocram security at CCU for non secure access */clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);-#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
struct udevice *dev;ret = uclass_get_device(UCLASS_RAM, 0, &dev);if (ret) {debug("DRAM init failed: %d\n", ret);hang();}-#endif
mbox_init();-#ifdef CONFIG_CADENCE_QSPI
mbox_qspi_open();-#endif } diff --git a/arch/arm/mach-socfpga/include/mach/firewall_s10.h b/arch/arm/mach-socfpga/include/mach/firewall.h similarity index 94% rename from arch/arm/mach-socfpga/include/mach/firewall_s10.h rename to arch/arm/mach-socfpga/include/mach/firewall.h index b96f779f14..516bd1c0e1 100644 --- a/arch/arm/mach-socfpga/include/mach/firewall_s10.h +++ b/arch/arm/mach-socfpga/include/mach/firewall.h @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
-#ifndef _FIREWALL_S10_ -#define _FIREWALL_S10_ +#ifndef _FIREWALL_H_ +#define _FIREWALL_H_
struct socfpga_firwall_l4_per { u32 nand; /* 0x00 */ @@ -117,4 +117,6 @@ struct socfpga_firwall_l4_sys { #define FW_MPU_DDR_SCR_WRITEL(data, reg) \ writel(data, SOCFPGA_FW_MPU_DDR_SCR_ADDRESS + (reg))
-#endif /* _FIREWALL_S10_ */ +void firewall_setup(void);
+#endif /* _FIREWALL_H_ */ diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index 16f19f901d..cdfbd06327 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -12,7 +12,7 @@ #include <image.h> #include <spl.h> #include <asm/arch/clock_manager.h> -#include <asm/arch/firewall_s10.h> +#include <asm/arch/firewall.h> #include <asm/arch/mailbox_s10.h> #include <asm/arch/misc.h> #include <asm/arch/reset_manager.h> @@ -39,80 +39,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif
-void spl_disable_firewall_l4_per(void) -{
const struct socfpga_firwall_l4_per *firwall_l4_per_base =(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;u32 i;const u32 *addr[] = {&firwall_l4_per_base->nand,&firwall_l4_per_base->nand_data,&firwall_l4_per_base->usb0,&firwall_l4_per_base->usb1,&firwall_l4_per_base->spim0,&firwall_l4_per_base->spim1,&firwall_l4_per_base->emac0,&firwall_l4_per_base->emac1,&firwall_l4_per_base->emac2,&firwall_l4_per_base->sdmmc,&firwall_l4_per_base->gpio0,&firwall_l4_per_base->gpio1,&firwall_l4_per_base->i2c0,&firwall_l4_per_base->i2c1,&firwall_l4_per_base->i2c2,&firwall_l4_per_base->i2c3,&firwall_l4_per_base->i2c4,&firwall_l4_per_base->timer0,&firwall_l4_per_base->timer1,&firwall_l4_per_base->uart0,&firwall_l4_per_base->uart1};/** The following lines of code will enable non-secure access* to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This* is needed as most OS run in non-secure mode. Thus we need to* enable non-secure access to these peripherals in order for the* OS to use these peripherals.*/for (i = 0; i < ARRAY_SIZE(addr); i++)writel(FIREWALL_L4_DISABLE_ALL, addr[i]);-}
-void spl_disable_firewall_l4_sys(void) -{
const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;u32 i;const u32 *addr[] = {&firwall_l4_sys_base->dma_ecc,&firwall_l4_sys_base->emac0rx_ecc,&firwall_l4_sys_base->emac0tx_ecc,&firwall_l4_sys_base->emac1rx_ecc,&firwall_l4_sys_base->emac1tx_ecc,&firwall_l4_sys_base->emac2rx_ecc,&firwall_l4_sys_base->emac2tx_ecc,&firwall_l4_sys_base->nand_ecc,&firwall_l4_sys_base->nand_read_ecc,&firwall_l4_sys_base->nand_write_ecc,&firwall_l4_sys_base->ocram_ecc,&firwall_l4_sys_base->sdmmc_ecc,&firwall_l4_sys_base->usb0_ecc,&firwall_l4_sys_base->usb1_ecc,&firwall_l4_sys_base->clock_manager,&firwall_l4_sys_base->io_manager,&firwall_l4_sys_base->reset_manager,&firwall_l4_sys_base->system_manager,&firwall_l4_sys_base->watchdog0,&firwall_l4_sys_base->watchdog1,&firwall_l4_sys_base->watchdog2,&firwall_l4_sys_base->watchdog3};for (i = 0; i < ARRAY_SIZE(addr); i++)writel(FIREWALL_L4_DISABLE_ALL, addr[i]);-}
void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -154,22 +80,7 @@ void board_init_f(ulong dummy) preloader_console_init(); cm_print_clock_quick_summary();
/* enable non-secure interface to DMA330 DMA and peripherals */writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,socfpga_sysmgr_base + SYSMGR_S10_DMA);writel(SYSMGR_DMAPERIPH_ALL_NS,socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);spl_disable_firewall_l4_per();spl_disable_firewall_l4_sys();/* disable lwsocf2fpga and soc2fpga bridge security */writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);/* disable SMMU security */writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
firewall_setup(); /* disable ocram security at CCU for non secure access */ clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index d5812f2fd7..8948c31f45 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -13,7 +13,7 @@ #include <reset.h> #include "sdram_s10.h" #include <wait_bit.h> -#include <asm/arch/firewall_s10.h> +#include <asm/arch/firewall.h> #include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h>
#include <asm/io.h>
2.19.0
Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Change prefix from RSTMGR_S10* to RSTMGR_SOC64*.
v3: - Add new reset_manager_soc64.h - Convert to use defines instead of struct. --- .../include/mach/reset_manager_s10.h | 87 +------------------ .../include/mach/reset_manager_soc64.h | 38 ++++++++ arch/arm/mach-socfpga/reset_manager_s10.c | 20 ++--- 3 files changed, 50 insertions(+), 95 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index b602129656..fdc9c8c9a4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -1,95 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> * */
#ifndef _RESET_MANAGER_S10_ #define _RESET_MANAGER_S10_
-void reset_cpu(ulong addr); -int cpu_has_been_warmreset(void); - -void socfpga_bridges_reset(int enable); - -void socfpga_per_reset(u32 reset, int set); -void socfpga_per_reset_all(void); - -#define RSTMGR_S10_STATUS 0 -#define RSTMGR_S10_MPUMODRST 0x20 -#define RSTMGR_S10_PER0MODRST 0x24 -#define RSTMGR_S10_PER1MODRST 0x28 -#define RSTMGR_S10_BRGMODRST 0x2c - -#define RSTMGR_MPUMODRST_CORE0 0 -#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 - -/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 - -/* - * Define a reset identifier, from which a permodrst bank ID - * and reset ID can be extracted using the subsequent macros - * RSTMGR_RESET() and RSTMGR_BANK(). - */ -#define RSTMGR_BANK_OFFSET 8 -#define RSTMGR_BANK_MASK 0x7 -#define RSTMGR_RESET_OFFSET 0 -#define RSTMGR_RESET_MASK 0x1f -#define RSTMGR_DEFINE(_bank, _offset) \ - ((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET) - -/* Extract reset ID from the reset identifier. */ -#define RSTMGR_RESET(_reset) \ - (((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK) - -/* Extract bank ID from the reset identifier. */ -#define RSTMGR_BANK(_reset) \ - (((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK) - -/* - * SocFPGA Stratix10 reset IDs, bank mapping is as follows: - * 0 ... mpumodrst - * 1 ... per0modrst - * 2 ... per1modrst - * 3 ... brgmodrst - */ -#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) -#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) -#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) -#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) -#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) -#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) -#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) -#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) -#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) -#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) -#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) -#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) -#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) -#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) -#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) -#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) -#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) -#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) -#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) -#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) -#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) -#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) -#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) -#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) -#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) -#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) -#define RSTMGR_SDR RSTMGR_DEFINE(3, 6) - -/* Create a human-readable reference to SoCFPGA reset. */ -#define SOCFPGA_RESET(_name) RSTMGR_##_name +#include <asm/arch/reset_manager_soc64.h>
#endif /* _RESET_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h new file mode 100644 index 0000000000..3b739a0202 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + */ + +#ifndef _RESET_MANAGER_SOC64_H_ +#define _RESET_MANAGER_SOC64_H_ + +void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); +void socfpga_bridges_reset(int enable); + +#define RSTMGR_SOC64_STATUS 0 +#define RSTMGR_SOC64_MPUMODRST 0x20 +#define RSTMGR_SOC64_PER0MODRST 0x24 +#define RSTMGR_SOC64_PER1MODRST 0x28 +#define RSTMGR_SOC64_BRGMODRST 0x2c + +#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004 + +/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00 + +/* + * SocFPGA Stratix10 reset IDs, bank mapping is as follows: + * 0 ... mpumodrst + * 1 ... per0modrst + * 2 ... per1modrst + * 3 ... brgmodrst + */ +#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) + +#endif /* _RESET_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 50a2d80930..bdc0f3ee6e 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -18,13 +18,13 @@ void socfpga_per_reset(u32 reset, int set) unsigned long reg;
if (RSTMGR_BANK(reset) == 0) - reg = RSTMGR_S10_MPUMODRST; + reg = RSTMGR_SOC64_MPUMODRST; else if (RSTMGR_BANK(reset) == 1) - reg = RSTMGR_S10_PER0MODRST; + reg = RSTMGR_SOC64_PER0MODRST; else if (RSTMGR_BANK(reset) == 2) - reg = RSTMGR_S10_PER1MODRST; + reg = RSTMGR_SOC64_PER1MODRST; else if (RSTMGR_BANK(reset) == 3) - reg = RSTMGR_S10_BRGMODRST; + reg = RSTMGR_SOC64_BRGMODRST; else /* Invalid reset register, do nothing */ return;
@@ -47,9 +47,9 @@ void socfpga_per_reset_all(void)
/* disable all except OCP and l4wd0. OCP disable later */ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK), - socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST); - writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST); - writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST); + socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST); + writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST); + writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_SOC64_PER1MODRST); }
void socfpga_bridges_reset(int enable) @@ -60,7 +60,7 @@ void socfpga_bridges_reset(int enable) ~0);
/* Release all bridges from reset state */ - clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0); + clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0);
/* Poll until all idleack to 0 */ while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK)) @@ -83,7 +83,7 @@ void socfpga_bridges_reset(int enable) ;
/* Reset all bridges (except NOR DDR scheduler & F2S) */ - setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, + setbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~(RSTMGR_BRGMODRST_DDRSCH_MASK | RSTMGR_BRGMODRST_FPGA2SOC_MASK));
@@ -97,6 +97,6 @@ void socfpga_bridges_reset(int enable) */ int cpu_has_been_warmreset(void) { - return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) & + return readl(socfpga_rstmgr_base + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK; }
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Move Stratix10 and Agilex reset manager common code to reset_manager_soc64.h.
Remove unused RSTMGR_XXX defines.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Change prefix from RSTMGR_S10* to RSTMGR_SOC64*.
v3:
- Add new reset_manager_soc64.h
- Convert to use defines instead of struct.
.../include/mach/reset_manager_s10.h | 87 +------------------ .../include/mach/reset_manager_soc64.h | 38 ++++++++ arch/arm/mach-socfpga/reset_manager_s10.c | 20 ++--- 3 files changed, 50 insertions(+), 95 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h index b602129656..fdc9c8c9a4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_s10.h @@ -1,95 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
#ifndef _RESET_MANAGER_S10_ #define _RESET_MANAGER_S10_
-void reset_cpu(ulong addr); -int cpu_has_been_warmreset(void);
-void socfpga_bridges_reset(int enable);
-void socfpga_per_reset(u32 reset, int set); -void socfpga_per_reset_all(void);
-#define RSTMGR_S10_STATUS 0 -#define RSTMGR_S10_MPUMODRST 0x20 -#define RSTMGR_S10_PER0MODRST 0x24 -#define RSTMGR_S10_PER1MODRST 0x28 -#define RSTMGR_S10_BRGMODRST 0x2c
-#define RSTMGR_MPUMODRST_CORE0 0 -#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 -#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 -#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
-/* Watchdogs and MPU warm reset mask */ -#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
-/*
- Define a reset identifier, from which a permodrst bank ID
- and reset ID can be extracted using the subsequent macros
- RSTMGR_RESET() and RSTMGR_BANK().
- */
-#define RSTMGR_BANK_OFFSET 8 -#define RSTMGR_BANK_MASK 0x7 -#define RSTMGR_RESET_OFFSET 0 -#define RSTMGR_RESET_MASK 0x1f -#define RSTMGR_DEFINE(_bank, _offset) \
((_bank) << RSTMGR_BANK_OFFSET) | ((_offset) << RSTMGR_RESET_OFFSET)-/* Extract reset ID from the reset identifier. */ -#define RSTMGR_RESET(_reset) \
(((_reset) >> RSTMGR_RESET_OFFSET) & RSTMGR_RESET_MASK)-/* Extract bank ID from the reset identifier. */ -#define RSTMGR_BANK(_reset) \
(((_reset) >> RSTMGR_BANK_OFFSET) & RSTMGR_BANK_MASK)-/*
- SocFPGA Stratix10 reset IDs, bank mapping is as follows:
- 0 ... mpumodrst
- 1 ... per0modrst
- 2 ... per1modrst
- 3 ... brgmodrst
- */
-#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0) -#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1) -#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2) -#define RSTMGR_USB0 RSTMGR_DEFINE(1, 3) -#define RSTMGR_USB1 RSTMGR_DEFINE(1, 4) -#define RSTMGR_NAND RSTMGR_DEFINE(1, 5) -#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7) -#define RSTMGR_EMAC0_OCP RSTMGR_DEFINE(1, 8) -#define RSTMGR_EMAC1_OCP RSTMGR_DEFINE(1, 9) -#define RSTMGR_EMAC2_OCP RSTMGR_DEFINE(1, 10) -#define RSTMGR_USB0_OCP RSTMGR_DEFINE(1, 11) -#define RSTMGR_USB1_OCP RSTMGR_DEFINE(1, 12) -#define RSTMGR_NAND_OCP RSTMGR_DEFINE(1, 13) -#define RSTMGR_SDMMC_OCP RSTMGR_DEFINE(1, 15) -#define RSTMGR_DMA RSTMGR_DEFINE(1, 16) -#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17) -#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18) -#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) -#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1) -#define RSTMGR_L4WD2 RSTMGR_DEFINE(2, 2) -#define RSTMGR_L4WD3 RSTMGR_DEFINE(2, 3) -#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) -#define RSTMGR_I2C0 RSTMGR_DEFINE(2, 8) -#define RSTMGR_I2C1 RSTMGR_DEFINE(2, 9) -#define RSTMGR_I2C2 RSTMGR_DEFINE(2, 10) -#define RSTMGR_I2C3 RSTMGR_DEFINE(2, 11) -#define RSTMGR_I2C4 RSTMGR_DEFINE(2, 12) -#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16) -#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17) -#define RSTMGR_GPIO0 RSTMGR_DEFINE(2, 24) -#define RSTMGR_GPIO1 RSTMGR_DEFINE(2, 25) -#define RSTMGR_SDR RSTMGR_DEFINE(3, 6)
-/* Create a human-readable reference to SoCFPGA reset. */ -#define SOCFPGA_RESET(_name) RSTMGR_##_name +#include <asm/arch/reset_manager_soc64.h>
#endif /* _RESET_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h new file mode 100644 index 0000000000..3b739a0202 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
+#ifndef _RESET_MANAGER_SOC64_H_ +#define _RESET_MANAGER_SOC64_H_
+void reset_deassert_peripherals_handoff(void); +int cpu_has_been_warmreset(void); +void socfpga_bridges_reset(int enable);
+#define RSTMGR_SOC64_STATUS 0 +#define RSTMGR_SOC64_MPUMODRST 0x20 +#define RSTMGR_SOC64_PER0MODRST 0x24 +#define RSTMGR_SOC64_PER1MODRST 0x28 +#define RSTMGR_SOC64_BRGMODRST 0x2c
+#define RSTMGR_MPUMODRST_CORE0 0 +#define RSTMGR_PER0MODRST_OCP_MASK 0x0020bf00 +#define RSTMGR_BRGMODRST_DDRSCH_MASK 0X00000040 +#define RSTMGR_BRGMODRST_FPGA2SOC_MASK 0x00000004
+/* Watchdogs and MPU warm reset mask */ +#define RSTMGR_L4WD_MPU_WARMRESET_MASK 0x000F0F00
+/*
- SocFPGA Stratix10 reset IDs, bank mapping is as follows:
- 0 ... mpumodrst
- 1 ... per0modrst
- 2 ... per1modrst
- 3 ... brgmodrst
- */
+#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0) +#define RSTMGR_OSC1TIMER0 RSTMGR_DEFINE(2, 4) +#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
+#endif /* _RESET_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index 50a2d80930..bdc0f3ee6e 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -18,13 +18,13 @@ void socfpga_per_reset(u32 reset, int set) unsigned long reg;
if (RSTMGR_BANK(reset) == 0)
reg = RSTMGR_S10_MPUMODRST;
reg = RSTMGR_SOC64_MPUMODRST; else if (RSTMGR_BANK(reset) == 1)
reg = RSTMGR_S10_PER0MODRST;
reg = RSTMGR_SOC64_PER0MODRST; else if (RSTMGR_BANK(reset) == 2)
reg = RSTMGR_S10_PER1MODRST;
reg = RSTMGR_SOC64_PER1MODRST; else if (RSTMGR_BANK(reset) == 3)
reg = RSTMGR_S10_BRGMODRST;
reg = RSTMGR_SOC64_BRGMODRST; else /* Invalid reset register, do nothing */ return;@@ -47,9 +47,9 @@ void socfpga_per_reset_all(void)
/* disable all except OCP and l4wd0. OCP disable later */ writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_S10_PER0MODRST);writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_S10_PER1MODRST);
socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST);writel(~l4wd0, socfpga_rstmgr_base + RSTMGR_SOC64_PER0MODRST);writel(0xffffffff, socfpga_rstmgr_base + RSTMGR_SOC64_PER1MODRST);}
void socfpga_bridges_reset(int enable) @@ -60,7 +60,7 @@ void socfpga_bridges_reset(int enable) ~0);
/* Release all bridges from reset state */
clrbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST, ~0);
clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0); /* Poll until all idleack to 0 */ while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))@@ -83,7 +83,7 @@ void socfpga_bridges_reset(int enable) ;
/* Reset all bridges (except NOR DDR scheduler & F2S) */
setbits_le32(socfpga_rstmgr_base + RSTMGR_S10_BRGMODRST,
setbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~(RSTMGR_BRGMODRST_DDRSCH_MASK | RSTMGR_BRGMODRST_FPGA2SOC_MASK));@@ -97,6 +97,6 @@ void socfpga_bridges_reset(int enable) */ int cpu_has_been_warmreset(void) {
return readl(socfpga_rstmgr_base + RSTMGR_S10_STATUS) &
return readl(socfpga_rstmgr_base + RSTMGR_SOC64_STATUS) & RSTMGR_L4WD_MPU_WARMRESET_MASK;}
2.19.0
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v3: - Add reset_manager_soc64.h - Convert to use defines instead of struct. --- arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ .../mach-socfpga/include/mach/reset_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index a5b6931350..019c518ae4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -45,6 +45,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_agilex.h> #endif
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h new file mode 100644 index 0000000000..617e06ec06 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _RESET_MANAGER_AGILEX_ +#define _RESET_MANAGER_AGILEX_ + +#include <asm/arch/reset_manager_soc64.h> + +#endif /* _RESET_MANAGER_AGILEX_ */
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ .../mach-socfpga/include/mach/reset_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index a5b6931350..019c518ae4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -45,6 +45,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_agilex.h>
Why don't you just include reset_manager_soc64.h here? No need for the additional file.
Regards, Simon
#endif
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h new file mode 100644 index 0000000000..617e06ec06 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _RESET_MANAGER_AGILEX_ +#define _RESET_MANAGER_AGILEX_
+#include <asm/arch/reset_manager_soc64.h>
+#endif /* _RESET_MANAGER_AGILEX_ */
2.19.0
On Wed, Oct 2, 2019 at 4:26 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ .../mach-socfpga/include/mach/reset_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index a5b6931350..019c518ae4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -45,6 +45,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_agilex.h>
Why don't you just include reset_manager_soc64.h here? No need for the additional file.
Do you mean remove reset_manager_s10.h and reset_manager_agilex.h and include reset_manager_soc64.h directly? These 2 header files includes reset_manager_soc64.h and don't have additional define in them now.
Regards Ley Foon
#endif
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h new file mode 100644 index 0000000000..617e06ec06 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _RESET_MANAGER_AGILEX_ +#define _RESET_MANAGER_AGILEX_
+#include <asm/arch/reset_manager_soc64.h>
+#endif /* _RESET_MANAGER_AGILEX_ */
2.19.0
On Wed, Oct 2, 2019 at 11:25 AM Ley Foon Tan lftan.linux@gmail.com wrote:
On Wed, Oct 2, 2019 at 4:26 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ .../mach-socfpga/include/mach/reset_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index a5b6931350..019c518ae4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -45,6 +45,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_agilex.h>
Why don't you just include reset_manager_soc64.h here? No need for the additional file.
Do you mean remove reset_manager_s10.h and reset_manager_agilex.h and include reset_manager_soc64.h directly? These 2 header files includes reset_manager_soc64.h and don't have additional define in them now.
Right, these files could be removed, no? Unless you're planning to add anything to them soon...
Regards, Simon
Regards Ley Foon
#endif
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h new file mode 100644 index 0000000000..617e06ec06 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _RESET_MANAGER_AGILEX_ +#define _RESET_MANAGER_AGILEX_
+#include <asm/arch/reset_manager_soc64.h>
+#endif /* _RESET_MANAGER_AGILEX_ */
2.19.0
On Wed, Oct 2, 2019 at 6:16 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Wed, Oct 2, 2019 at 11:25 AM Ley Foon Tan lftan.linux@gmail.com wrote:
On Wed, Oct 2, 2019 at 4:26 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add reset manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Add reset_manager_soc64.h
- Convert to use defines instead of struct.
arch/arm/mach-socfpga/include/mach/reset_manager.h | 2 ++ .../mach-socfpga/include/mach/reset_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager.h b/arch/arm/mach-socfpga/include/mach/reset_manager.h index a5b6931350..019c518ae4 100644 --- a/arch/arm/mach-socfpga/include/mach/reset_manager.h +++ b/arch/arm/mach-socfpga/include/mach/reset_manager.h @@ -45,6 +45,8 @@ void socfpga_per_reset_all(void); #include <asm/arch/reset_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/reset_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/reset_manager_agilex.h>
Why don't you just include reset_manager_soc64.h here? No need for the additional file.
Do you mean remove reset_manager_s10.h and reset_manager_agilex.h and include reset_manager_soc64.h directly? These 2 header files includes reset_manager_soc64.h and don't have additional define in them now.
Right, these files could be removed, no? Unless you're planning to add anything to them soon...
Will remove them.
Regards Ley Foon
Regards Ley Foon
#endif
#endif /* _RESET_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h new file mode 100644 index 0000000000..617e06ec06 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _RESET_MANAGER_AGILEX_ +#define _RESET_MANAGER_AGILEX_
+#include <asm/arch/reset_manager_soc64.h>
+#endif /* _RESET_MANAGER_AGILEX_ */
2.19.0
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Change prefix from SYSMGR_S10* to SYSMGR_SOC64*.
v3: - Change filename to system_manager_soc64.h - Move to use defines instead of struct.
v2: - Move common defines for Stratix 10 and Agilex to system_manager_s10_agilex_common.h --- arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- arch/arm/mach-socfpga/firewall.c | 4 +- .../include/mach/system_manager_s10.h | 116 +---------------- .../include/mach/system_manager_soc64.h | 123 ++++++++++++++++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc_s10.c | 4 +- arch/arm/mach-socfpga/reset_manager_s10.c | 14 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- arch/arm/mach-socfpga/system_manager_s10.c | 26 ++-- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 8 +- drivers/ddr/altera/sdram_s10.c | 2 +- 11 files changed, 157 insertions(+), 146 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index c6269701f0..bae07e02b6 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -382,7 +382,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
unsigned int cm_get_qspi_controller_clk_hz(void) { - return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0); + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); }
unsigned int cm_get_spi_controller_clk_hz(void) diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 7c9d317896..c32a7c84b5 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -101,7 +101,7 @@ void firewall_setup(void)
/* enable non-secure interface to DMA330 DMA and peripherals */ writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, - socfpga_sysmgr_base + SYSMGR_S10_DMA); + socfpga_sysmgr_base + SYSMGR_SOC64_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS, - socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH); + socfpga_sysmgr_base + SYSMGR_SOC64_DMA_PERIPH); } diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h index e68a8e730e..c537fb300c 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -1,124 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> * */
#ifndef _SYSTEM_MANAGER_S10_ #define _SYSTEM_MANAGER_S10_
-void sysmgr_pinmux_init(void); -void populate_sysmgr_fpgaintf_module(void); -void populate_sysmgr_pinmux(void); -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); - -#define SYSMGR_S10_WDDBG 0x8 -#define SYSMGR_S10_DMA 0x20 -#define SYSMGR_S10_DMA_PERIPH 0x24 -#define SYSMGR_S10_SDMMC 0x28 -#define SYSMGR_S10_SDMMC_L3MASTER 0x2c -#define SYSMGR_S10_EMAC_GLOBAL 0x40 -#define SYSMGR_S10_EMAC0 0x44 -#define SYSMGR_S10_EMAC1 0x48 -#define SYSMGR_S10_EMAC2 0x4c -#define SYSMGR_S10_EMAC0_ACE 0x50 -#define SYSMGR_S10_EMAC1_ACE 0x54 -#define SYSMGR_S10_EMAC2_ACE 0x58 -#define SYSMGR_S10_NAND_AXUSER 0x5c -#define SYSMGR_S10_FPGAINTF_EN1 0x68 -#define SYSMGR_S10_FPGAINTF_EN2 0x6c -#define SYSMGR_S10_FPGAINTF_EN3 0x70 -#define SYSMGR_S10_DMA_L3MASTER 0x74 -#define SYSMGR_S10_HMC_CLK 0xb4 -#define SYSMGR_S10_IO_PA_CTRL 0xb8 -#define SYSMGR_S10_NOC_TIMEOUT 0xc0 -#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_S10_NOC_IDLEACK 0xd0 -#define SYSMGR_S10_NOC_IDLESTATUS 0xd4 -#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8 -#define SYSMGR_S10_FPGA_CONFIG 0xdc -#define SYSMGR_S10_IOCSRCLK_GATE 0xe0 -#define SYSMGR_S10_GPO 0xe4 -#define SYSMGR_S10_GPI 0xe8 -#define SYSMGR_S10_MPU 0xf0 -#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200 -#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204 -#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208 -#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c -#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210 -#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214 -#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218 -#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c -#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220 -#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224 -#define SYSMGR_S10_PINSEL0 0x1000 -#define SYSMGR_S10_IOCTRL0 0x1130 -#define SYSMGR_S10_EMAC0_USEFPGA 0x1300 -#define SYSMGR_S10_EMAC1_USEFPGA 0x1304 -#define SYSMGR_S10_EMAC2_USEFPGA 0x1308 -#define SYSMGR_S10_I2C0_USEFPGA 0x130c -#define SYSMGR_S10_I2C1_USEFPGA 0x1310 -#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314 -#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318 -#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c -#define SYSMGR_S10_NAND_USEFPGA 0x1320 -#define SYSMGR_S10_SPIM0_USEFPGA 0x1328 -#define SYSMGR_S10_SPIM1_USEFPGA 0x132c -#define SYSMGR_S10_SPIS0_USEFPGA 0x1330 -#define SYSMGR_S10_SPIS1_USEFPGA 0x1334 -#define SYSMGR_S10_UART0_USEFPGA 0x1338 -#define SYSMGR_S10_UART1_USEFPGA 0x133c -#define SYSMGR_S10_MDIO0_USEFPGA 0x1340 -#define SYSMGR_S10_MDIO1_USEFPGA 0x1344 -#define SYSMGR_S10_MDIO2_USEFPGA 0x1348 -#define SYSMGR_S10_JTAG_USEFPGA 0x1350 -#define SYSMGR_S10_SDMMC_USEFPGA 0x1354 -#define SYSMGR_S10_HPS_OSC_CLK 0x1358 -#define SYSMGR_S10_IODELAY0 0x1400 - -#define SYSMGR_SDMMC SYSMGR_S10_SDMMC - -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) -#define SYSMGR_ECC_OCRAM_EN BIT(0) -#define SYSMGR_ECC_OCRAM_SERR BIT(3) -#define SYSMGR_ECC_OCRAM_DERR BIT(4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1 - -#define SYSMGR_FPGAINTF_NAND BIT(4) -#define SYSMGR_FPGAINTF_SDMMC BIT(8) -#define SYSMGR_FPGAINTF_SPIM0 BIT(16) -#define SYSMGR_FPGAINTF_SPIM1 BIT(24) -#define SYSMGR_FPGAINTF_EMAC0 BIT(0) -#define SYSMGR_FPGAINTF_EMAC1 BIT(8) -#define SYSMGR_FPGAINTF_EMAC2 BIT(16) - -#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 -#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 - -/* EMAC Group Bit definitions */ -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 - -#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 - -#define SYSMGR_NOC_H2F_MSK 0x00000001 -#define SYSMGR_NOC_LWH2F_MSK 0x00000010 -#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 - -#define SYSMGR_DMA_IRQ_NS 0xFF000000 -#define SYSMGR_DMA_MGR_NS 0x00010000 - -#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF - -#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F +#include <asm/arch/system_manager_soc64.h>
#endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h new file mode 100644 index 0000000000..c09e4ee19c --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _SYSTEM_MANAGER_SOC64_H_ +#define _SYSTEM_MANAGER_SOC64_H_ + +void sysmgr_pinmux_init(void); +void populate_sysmgr_fpgaintf_module(void); +void populate_sysmgr_pinmux(void); +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len); + +#define SYSMGR_SOC64_WDDBG 0x8 +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 +#define SYSMGR_SOC64_EMAC0 0x44 +#define SYSMGR_SOC64_EMAC1 0x48 +#define SYSMGR_SOC64_EMAC2 0x4c +#define SYSMGR_SOC64_EMAC0_ACE 0x50 +#define SYSMGR_SOC64_EMAC1_ACE 0x54 +#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#define SYSMGR_SOC64_NAND_AXUSER 0x5c +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_DMA_L3MASTER 0x74 +#define SYSMGR_SOC64_HMC_CLK 0xb4 +#define SYSMGR_SOC64_IO_PA_CTRL 0xb8 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xdc +#define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 +#define SYSMGR_SOC64_GPO 0xe4 +#define SYSMGR_SOC64_GPI 0xe8 +#define SYSMGR_SOC64_MPU 0xf0 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SOC64_PINSEL0 0x1000 +#define SYSMGR_SOC64_IOCTRL0 0x1130 +#define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 +#define SYSMGR_SOC64_EMAC1_USEFPGA 0x1304 +#define SYSMGR_SOC64_EMAC2_USEFPGA 0x1308 +#define SYSMGR_SOC64_I2C0_USEFPGA 0x130c +#define SYSMGR_SOC64_I2C1_USEFPGA 0x1310 +#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA 0x1314 +#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA 0x1318 +#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA 0x131c +#define SYSMGR_SOC64_NAND_USEFPGA 0x1320 +#define SYSMGR_SOC64_SPIM0_USEFPGA 0x1328 +#define SYSMGR_SOC64_SPIM1_USEFPGA 0x132c +#define SYSMGR_SOC64_SPIS0_USEFPGA 0x1330 +#define SYSMGR_SOC64_SPIS1_USEFPGA 0x1334 +#define SYSMGR_SOC64_UART0_USEFPGA 0x1338 +#define SYSMGR_SOC64_UART1_USEFPGA 0x133c +#define SYSMGR_SOC64_MDIO0_USEFPGA 0x1340 +#define SYSMGR_SOC64_MDIO1_USEFPGA 0x1344 +#define SYSMGR_SOC64_MDIO2_USEFPGA 0x1348 +#define SYSMGR_SOC64_JTAG_USEFPGA 0x1350 +#define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354 +#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 +#define SYSMGR_SOC64_IODELAY0 0x1400 + +#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC + +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1 + +#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(8) +#define SYSMGR_FPGAINTF_SPIM0 BIT(16) +#define SYSMGR_FPGAINTF_SPIM1 BIT(24) +#define SYSMGR_FPGAINTF_EMAC0 BIT(0) +#define SYSMGR_FPGAINTF_EMAC1 BIT(8) +#define SYSMGR_FPGAINTF_EMAC2 BIT(16) + +#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0 + +/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2 + +#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3 + +#define SYSMGR_NOC_H2F_MSK 0x00000001 +#define SYSMGR_NOC_LWH2F_MSK 0x00000010 +#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001 + +#define SYSMGR_DMA_IRQ_NS 0xFF000000 +#define SYSMGR_DMA_MGR_NS 0x00010000 + +#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF + +#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F + +#endif /* _SYSTEM_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 11b57361c7..ba81461f90 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -316,7 +316,7 @@ int mbox_qspi_open(void) /* We are getting QSPI ref clock and set into sysmgr boot register */ printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); writel(resp_buf[0], - socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0); + socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
return 0;
diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 16fbf71599..ba95ab566b 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -65,8 +65,8 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) else return -EINVAL;
- clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 + - gmac_index), + clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + + SYSMGR_SOC64_EMAC0 + gmac_index), SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
return 0; diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index bdc0f3ee6e..938999043e 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -56,29 +56,29 @@ void socfpga_bridges_reset(int enable) { if (enable) { /* clear idle request to all bridges */ - setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR, + setbits_le32(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
/* Release all bridges from reset state */ clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0);
/* Poll until all idleack to 0 */ - while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK)) + while (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK)) ; } else { /* set idle request to all bridges */ - writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET); + writel(~0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_SET);
/* Enable the NOC timeout */ - writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT); + writel(1, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT);
/* Poll until all idleack to 1 */ - while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^ + while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ;
/* Poll until all idlestatus to 1 */ - while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^ + while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ;
@@ -88,7 +88,7 @@ void socfpga_bridges_reset(int enable) RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */ - writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT); + writel(0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT); } }
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index cdfbd06327..fabedba6d1 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -53,7 +53,7 @@ void board_init_f(ulong dummy) #ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, - socfpga_sysmgr_base + SYSMGR_S10_WDDBG); + socfpga_sysmgr_base + SYSMGR_SOC64_WDDBG);
/* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c index c046bb17c9..0da9431517 100644 --- a/arch/arm/mach-socfpga/system_manager_s10.c +++ b/arch/arm/mach-socfpga/system_manager_s10.c @@ -29,31 +29,31 @@ void populate_sysmgr_fpgaintf_module(void) u32 handoff_val = 0;
/* Enable the signal for those HPS peripherals that use FPGA. */ - if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NAND_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_NAND; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SDMMC_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SDMMC; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM0_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM0; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM1_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM1; - writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2); + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN2);
handoff_val = 0; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC0; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC1_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC1; - if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) == + if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC2_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC2; - writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3); + writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN3); }
/* @@ -69,7 +69,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] + - (u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0); + (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_PINSEL0); }
/* setup the pin ctrl */ @@ -77,7 +77,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] + - (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0); + (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IOCTRL0); }
/* setup the fpga use */ @@ -85,7 +85,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] + - (u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA); + (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA); }
/* setup the IO delay */ @@ -93,6 +93,6 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] + - (u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0); + (u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IODELAY0); } } diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index c9570fea38..b002f38215 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -35,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void) #ifdef CONFIG_SPL_BUILD u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
- writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1); + writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif - return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1); + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); }
const unsigned int cm_get_intosc_clk_hz(void) @@ -50,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void) #ifdef CONFIG_SPL_BUILD u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
- writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2); + writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif - return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2); + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); } diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 8948c31f45..9578aa743d 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -148,7 +148,7 @@ static int emif_reset(struct altera_sdram_platdata *plat) static int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_sysmgr_base + - SYSMGR_S10_HMC_CLK), + SYSMGR_SOC64_HMC_CLK), SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); }
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Move Stratix10 and Agilex system manager common code to system_manager_soc64.h.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Change prefix from SYSMGR_S10* to SYSMGR_SOC64*.
v3:
- Change filename to system_manager_soc64.h
- Move to use defines instead of struct.
v2:
- Move common defines for Stratix 10 and Agilex to system_manager_s10_agilex_common.h
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- arch/arm/mach-socfpga/firewall.c | 4 +- .../include/mach/system_manager_s10.h | 116 +---------------- .../include/mach/system_manager_soc64.h | 123 ++++++++++++++++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc_s10.c | 4 +- arch/arm/mach-socfpga/reset_manager_s10.c | 14 +- arch/arm/mach-socfpga/spl_s10.c | 2 +- arch/arm/mach-socfpga/system_manager_s10.c | 26 ++-- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 8 +- drivers/ddr/altera/sdram_s10.c | 2 +- 11 files changed, 157 insertions(+), 146 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/clock_manager_s10.c b/arch/arm/mach-socfpga/clock_manager_s10.c index c6269701f0..bae07e02b6 100644 --- a/arch/arm/mach-socfpga/clock_manager_s10.c +++ b/arch/arm/mach-socfpga/clock_manager_s10.c @@ -382,7 +382,7 @@ unsigned int cm_get_l4_sp_clk_hz(void)
unsigned int cm_get_qspi_controller_clk_hz(void) {
return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);}
unsigned int cm_get_spi_controller_clk_hz(void) diff --git a/arch/arm/mach-socfpga/firewall.c b/arch/arm/mach-socfpga/firewall.c index 7c9d317896..c32a7c84b5 100644 --- a/arch/arm/mach-socfpga/firewall.c +++ b/arch/arm/mach-socfpga/firewall.c @@ -101,7 +101,7 @@ void firewall_setup(void)
/* enable non-secure interface to DMA330 DMA and peripherals */ writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS,
socfpga_sysmgr_base + SYSMGR_S10_DMA);
socfpga_sysmgr_base + SYSMGR_SOC64_DMA); writel(SYSMGR_DMAPERIPH_ALL_NS,
socfpga_sysmgr_base + SYSMGR_S10_DMA_PERIPH);
socfpga_sysmgr_base + SYSMGR_SOC64_DMA_PERIPH);} diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h index e68a8e730e..c537fb300c 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_s10.h @@ -1,124 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
#ifndef _SYSTEM_MANAGER_S10_ #define _SYSTEM_MANAGER_S10_
-void sysmgr_pinmux_init(void); -void populate_sysmgr_fpgaintf_module(void); -void populate_sysmgr_pinmux(void); -void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); -void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
-#define SYSMGR_S10_WDDBG 0x8 -#define SYSMGR_S10_DMA 0x20 -#define SYSMGR_S10_DMA_PERIPH 0x24 -#define SYSMGR_S10_SDMMC 0x28 -#define SYSMGR_S10_SDMMC_L3MASTER 0x2c -#define SYSMGR_S10_EMAC_GLOBAL 0x40 -#define SYSMGR_S10_EMAC0 0x44 -#define SYSMGR_S10_EMAC1 0x48 -#define SYSMGR_S10_EMAC2 0x4c -#define SYSMGR_S10_EMAC0_ACE 0x50 -#define SYSMGR_S10_EMAC1_ACE 0x54 -#define SYSMGR_S10_EMAC2_ACE 0x58 -#define SYSMGR_S10_NAND_AXUSER 0x5c -#define SYSMGR_S10_FPGAINTF_EN1 0x68 -#define SYSMGR_S10_FPGAINTF_EN2 0x6c -#define SYSMGR_S10_FPGAINTF_EN3 0x70 -#define SYSMGR_S10_DMA_L3MASTER 0x74 -#define SYSMGR_S10_HMC_CLK 0xb4 -#define SYSMGR_S10_IO_PA_CTRL 0xb8 -#define SYSMGR_S10_NOC_TIMEOUT 0xc0 -#define SYSMGR_S10_NOC_IDLEREQ_SET 0xc4 -#define SYSMGR_S10_NOC_IDLEREQ_CLR 0xc8 -#define SYSMGR_S10_NOC_IDLEREQ_VAL 0xcc -#define SYSMGR_S10_NOC_IDLEACK 0xd0 -#define SYSMGR_S10_NOC_IDLESTATUS 0xd4 -#define SYSMGR_S10_FPGA2SOC_CTRL 0xd8 -#define SYSMGR_S10_FPGA_CONFIG 0xdc -#define SYSMGR_S10_IOCSRCLK_GATE 0xe0 -#define SYSMGR_S10_GPO 0xe4 -#define SYSMGR_S10_GPI 0xe8 -#define SYSMGR_S10_MPU 0xf0 -#define SYSMGR_S10_BOOT_SCRATCH_COLD0 0x200 -#define SYSMGR_S10_BOOT_SCRATCH_COLD1 0x204 -#define SYSMGR_S10_BOOT_SCRATCH_COLD2 0x208 -#define SYSMGR_S10_BOOT_SCRATCH_COLD3 0x20c -#define SYSMGR_S10_BOOT_SCRATCH_COLD4 0x210 -#define SYSMGR_S10_BOOT_SCRATCH_COLD5 0x214 -#define SYSMGR_S10_BOOT_SCRATCH_COLD6 0x218 -#define SYSMGR_S10_BOOT_SCRATCH_COLD7 0x21c -#define SYSMGR_S10_BOOT_SCRATCH_COLD8 0x220 -#define SYSMGR_S10_BOOT_SCRATCH_COLD9 0x224 -#define SYSMGR_S10_PINSEL0 0x1000 -#define SYSMGR_S10_IOCTRL0 0x1130 -#define SYSMGR_S10_EMAC0_USEFPGA 0x1300 -#define SYSMGR_S10_EMAC1_USEFPGA 0x1304 -#define SYSMGR_S10_EMAC2_USEFPGA 0x1308 -#define SYSMGR_S10_I2C0_USEFPGA 0x130c -#define SYSMGR_S10_I2C1_USEFPGA 0x1310 -#define SYSMGR_S10_I2C_EMAC0_USEFPGA 0x1314 -#define SYSMGR_S10_I2C_EMAC1_USEFPGA 0x1318 -#define SYSMGR_S10_I2C_EMAC2_USEFPGA 0x131c -#define SYSMGR_S10_NAND_USEFPGA 0x1320 -#define SYSMGR_S10_SPIM0_USEFPGA 0x1328 -#define SYSMGR_S10_SPIM1_USEFPGA 0x132c -#define SYSMGR_S10_SPIS0_USEFPGA 0x1330 -#define SYSMGR_S10_SPIS1_USEFPGA 0x1334 -#define SYSMGR_S10_UART0_USEFPGA 0x1338 -#define SYSMGR_S10_UART1_USEFPGA 0x133c -#define SYSMGR_S10_MDIO0_USEFPGA 0x1340 -#define SYSMGR_S10_MDIO1_USEFPGA 0x1344 -#define SYSMGR_S10_MDIO2_USEFPGA 0x1348 -#define SYSMGR_S10_JTAG_USEFPGA 0x1350 -#define SYSMGR_S10_SDMMC_USEFPGA 0x1354 -#define SYSMGR_S10_HPS_OSC_CLK 0x1358 -#define SYSMGR_S10_IODELAY0 0x1400
-#define SYSMGR_SDMMC SYSMGR_S10_SDMMC
-#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) -#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) -#define SYSMGR_ECC_OCRAM_EN BIT(0) -#define SYSMGR_ECC_OCRAM_SERR BIT(3) -#define SYSMGR_ECC_OCRAM_DERR BIT(4) -#define SYSMGR_FPGAINTF_USEFPGA 0x1
-#define SYSMGR_FPGAINTF_NAND BIT(4) -#define SYSMGR_FPGAINTF_SDMMC BIT(8) -#define SYSMGR_FPGAINTF_SPIM0 BIT(16) -#define SYSMGR_FPGAINTF_SPIM1 BIT(24) -#define SYSMGR_FPGAINTF_EMAC0 BIT(0) -#define SYSMGR_FPGAINTF_EMAC1 BIT(8) -#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
-#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 -#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
-/* EMAC Group Bit definitions */ -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
-#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 -#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 -#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
-#define SYSMGR_NOC_H2F_MSK 0x00000001 -#define SYSMGR_NOC_LWH2F_MSK 0x00000010 -#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
-#define SYSMGR_DMA_IRQ_NS 0xFF000000 -#define SYSMGR_DMA_MGR_NS 0x00010000
-#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
-#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F +#include <asm/arch/system_manager_soc64.h>
#endif /* _SYSTEM_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h new file mode 100644 index 0000000000..c09e4ee19c --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _SYSTEM_MANAGER_SOC64_H_ +#define _SYSTEM_MANAGER_SOC64_H_
+void sysmgr_pinmux_init(void); +void populate_sysmgr_fpgaintf_module(void); +void populate_sysmgr_pinmux(void); +void sysmgr_pinmux_table_sel(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_ctrl(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_fpga(const u32 **table, unsigned int *table_len); +void sysmgr_pinmux_table_delay(const u32 **table, unsigned int *table_len);
+#define SYSMGR_SOC64_WDDBG 0x8 +#define SYSMGR_SOC64_DMA 0x20 +#define SYSMGR_SOC64_DMA_PERIPH 0x24 +#define SYSMGR_SOC64_SDMMC 0x28 +#define SYSMGR_SOC64_SDMMC_L3MASTER 0x2c +#define SYSMGR_SOC64_EMAC_GLOBAL 0x40 +#define SYSMGR_SOC64_EMAC0 0x44 +#define SYSMGR_SOC64_EMAC1 0x48 +#define SYSMGR_SOC64_EMAC2 0x4c +#define SYSMGR_SOC64_EMAC0_ACE 0x50 +#define SYSMGR_SOC64_EMAC1_ACE 0x54 +#define SYSMGR_SOC64_EMAC2_ACE 0x58 +#define SYSMGR_SOC64_NAND_AXUSER 0x5c +#define SYSMGR_SOC64_FPGAINTF_EN1 0x68 +#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c +#define SYSMGR_SOC64_FPGAINTF_EN3 0x70 +#define SYSMGR_SOC64_DMA_L3MASTER 0x74 +#define SYSMGR_SOC64_HMC_CLK 0xb4 +#define SYSMGR_SOC64_IO_PA_CTRL 0xb8 +#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0 +#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4 +#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8 +#define SYSMGR_SOC64_NOC_IDLEREQ_VAL 0xcc +#define SYSMGR_SOC64_NOC_IDLEACK 0xd0 +#define SYSMGR_SOC64_NOC_IDLESTATUS 0xd4 +#define SYSMGR_SOC64_FPGA2SOC_CTRL 0xd8 +#define SYSMGR_SOC64_FPGA_CONFIG 0xdc +#define SYSMGR_SOC64_IOCSRCLK_GATE 0xe0 +#define SYSMGR_SOC64_GPO 0xe4 +#define SYSMGR_SOC64_GPI 0xe8 +#define SYSMGR_SOC64_MPU 0xf0 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD0 0x200 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD1 0x204 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD2 0x208 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD3 0x20c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD4 0x210 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD5 0x214 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD6 0x218 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD7 0x21c +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD8 0x220 +#define SYSMGR_SOC64_BOOT_SCRATCH_COLD9 0x224 +#define SYSMGR_SOC64_PINSEL0 0x1000 +#define SYSMGR_SOC64_IOCTRL0 0x1130 +#define SYSMGR_SOC64_EMAC0_USEFPGA 0x1300 +#define SYSMGR_SOC64_EMAC1_USEFPGA 0x1304 +#define SYSMGR_SOC64_EMAC2_USEFPGA 0x1308 +#define SYSMGR_SOC64_I2C0_USEFPGA 0x130c +#define SYSMGR_SOC64_I2C1_USEFPGA 0x1310 +#define SYSMGR_SOC64_I2C_EMAC0_USEFPGA 0x1314 +#define SYSMGR_SOC64_I2C_EMAC1_USEFPGA 0x1318 +#define SYSMGR_SOC64_I2C_EMAC2_USEFPGA 0x131c +#define SYSMGR_SOC64_NAND_USEFPGA 0x1320 +#define SYSMGR_SOC64_SPIM0_USEFPGA 0x1328 +#define SYSMGR_SOC64_SPIM1_USEFPGA 0x132c +#define SYSMGR_SOC64_SPIS0_USEFPGA 0x1330 +#define SYSMGR_SOC64_SPIS1_USEFPGA 0x1334 +#define SYSMGR_SOC64_UART0_USEFPGA 0x1338 +#define SYSMGR_SOC64_UART1_USEFPGA 0x133c +#define SYSMGR_SOC64_MDIO0_USEFPGA 0x1340 +#define SYSMGR_SOC64_MDIO1_USEFPGA 0x1344 +#define SYSMGR_SOC64_MDIO2_USEFPGA 0x1348 +#define SYSMGR_SOC64_JTAG_USEFPGA 0x1350 +#define SYSMGR_SOC64_SDMMC_USEFPGA 0x1354 +#define SYSMGR_SOC64_HPS_OSC_CLK 0x1358 +#define SYSMGR_SOC64_IODELAY0 0x1400
+#define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC
+#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) +#define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) +#define SYSMGR_ECC_OCRAM_EN BIT(0) +#define SYSMGR_ECC_OCRAM_SERR BIT(3) +#define SYSMGR_ECC_OCRAM_DERR BIT(4) +#define SYSMGR_FPGAINTF_USEFPGA 0x1
+#define SYSMGR_FPGAINTF_NAND BIT(4) +#define SYSMGR_FPGAINTF_SDMMC BIT(8) +#define SYSMGR_FPGAINTF_SPIM0 BIT(16) +#define SYSMGR_FPGAINTF_SPIM1 BIT(24) +#define SYSMGR_FPGAINTF_EMAC0 BIT(0) +#define SYSMGR_FPGAINTF_EMAC1 BIT(8) +#define SYSMGR_FPGAINTF_EMAC2 BIT(16)
+#define SYSMGR_SDMMC_SMPLSEL_SHIFT 4 +#define SYSMGR_SDMMC_DRVSEL_SHIFT 0
+/* EMAC Group Bit definitions */ +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
+#define SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB 0 +#define SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB 2 +#define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x3
+#define SYSMGR_NOC_H2F_MSK 0x00000001 +#define SYSMGR_NOC_LWH2F_MSK 0x00000010 +#define SYSMGR_HMC_CLK_STATUS_MSK 0x00000001
+#define SYSMGR_DMA_IRQ_NS 0xFF000000 +#define SYSMGR_DMA_MGR_NS 0x00010000
+#define SYSMGR_DMAPERIPH_ALL_NS 0xFFFFFFFF
+#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#endif /* _SYSTEM_MANAGER_SOC64_H_ */ diff --git a/arch/arm/mach-socfpga/mailbox_s10.c b/arch/arm/mach-socfpga/mailbox_s10.c index 11b57361c7..ba81461f90 100644 --- a/arch/arm/mach-socfpga/mailbox_s10.c +++ b/arch/arm/mach-socfpga/mailbox_s10.c @@ -316,7 +316,7 @@ int mbox_qspi_open(void) /* We are getting QSPI ref clock and set into sysmgr boot register */ printf("QSPI: Reference clock at %d Hz\n", resp_buf[0]); writel(resp_buf[0],
socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD0);
socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); return 0;diff --git a/arch/arm/mach-socfpga/misc_s10.c b/arch/arm/mach-socfpga/misc_s10.c index 16fbf71599..ba95ab566b 100644 --- a/arch/arm/mach-socfpga/misc_s10.c +++ b/arch/arm/mach-socfpga/misc_s10.c @@ -65,8 +65,8 @@ static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode) else return -EINVAL;
clrsetbits_le32((unsigned long)(socfpga_sysmgr_base + SYSMGR_S10_EMAC0 +gmac_index),
clrsetbits_le32((unsigned long)(socfpga_sysmgr_base +SYSMGR_SOC64_EMAC0 + gmac_index), SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg); return 0;diff --git a/arch/arm/mach-socfpga/reset_manager_s10.c b/arch/arm/mach-socfpga/reset_manager_s10.c index bdc0f3ee6e..938999043e 100644 --- a/arch/arm/mach-socfpga/reset_manager_s10.c +++ b/arch/arm/mach-socfpga/reset_manager_s10.c @@ -56,29 +56,29 @@ void socfpga_bridges_reset(int enable) { if (enable) { /* clear idle request to all bridges */
setbits_le32(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_CLR,
setbits_le32(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0); /* Release all bridges from reset state */ clrbits_le32(socfpga_rstmgr_base + RSTMGR_SOC64_BRGMODRST, ~0); /* Poll until all idleack to 0 */
while (readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK))
while (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK)) ; } else { /* set idle request to all bridges */
writel(~0, socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEREQ_SET);
writel(~0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEREQ_SET); /* Enable the NOC timeout */
writel(1, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
writel(1, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT); /* Poll until all idleack to 1 */
while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLEACK) ^
while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLEACK) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ; /* Poll until all idlestatus to 1 */
while ((readl(socfpga_sysmgr_base + SYSMGR_S10_NOC_IDLESTATUS) ^
while ((readl(socfpga_sysmgr_base + SYSMGR_SOC64_NOC_IDLESTATUS) ^ (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK))) ;@@ -88,7 +88,7 @@ void socfpga_bridges_reset(int enable) RSTMGR_BRGMODRST_FPGA2SOC_MASK));
/* Disable NOC timeout */
writel(0, socfpga_sysmgr_base + SYSMGR_S10_NOC_TIMEOUT);
writel(0, socfpga_sysmgr_base + SYSMGR_SOC64_NOC_TIMEOUT); }}
diff --git a/arch/arm/mach-socfpga/spl_s10.c b/arch/arm/mach-socfpga/spl_s10.c index cdfbd06327..fabedba6d1 100644 --- a/arch/arm/mach-socfpga/spl_s10.c +++ b/arch/arm/mach-socfpga/spl_s10.c @@ -53,7 +53,7 @@ void board_init_f(ulong dummy) #ifdef CONFIG_HW_WATCHDOG /* Ensure watchdog is paused when debugging is happening */ writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_sysmgr_base + SYSMGR_S10_WDDBG);
socfpga_sysmgr_base + SYSMGR_SOC64_WDDBG); /* Enable watchdog before initializing the HW */ socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);diff --git a/arch/arm/mach-socfpga/system_manager_s10.c b/arch/arm/mach-socfpga/system_manager_s10.c index c046bb17c9..0da9431517 100644 --- a/arch/arm/mach-socfpga/system_manager_s10.c +++ b/arch/arm/mach-socfpga/system_manager_s10.c @@ -29,31 +29,31 @@ void populate_sysmgr_fpgaintf_module(void) u32 handoff_val = 0;
/* Enable the signal for those HPS peripherals that use FPGA. */
if (readl(socfpga_sysmgr_base + SYSMGR_S10_NAND_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_NAND_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_NAND;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_SDMMC_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SDMMC_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SDMMC;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM0_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM0_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM0;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_SPIM1_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_SPIM1_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_SPIM1;
writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN2);
writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN2); handoff_val = 0;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC0;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC1_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC1_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC1;
if (readl(socfpga_sysmgr_base + SYSMGR_S10_EMAC2_USEFPGA) ==
if (readl(socfpga_sysmgr_base + SYSMGR_SOC64_EMAC2_USEFPGA) == SYSMGR_FPGAINTF_USEFPGA) handoff_val |= SYSMGR_FPGAINTF_EMAC2;
writel(handoff_val, socfpga_sysmgr_base + SYSMGR_S10_FPGAINTF_EN3);
writel(handoff_val, socfpga_sysmgr_base + SYSMGR_SOC64_FPGAINTF_EN3);}
/* @@ -69,7 +69,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] +
(u8 *)socfpga_sysmgr_base + SYSMGR_S10_PINSEL0);
(u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_PINSEL0); } /* setup the pin ctrl */@@ -77,7 +77,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] +
(u8 *)socfpga_sysmgr_base + SYSMGR_S10_IOCTRL0);
(u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IOCTRL0); } /* setup the fpga use */@@ -85,7 +85,7 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] +
(u8 *)socfpga_sysmgr_base + SYSMGR_S10_EMAC0_USEFPGA);
(u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_EMAC0_USEFPGA); } /* setup the IO delay */@@ -93,6 +93,6 @@ void populate_sysmgr_pinmux(void) for (i = 0; i < len; i = i + 2) { writel(sys_mgr_table_u32[i + 1], sys_mgr_table_u32[i] +
(u8 *)socfpga_sysmgr_base + SYSMGR_S10_IODELAY0);
(u8 *)socfpga_sysmgr_base + SYSMGR_SOC64_IODELAY0); }} diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index c9570fea38..b002f38215 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -35,9 +35,9 @@ const unsigned int cm_get_osc_clk_hz(void) #ifdef CONFIG_SPL_BUILD u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);#endif
return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD1);
return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);}
const unsigned int cm_get_intosc_clk_hz(void) @@ -50,7 +50,7 @@ const unsigned int cm_get_fpga_clk_hz(void) #ifdef CONFIG_SPL_BUILD u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
writel(clock, socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);#endif
return readl(socfpga_sysmgr_base + SYSMGR_S10_BOOT_SCRATCH_COLD2);
return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);} diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 8948c31f45..9578aa743d 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -148,7 +148,7 @@ static int emif_reset(struct altera_sdram_platdata *plat) static int poll_hmc_clock_status(void) { return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +
SYSMGR_S10_HMC_CLK),
SYSMGR_SOC64_HMC_CLK), SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);}
-- 2.19.0
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v3: - Change include filename to system_manager_soc64.h. - Move to use defines instead of struct.
v2: - Include system_manager_s10_agilex_common.h in system_manager_agilex.h --- arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++ .../mach-socfpga/include/mach/system_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 803305eb35..a4a6bbf600 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -10,6 +10,8 @@ extern phys_addr_t socfpga_sysmgr_base;
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/system_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/system_manager_agilex.h> #else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h new file mode 100644 index 0000000000..cb284114be --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _SYSTEM_MANAGER_AGILEX_ +#define _SYSTEM_MANAGER_AGILEX_ + +#include <asm/arch/system_manager_soc64.h> + +#endif /* _SYSTEM_MANAGER_AGILEX_ */
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Change include filename to system_manager_soc64.h.
- Move to use defines instead of struct.
v2:
- Include system_manager_s10_agilex_common.h in system_manager_agilex.h
arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++ .../mach-socfpga/include/mach/system_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 803305eb35..a4a6bbf600 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -10,6 +10,8 @@ extern phys_addr_t socfpga_sysmgr_base;
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/system_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/system_manager_agilex.h>
Same as before: why do we need this nearly empty file?
Regards, Simon
#else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h new file mode 100644 index 0000000000..cb284114be --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _SYSTEM_MANAGER_AGILEX_ +#define _SYSTEM_MANAGER_AGILEX_
+#include <asm/arch/system_manager_soc64.h>
+#endif /* _SYSTEM_MANAGER_AGILEX_ */
2.19.0
On Wed, Oct 2, 2019 at 4:27 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add system manager support for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v3:
- Change include filename to system_manager_soc64.h.
- Move to use defines instead of struct.
v2:
- Include system_manager_s10_agilex_common.h in system_manager_agilex.h
arch/arm/mach-socfpga/include/mach/system_manager.h | 2 ++ .../mach-socfpga/include/mach/system_manager_agilex.h | 11 +++++++++++ 2 files changed, 13 insertions(+) create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager.h b/arch/arm/mach-socfpga/include/mach/system_manager.h index 803305eb35..a4a6bbf600 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager.h @@ -10,6 +10,8 @@ extern phys_addr_t socfpga_sysmgr_base;
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/system_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/system_manager_agilex.h>
Same as before: why do we need this nearly empty file?
Noted. Will change this.
Regards Ley Foon
#else #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUX BIT(0) #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO BIT(1) diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h new file mode 100644 index 0000000000..cb284114be --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/system_manager_agilex.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _SYSTEM_MANAGER_AGILEX_ +#define _SYSTEM_MANAGER_AGILEX_
+#include <asm/arch/system_manager_soc64.h>
+#endif /* _SYSTEM_MANAGER_AGILEX_ */
2.19.0
Move Stratix10 and Agilex clock manager common code to new header file.
Fixed CLKMGR_INTOSC_HZ to 400MHz instead of 460MHz.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- .../include/mach/clock_manager_s10.h | 16 +++---------- .../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++ 2 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index fa0ba26f09..223940ba0c 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 * - * Copyright (C) 2016-2018 Intel Corporation <www.intel.com> + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> * */
@@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(void); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); -const unsigned int cm_get_intosc_clk_hz(void); -const unsigned int cm_get_fpga_clk_hz(void); - -#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000 - -/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void);
struct cm_config { /* main group */ @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#include <asm/arch/clock_manager_soc64.h> + #endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h new file mode 100644 index 0000000000..1a134b89ba --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * + */ + +#ifndef _CLOCK_MANAGER_SOC64_ +#define _CLOCK_MANAGER_SOC64_ + +const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void); + +#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 400000000 +#define CLKMGR_FPGA_CLK_HZ 50000000 + +/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void); + +#endif /* _CLOCK_MANAGER_SOC64_ */
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Move Stratix10 and Agilex clock manager common code to new header file.
Fixed CLKMGR_INTOSC_HZ to 400MHz instead of 460MHz.
Separate patch for a fix vs. moving code, please!
Regards, Simon
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
.../include/mach/clock_manager_s10.h | 16 +++---------- .../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++ 2 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index fa0ba26f09..223940ba0c 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
@@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(void); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); -const unsigned int cm_get_intosc_clk_hz(void); -const unsigned int cm_get_fpga_clk_hz(void);
-#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000
-/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void);
struct cm_config { /* main group */ @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#include <asm/arch/clock_manager_soc64.h>
#endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h new file mode 100644 index 0000000000..1a134b89ba --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CLOCK_MANAGER_SOC64_ +#define _CLOCK_MANAGER_SOC64_
+const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void);
+#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 400000000 +#define CLKMGR_FPGA_CLK_HZ 50000000
+/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void);
+#endif /* _CLOCK_MANAGER_SOC64_ */
2.19.0
On Wed, Oct 2, 2019 at 4:28 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Move Stratix10 and Agilex clock manager common code to new header file.
Fixed CLKMGR_INTOSC_HZ to 400MHz instead of 460MHz.
Separate patch for a fix vs. moving code, please!
Okay.
Regards Ley Foon
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
.../include/mach/clock_manager_s10.h | 16 +++---------- .../include/mach/clock_manager_soc64.h | 23 +++++++++++++++++++ 2 files changed, 26 insertions(+), 13 deletions(-) create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h index fa0ba26f09..223940ba0c 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
*/
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
@@ -14,18 +14,6 @@ unsigned int cm_get_l4_sp_clk_hz(void); unsigned int cm_get_mmc_controller_clk_hz(void); unsigned int cm_get_qspi_controller_clk_hz(void); unsigned int cm_get_spi_controller_clk_hz(void); -const unsigned int cm_get_osc_clk_hz(void); -const unsigned int cm_get_f2s_per_ref_clk_hz(void); -const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); -const unsigned int cm_get_intosc_clk_hz(void); -const unsigned int cm_get_fpga_clk_hz(void);
-#define CLKMGR_EOSC1_HZ 25000000 -#define CLKMGR_INTOSC_HZ 460000000 -#define CLKMGR_FPGA_CLK_HZ 50000000
-/* Clock configuration accessors */ -const struct cm_config * const cm_get_default_config(void);
struct cm_config { /* main group */ @@ -186,4 +174,6 @@ void cm_basic_init(const struct cm_config * const cfg);
#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK 0x00000020
+#include <asm/arch/clock_manager_soc64.h>
#endif /* _CLOCK_MANAGER_S10_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h new file mode 100644 index 0000000000..1a134b89ba --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CLOCK_MANAGER_SOC64_ +#define _CLOCK_MANAGER_SOC64_
+const unsigned int cm_get_osc_clk_hz(void); +const unsigned int cm_get_f2s_per_ref_clk_hz(void); +const unsigned int cm_get_f2s_sdr_ref_clk_hz(void); +const unsigned int cm_get_intosc_clk_hz(void); +const unsigned int cm_get_fpga_clk_hz(void);
+#define CLKMGR_EOSC1_HZ 25000000 +#define CLKMGR_INTOSC_HZ 400000000 +#define CLKMGR_FPGA_CLK_HZ 50000000
+/* Clock configuration accessors */ +const struct cm_config * const cm_get_default_config(void);
+#endif /* _CLOCK_MANAGER_SOC64_ */
2.19.0
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions.
Rename stratix10-clock.h to socfpga-soc64-clock.h.
stratix10-clock.h is from Linux commit ID 89727949ea1e.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Get address from DT.
v3: - Fixed clear PLL's lostlock bypass mode to ensure the clock manager provide glitchless clock to downstream logic - Changed CM_REG_CLRBITS(), CM_REG_SETBITS() and CM_REG_CLRSETBITS() macros argument ordering, to match with clrbits_le32, setbits_le32 and clrsetbits_le32. - Rename stratix10-clock.h to socfpga-soc64-clock.h. - Convert struct to defines and move defines to clk-agilex.h
v2: - Convert Clock driver to DM --- arch/arm/mach-socfpga/misc.c | 4 + drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ .../dt-bindings/clock/socfpga-soc64-clock.h | 84 +++ 5 files changed, 905 insertions(+) create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 include/dt-bindings/clock/socfpga-soc64-clock.h
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dffd1b2e41..f540606569 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -240,7 +240,11 @@ void socfpga_get_manager_addr(void) if (!socfpga_sysmgr_base) hang();
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX + socfpga_clkmgr_base = socfpga_get_base_addr("intel,agilex-clkmgr"); +#else socfpga_clkmgr_base = socfpga_get_base_addr("altr,clk-mgr"); +#endif if (!socfpga_clkmgr_base) hang(); } diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index a3ae8b24b0..96215ad5c4 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2018 Marek Vasut marex@denx.de #
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c new file mode 100644 index 0000000000..f796016d73 --- /dev/null +++ b/drivers/clk/altera/clk-agilex.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <common.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <dt-bindings/clock/socfpga-soc64-clock.h> + +#include <asm/arch/clock_manager.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct socfpga_clk_platdata { + void __iomem *regs; +}; + +/* + * function to write the bypass register which requires a poll of the + * busy bit + */ +static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); + cm_wait_for_fsm(); +} + +static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); + cm_wait_for_fsm(); +} + +/* function to write the ctrl register which requires a poll of the busy bit */ +static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val) +{ + CM_REG_WRITEL(plat, val, CLKMGR_CTRL); + cm_wait_for_fsm(); +} + +#define MEMBUS_MAINPLL 0 +#define MEMBUS_PERPLL 1 +#define MEMBUS_TIMEOUT 1000 +#define MEMBUS_ADDR_CLKSLICE 0x27 +#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80 + +static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll, + int timeout) +{ + int cnt = 0; + u32 req_status; + + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + + while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) { + if (pll == MEMBUS_MAINPLL) + req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM); + else + req_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM); + cnt++; + } + + if (cnt >= timeout) + return -ETIMEDOUT; + + return 0; +} + +static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll, + u32 addr_offset, u32 wdat, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK | + (wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr); + + return membus_wait_for_req(plat, pll, timeout); +} + +static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll, + u32 addr_offset, u32 *rdata, int timeout) +{ + u32 addr; + u32 val; + + addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK); + + val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr); + + if (pll == MEMBUS_MAINPLL) + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM); + else + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM); + + *rdata = 0; + + if (membus_wait_for_req(plat, pll, timeout)) + return -ETIMEDOUT; + + if (pll == MEMBUS_MAINPLL) + *rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT); + else + *rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT); + + debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr); + + return 0; +} + +static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) +{ + u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib; + + mdiv = pllm & CLKMGR_PLLM_MDIV_MASK; + arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET; + refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_REFCLKDIV_OFFSET; + mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv)); + if (!mscnt) + mscnt = 1; + hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) - + CLKMGR_VCOCALIB_HSCNT_CONST; + vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | + ((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) & + CLKMGR_VCOCALIB_MSCNT_MASK); + + /* Dump all the pll calibration settings for debug purposes */ + debug("mdiv : %d\n", mdiv); + debug("arefclkdiv : %d\n", arefclkdiv); + debug("drefclkdiv : %d\n", drefclkdiv); + debug("refclkdiv : %d\n", refclkdiv); + debug("mscnt : %d\n", mscnt); + debug("hscnt : %d\n", hscnt); + debug("vcocalib : 0x%08x\n", vcocalib); + + return vcocalib; +} + +/* + * Setup clocks while making no assumptions about previous state of the clocks. + */ +static void clk_basic_init(struct udevice *dev, + const struct cm_config * const cfg) +{ + struct socfpga_clk_platdata *plat = dev_get_platdata(dev); + u32 vcocalib; + u32 rdata; + + if (!cfg) + return; + + /* Put both PLLs in bypass */ + clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL); + clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL); + + /* Put both PLLs in Reset and Power Down */ + CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* setup main PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob); + CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM); + CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK); + CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV); + + /* setup peripheral PLL dividers where calculate the vcocalib value */ + vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob); + CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK, + CLKMGR_PERPLL_PLLGLOB); + CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK); + CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB); + CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0); + CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1); + CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2); + CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3); + CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM); + CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL); + CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV); + + /* Take both PLL out of reset and power up */ + CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK); + + /* Membus programming to set mainpll and perripll to + * source synchronous mode + */ + membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata, + MEMBUS_TIMEOUT); + membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, + (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN), + MEMBUS_TIMEOUT); + membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata, + MEMBUS_TIMEOUT); + membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, + (rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN), + MEMBUS_TIMEOUT); + + cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK); + + /* Configure ping pong counters in altera group */ + CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR); + CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR); + CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR); + CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR); + CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR); + CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR); + CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR); + CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR); + + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK); + CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK); + + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_MAINPLL_PLLGLOB); + CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) | + CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK, + CLKMGR_PERPLL_PLLGLOB); + + /* Take all PLLs out of bypass */ + clk_write_bypass_mainpll(plat, 0); + clk_write_bypass_perpll(plat, 0); + + /* Clear the loss of lock bits (write 1 to clear) */ + CM_REG_CLRBITS(plat, CLKMGR_INTRCLR, + CLKMGR_INTER_PERPLLLOST_MASK | + CLKMGR_INTER_MAINPLLLOST_MASK); + + /* Take all ping pong counters out of reset */ + CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST, + CLKMGR_ALT_EXTCNTRST_ALLCNTRST); + + /* Out of boot mode */ + clk_write_ctrl(plat, + CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); +} + +static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat, + u32 pllglob_reg, u32 pllm_reg) +{ + u64 fref, arefdiv, mdiv, reg, vco; + + reg = CM_REG_READL(plat, pllglob_reg); + + fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET; + + switch (fref) { + case CLKMGR_VCO_PSRC_EOSC1: + fref = cm_get_osc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_INTOSC: + fref = cm_get_intosc_clk_hz(); + break; + case CLKMGR_VCO_PSRC_F2S: + fref = cm_get_fpga_clk_hz(); + break; + } + + arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >> + CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET; + + mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK; + + vco = fref / arefdiv; + vco = vco * mdiv; + + return vco; +} + +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB, + CLKMGR_MAINPLL_PLLM); +} + +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat) +{ + return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB, + CLKMGR_PERPLL_PLLM); +} + +static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg) +{ + u32 clksrc = CM_REG_READL(plat, reg); + + return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET; +} + +static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg, + u32 main_reg, u32 per_reg) +{ + u64 clock; + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg); + + switch (clklsrc) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, main_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + clock /= (CM_REG_READL(plat, per_reg) & + CLKMGR_CLKCNT_MSK); + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + default: + return 0; + } + + return clock; +} + +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat) +{ + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK, + CLKMGR_MAINPLL_PLLC0, + CLKMGR_PERPLL_PLLC0); + + clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) & + CLKMGR_CLKCNT_MSK); + + return clock; +} + +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat) +{ + return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK, + CLKMGR_MAINPLL_PLLC1, + CLKMGR_PERPLL_PLLC1); +} + +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MAIN_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat) +{ + u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR, + CLKMGR_MAINPLL_PLLC3, + CLKMGR_PERPLL_PLLC3); + + clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) & + CLKMGR_CLKCNT_MSK); + + return clock / 4; +} + +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4SPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat) +{ + u64 clock = clk_get_l3_main_clk_hz(plat); + + clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >> + CLKMGR_NOCDIV_L4MPCLK_OFFSET) & + CLKMGR_NOCDIV_DIVIDER_MASK); + + return clock; +} + +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat) +{ + if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) + return clk_get_l3_main_clk_hz(plat) / 2; + + return clk_get_l3_main_clk_hz(plat) / 4; +} + +static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id) +{ + bool emacsel_a; + u32 ctl; + u32 ctr_reg; + u32 clock; + u32 div; + u32 reg; + + /* Get EMAC clock source */ + ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL); + if (emac_id == SOCFPGA_SOC64_EMAC0_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK; + else if (emac_id == SOCFPGA_SOC64_EMAC1_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK; + else if (emac_id == SOCFPGA_SOC64_EMAC2_CLK) + ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) & + CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK; + else + return 0; + + if (ctl) { + /* EMAC B source */ + emacsel_a = false; + ctr_reg = CLKMGR_ALTR_EMACBCTR; + } else { + /* EMAC A source */ + emacsel_a = true; + ctr_reg = CLKMGR_ALTR_EMACACTR; + } + + reg = CM_REG_READL(plat, ctr_reg); + clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK) + >> CLKMGR_ALT_EMACCTR_SRC_OFFSET; + div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK) + >> CLKMGR_ALT_EMACCTR_CNT_OFFSET; + + switch (clock) { + case CLKMGR_CLKSRC_MAIN: + clock = clk_get_main_vco_clk_hz(plat); + if (emacsel_a) { + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) & + CLKMGR_CLKCNT_MSK); + } else { + clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) & + CLKMGR_CLKCNT_MSK); + } + break; + + case CLKMGR_CLKSRC_PER: + clock = clk_get_per_vco_clk_hz(plat); + if (emacsel_a) { + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) & + CLKMGR_CLKCNT_MSK); + } else { + clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) & + CLKMGR_CLKCNT_MSK); + } + break; + + case CLKMGR_CLKSRC_OSC1: + clock = cm_get_osc_clk_hz(); + break; + + case CLKMGR_CLKSRC_INTOSC: + clock = cm_get_intosc_clk_hz(); + break; + + case CLKMGR_CLKSRC_FPGA: + clock = cm_get_fpga_clk_hz(); + break; + } + + clock /= 1 + div; + + return clock; +} + +static ulong socfpga_clk_get_rate(struct clk *clk) +{ + struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev); + + switch (clk->id) { + case SOCFPGA_SOC64_MPU_CLK: + return clk_get_mpu_clk_hz(plat); + case SOCFPGA_SOC64_L4_MAIN_CLK: + return clk_get_l4_main_clk_hz(plat); + case SOCFPGA_SOC64_L4_SYS_FREE_CLK: + return clk_get_l4_sys_free_clk_hz(plat); + case SOCFPGA_SOC64_L4_MP_CLK: + return clk_get_l4_mp_clk_hz(plat); + case SOCFPGA_SOC64_L4_SP_CLK: + return clk_get_l4_sp_clk_hz(plat); + case SOCFPGA_SOC64_SDMMC_CLK: + return clk_get_sdmmc_clk_hz(plat); + case SOCFPGA_SOC64_EMAC0_CLK: + case SOCFPGA_SOC64_EMAC1_CLK: + case SOCFPGA_SOC64_EMAC2_CLK: + return clk_get_emac_clk_hz(plat, clk->id); + case SOCFPGA_SOC64_USB_CLK: + return clk_get_l4_mp_clk_hz(plat); + default: + return -ENXIO; + } +} + +static int socfpga_clk_probe(struct udevice *dev) +{ + const struct cm_config *cm_default_cfg = cm_get_default_config(); + + clk_basic_init(dev, cm_default_cfg); + + return 0; +} + +static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) +{ + struct socfpga_clk_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr; + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->regs = (void __iomem *)addr; + + return 0; +} + +static struct clk_ops socfpga_clk_ops = { + .get_rate = socfpga_clk_get_rate, +}; + +static const struct udevice_id socfpga_clk_match[] = { + { .compatible = "intel,agilex-clkmgr" }, + {} +}; + +U_BOOT_DRIVER(socfpga_agilex_clk) = { + .name = "clk-agilex", + .id = UCLASS_CLK, + .of_match = socfpga_clk_match, + .ops = &socfpga_clk_ops, + .probe = socfpga_clk_probe, + .ofdata_to_platdata = socfpga_clk_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata), +}; diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h new file mode 100644 index 0000000000..3cf2afa006 --- /dev/null +++ b/drivers/clk/altera/clk-agilex.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _CLK_AGILEX_ +#define _CLK_AGILEX_ + +#define CM_REG_READL(plat, reg) \ + readl(plat->regs + (reg)) + +#define CM_REG_WRITEL(plat, data, reg) \ + writel(data, plat->regs + (reg)) + +#define CM_REG_CLRBITS(plat, reg, clear) \ + clrbits_le32(plat->regs + (reg), (clear)) + +#define CM_REG_SETBITS(plat, reg, set) \ + setbits_le32(plat->regs + (reg), (set)) + +struct cm_config { + /* main group */ + u32 main_pll_mpuclk; + u32 main_pll_nocclk; + u32 main_pll_nocdiv; + u32 main_pll_pllglob; + u32 main_pll_fdbck; + u32 main_pll_pllc0; + u32 main_pll_pllc1; + u32 main_pll_pllc2; + u32 main_pll_pllc3; + u32 main_pll_pllm; + + /* peripheral group */ + u32 per_pll_emacctl; + u32 per_pll_gpiodiv; + u32 per_pll_pllglob; + u32 per_pll_fdbck; + u32 per_pll_pllc0; + u32 per_pll_pllc1; + u32 per_pll_pllc2; + u32 per_pll_pllc3; + u32 per_pll_pllm; + + /* altera group */ + u32 alt_emacactr; + u32 alt_emacbctr; + u32 alt_emacptpctr; + u32 alt_gpiodbctr; + u32 alt_sdmmcctr; + u32 alt_s2fuser0ctr; + u32 alt_s2fuser1ctr; + u32 alt_psirefctr; + + /* incoming clock */ + u32 hps_osc_clk_hz; + u32 fpga_clk_hz; + u32 spare[3]; +}; + +/* Clock Manager registers */ +#define CLKMGR_CTRL 0 +#define CLKMGR_STAT 4 +#define CLKMGR_TESTIOCTRL 8 +#define CLKMGR_INTRGEN 0x0c +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20 + +/* Clock Manager Main PPL group registers */ +#define CLKMGR_MAINPLL_EN 0x24 +#define CLKMGR_MAINPLL_ENS 0x28 +#define CLKMGR_MAINPLL_ENR 0x2c +#define CLKMGR_MAINPLL_BYPASS 0x30 +#define CLKMGR_MAINPLL_BYPASSS 0x34 +#define CLKMGR_MAINPLL_BYPASSR 0x38 +#define CLKMGR_MAINPLL_MPUCLK 0x3c +#define CLKMGR_MAINPLL_NOCCLK 0x40 +#define CLKMGR_MAINPLL_NOCDIV 0x44 +#define CLKMGR_MAINPLL_PLLGLOB 0x48 +#define CLKMGR_MAINPLL_FDBCK 0x4c +#define CLKMGR_MAINPLL_MEM 0x50 +#define CLKMGR_MAINPLL_MEMSTAT 0x54 +#define CLKMGR_MAINPLL_PLLC0 0x58 +#define CLKMGR_MAINPLL_PLLC1 0x5c +#define CLKMGR_MAINPLL_VCOCALIB 0x60 +#define CLKMGR_MAINPLL_PLLC2 0x64 +#define CLKMGR_MAINPLL_PLLC3 0x68 +#define CLKMGR_MAINPLL_PLLM 0x6c +#define CLKMGR_MAINPLL_FHOP 0x70 +#define CLKMGR_MAINPLL_SSC 0x74 +#define CLKMGR_MAINPLL_LOSTLOCK 0x78 + +/* Clock Manager Peripheral PPL group registers */ +#define CLKMGR_PERPLL_EN 0x7c +#define CLKMGR_PERPLL_ENS 0x80 +#define CLKMGR_PERPLL_ENR 0x84 +#define CLKMGR_PERPLL_BYPASS 0x88 +#define CLKMGR_PERPLL_BYPASSS 0x8c +#define CLKMGR_PERPLL_BYPASSR 0x90 +#define CLKMGR_PERPLL_EMACCTL 0x94 +#define CLKMGR_PERPLL_GPIODIV 0x98 +#define CLKMGR_PERPLL_PLLGLOB 0x9c +#define CLKMGR_PERPLL_FDBCK 0xa0 +#define CLKMGR_PERPLL_MEM 0xa4 +#define CLKMGR_PERPLL_MEMSTAT 0xa8 +#define CLKMGR_PERPLL_PLLC0 0xac +#define CLKMGR_PERPLL_PLLC1 0xb0 +#define CLKMGR_PERPLL_VCOCALIB 0xb4 +#define CLKMGR_PERPLL_PLLC2 0xb8 +#define CLKMGR_PERPLL_PLLC3 0xbc +#define CLKMGR_PERPLL_PLLM 0xc0 +#define CLKMGR_PERPLL_FHOP 0xc4 +#define CLKMGR_PERPLL_SSC 0xc8 +#define CLKMGR_PERPLL_LOSTLOCK 0xcc + +/* Clock Manager Altera group registers */ +#define CLKMGR_ALTR_JTAG 0xd0 +#define CLKMGR_ALTR_EMACACTR 0xd4 +#define CLKMGR_ALTR_EMACBCTR 0xd8 +#define CLKMGR_ALTR_EMACPTPCTR 0xdc +#define CLKMGR_ALTR_GPIODBCTR 0xe0 +#define CLKMGR_ALTR_SDMMCCTR 0xe4 +#define CLKMGR_ALTR_S2FUSER0CTR 0xe8 +#define CLKMGR_ALTR_S2FUSER1CTR 0xec +#define CLKMGR_ALTR_PSIREFCTR 0xf0 +#define CLKMGR_ALTR_EXTCNTRST 0xf4 + +#define CLKMGR_CTRL_BOOTMODE BIT(0) + +#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_MAIN_TRANS BIT(9) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16) +#define CLKMGR_STAT_PERF_TRANS BIT(17) +#define CLKMGR_STAT_BOOTMODE BIT(24) +#define CLKMGR_STAT_BOOTCLKSRC BIT(25) + +#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \ + (CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED) + +#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008 + +#define CLKMGR_CLKSRC_MASK GENMASK(18, 16) +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0) + +#define CLKMGR_BYPASS_MAINPLL_ALL 0x7 +#define CLKMGR_BYPASS_PERPLL_ALL 0x7f + +#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3 + +#define CLKMGR_PLLGLOB_PD_MASK BIT(0) +#define CLKMGR_PLLGLOB_RST_MASK BIT(1) +#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12) +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8) +#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27) +#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12 +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29) + +#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2 + +#define CLKMGR_MEM_REQ_SET_MSK BIT(24) +#define CLKMGR_MEM_WR_SET_MSK BIT(25) +#define CLKMGR_MEM_ERR_MSK BIT(26) +#define CLKMGR_MEM_WDAT_LSB_OFFSET 16 +#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0) +#define CLKMGR_MEM_ADDR_START 0x00004000 + +#define CLKMGR_PLLCX_EN_SET_MSK BIT(27) +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28) + +#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) +#define CLKMGR_VCOCALIB_MSCNT_CONST 100 +#define CLKMGR_VCOCALIB_HSCNT_CONST 4 + +#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0) + +#define CLKMGR_LOSTLOCK_SET_MASK BIT(0) + +#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28) + +#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16 +#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16) +#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0 +#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0) + +#define CLKMGR_ALT_EXTCNTRST_EMACACNTRST BIT(0) +#define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST BIT(1) +#define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST BIT(2) +#define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST BIT(3) +#define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST BIT(4) +#define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST BIT(5) +#define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST BIT(6) +#define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST BIT(7) +#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST \ + (CLKMGR_ALT_EXTCNTRST_EMACACNTRST | \ + CLKMGR_ALT_EXTCNTRST_EMACBCNTRST | \ + CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST | \ + CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST | \ + CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST | \ + CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST | \ + CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST | \ + CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST) +#endif /* _CLK_AGILEX_ */ diff --git a/include/dt-bindings/clock/socfpga-soc64-clock.h b/include/dt-bindings/clock/socfpga-soc64-clock.h new file mode 100644 index 0000000000..6a05f63676 --- /dev/null +++ b/include/dt-bindings/clock/socfpga-soc64-clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2019, Intel Corporation + */ + +#ifndef __SOCFPGA_SOC64_CLOCK_H +#define __SOCFPGA_SOC64_CLOCK_H + +/* fixed rate clocks */ +#define SOCFPGA_SOC64_OSC1 0 +#define SOCFPGA_SOC64_CB_INTOSC_HS_DIV2_CLK 1 +#define SOCFPGA_SOC64_CB_INTOSC_LS_CLK 2 +#define SOCFPGA_SOC64_F2S_FREE_CLK 3 + +/* fixed factor clocks */ +#define SOCFPGA_SOC64_L4_SYS_FREE_CLK 4 +#define SOCFPGA_SOC64_MPU_PERIPH_CLK 5 +#define SOCFPGA_SOC64_MPU_L2RAM_CLK 6 +#define SOCFPGA_SOC64_SDMMC_CIU_CLK 7 + +/* PLL clocks */ +#define SOCFPGA_SOC64_MAIN_PLL_CLK 8 +#define SOCFPGA_SOC64_PERIPH_PLL_CLK 9 +#define SOCFPGA_SOC64_BOOT_CLK 10 + +/* Periph clocks */ +#define SOCFPGA_SOC64_MAIN_MPU_BASE_CLK 11 +#define SOCFPGA_SOC64_MAIN_NOC_BASE_CLK 12 +#define SOCFPGA_SOC64_MAIN_EMACA_CLK 13 +#define SOCFPGA_SOC64_MAIN_EMACB_CLK 14 +#define SOCFPGA_SOC64_MAIN_EMAC_PTP_CLK 15 +#define SOCFPGA_SOC64_MAIN_GPIO_DB_CLK 16 +#define SOCFPGA_SOC64_MAIN_SDMMC_CLK 17 +#define SOCFPGA_SOC64_MAIN_S2F_USR0_CLK 18 +#define SOCFPGA_SOC64_MAIN_S2F_USR1_CLK 19 +#define SOCFPGA_SOC64_MAIN_PSI_REF_CLK 20 + +#define SOCFPGA_SOC64_PERI_MPU_BASE_CLK 21 +#define SOCFPGA_SOC64_PERI_NOC_BASE_CLK 22 +#define SOCFPGA_SOC64_PERI_EMACA_CLK 23 +#define SOCFPGA_SOC64_PERI_EMACB_CLK 24 +#define SOCFPGA_SOC64_PERI_EMAC_PTP_CLK 25 +#define SOCFPGA_SOC64_PERI_GPIO_DB_CLK 26 +#define SOCFPGA_SOC64_PERI_SDMMC_CLK 27 +#define SOCFPGA_SOC64_PERI_S2F_USR0_CLK 28 +#define SOCFPGA_SOC64_PERI_S2F_USR1_CLK 29 +#define SOCFPGA_SOC64_PERI_PSI_REF_CLK 30 + +#define SOCFPGA_SOC64_MPU_FREE_CLK 31 +#define SOCFPGA_SOC64_NOC_FREE_CLK 32 +#define SOCFPGA_SOC64_S2F_USR0_CLK 33 +#define SOCFPGA_SOC64_NOC_CLK 34 +#define SOCFPGA_SOC64_EMAC_A_FREE_CLK 35 +#define SOCFPGA_SOC64_EMAC_B_FREE_CLK 36 +#define SOCFPGA_SOC64_EMAC_PTP_FREE_CLK 37 +#define SOCFPGA_SOC64_GPIO_DB_FREE_CLK 38 +#define SOCFPGA_SOC64_SDMMC_FREE_CLK 39 +#define SOCFPGA_SOC64_S2F_USER1_FREE_CLK 40 +#define SOCFPGA_SOC64_PSI_REF_FREE_CLK 41 + +/* Gate clocks */ +#define SOCFPGA_SOC64_MPU_CLK 42 +#define SOCFPGA_SOC64_L4_MAIN_CLK 43 +#define SOCFPGA_SOC64_L4_MP_CLK 44 +#define SOCFPGA_SOC64_L4_SP_CLK 45 +#define SOCFPGA_SOC64_CS_AT_CLK 46 +#define SOCFPGA_SOC64_CS_TRACE_CLK 47 +#define SOCFPGA_SOC64_CS_PDBG_CLK 48 +#define SOCFPGA_SOC64_CS_TIMER_CLK 49 +#define SOCFPGA_SOC64_S2F_USER0_CLK 50 +#define SOCFPGA_SOC64_S2F_USER1_CLK 51 +#define SOCFPGA_SOC64_EMAC0_CLK 52 +#define SOCFPGA_SOC64_EMAC1_CLK 53 +#define SOCFPGA_SOC64_EMAC2_CLK 54 +#define SOCFPGA_SOC64_EMAC_PTP_CLK 55 +#define SOCFPGA_SOC64_GPIO_DB_CLK 56 +#define SOCFPGA_SOC64_SDMMC_CLK 57 +#define SOCFPGA_SOC64_PSI_REF_CLK 58 +#define SOCFPGA_SOC64_USB_CLK 59 +#define SOCFPGA_SOC64_SPI_M_CLK 60 +#define SOCFPGA_SOC64_NAND_CLK 61 +#define SOCFPGA_SOC64_NUM_CLKS 62 + +#endif /* __SOCFPGA_SOC64_CLOCK_H */
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add clock manager driver for Agilex. Provides clock initialization and get_rate functions.
Rename stratix10-clock.h to socfpga-soc64-clock.h.
stratix10-clock.h is from Linux commit ID 89727949ea1e.
Signed-off-by: Chee Hong Ang chee.hong.ang@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
I would have preferred the handoff data to come from devicetree...
Anyway: Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Get address from DT.
v3:
- Fixed clear PLL's lostlock bypass mode to ensure the clock manager provide glitchless clock
to downstream logic
- Changed CM_REG_CLRBITS(), CM_REG_SETBITS() and CM_REG_CLRSETBITS() macros
argument ordering, to match with clrbits_le32, setbits_le32 and clrsetbits_le32.
- Rename stratix10-clock.h to socfpga-soc64-clock.h.
- Convert struct to defines and move defines to clk-agilex.h
v2:
- Convert Clock driver to DM
arch/arm/mach-socfpga/misc.c | 4 + drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ .../dt-bindings/clock/socfpga-soc64-clock.h | 84 +++ 5 files changed, 905 insertions(+) create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 include/dt-bindings/clock/socfpga-soc64-clock.h
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index dffd1b2e41..f540606569 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -240,7 +240,11 @@ void socfpga_get_manager_addr(void) if (!socfpga_sysmgr_base) hang();
+#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
socfpga_clkmgr_base = socfpga_get_base_addr("intel,agilex-clkmgr");+#else socfpga_clkmgr_base = socfpga_get_base_addr("altr,clk-mgr"); +#endif if (!socfpga_clkmgr_base) hang(); } diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index a3ae8b24b0..96215ad5c4 100644 --- a/drivers/clk/altera/Makefile +++ b/drivers/clk/altera/Makefile @@ -3,4 +3,5 @@ # Copyright (C) 2018 Marek Vasut marex@denx.de #
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c new file mode 100644 index 0000000000..f796016d73 --- /dev/null +++ b/drivers/clk/altera/clk-agilex.c @@ -0,0 +1,579 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <asm/io.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dm/lists.h> +#include <dm/util.h> +#include <dt-bindings/clock/socfpga-soc64-clock.h>
+#include <asm/arch/clock_manager.h>
+DECLARE_GLOBAL_DATA_PTR;
+struct socfpga_clk_platdata {
void __iomem *regs;+};
+/*
- function to write the bypass register which requires a poll of the
- busy bit
- */
+static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val) +{
CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);cm_wait_for_fsm();+}
+static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val) +{
CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);cm_wait_for_fsm();+}
+/* function to write the ctrl register which requires a poll of the busy bit */ +static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val) +{
CM_REG_WRITEL(plat, val, CLKMGR_CTRL);cm_wait_for_fsm();+}
+#define MEMBUS_MAINPLL 0 +#define MEMBUS_PERPLL 1 +#define MEMBUS_TIMEOUT 1000 +#define MEMBUS_ADDR_CLKSLICE 0x27 +#define MEMBUS_CLKSLICE_SYNC_MODE_EN 0x80
+static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll,
int timeout)+{
int cnt = 0;u32 req_status;if (pll == MEMBUS_MAINPLL)req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);elsereq_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);while ((cnt < timeout) && (req_status & CLKMGR_MEM_REQ_SET_MSK)) {if (pll == MEMBUS_MAINPLL)req_status = CM_REG_READL(plat, CLKMGR_MAINPLL_MEM);elsereq_status = CM_REG_READL(plat, CLKMGR_PERPLL_MEM);cnt++;}if (cnt >= timeout)return -ETIMEDOUT;return 0;+}
+static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll,
u32 addr_offset, u32 wdat, int timeout)+{
u32 addr;u32 val;addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);val = (CLKMGR_MEM_REQ_SET_MSK | CLKMGR_MEM_WR_SET_MSK |(wdat << CLKMGR_MEM_WDAT_LSB_OFFSET) | addr);if (pll == MEMBUS_MAINPLL)CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);elseCM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);debug("MEMBUS: Write 0x%08x to addr = 0x%08x\n", wdat, addr);return membus_wait_for_req(plat, pll, timeout);+}
+static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll,
u32 addr_offset, u32 *rdata, int timeout)+{
u32 addr;u32 val;addr = ((addr_offset | CLKMGR_MEM_ADDR_START) & CLKMGR_MEM_ADDR_MASK);val = ((CLKMGR_MEM_REQ_SET_MSK & ~CLKMGR_MEM_WR_SET_MSK) | addr);if (pll == MEMBUS_MAINPLL)CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_MEM);elseCM_REG_WRITEL(plat, val, CLKMGR_PERPLL_MEM);*rdata = 0;if (membus_wait_for_req(plat, pll, timeout))return -ETIMEDOUT;if (pll == MEMBUS_MAINPLL)*rdata = CM_REG_READL(plat, CLKMGR_MAINPLL_MEMSTAT);else*rdata = CM_REG_READL(plat, CLKMGR_PERPLL_MEMSTAT);debug("MEMBUS: Read 0x%08x from addr = 0x%08x\n", *rdata, addr);return 0;+}
+static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) +{
u32 mdiv, refclkdiv, arefclkdiv, drefclkdiv, mscnt, hscnt, vcocalib;mdiv = pllm & CLKMGR_PLLM_MDIV_MASK;arefclkdiv = (pllglob & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;drefclkdiv = (pllglob & CLKMGR_PLLGLOB_DREFCLKDIV_MASK) >>CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET;refclkdiv = (pllglob & CLKMGR_PLLGLOB_REFCLKDIV_MASK) >>CLKMGR_PLLGLOB_REFCLKDIV_OFFSET;mscnt = CLKMGR_VCOCALIB_MSCNT_CONST / (mdiv * BIT(drefclkdiv));if (!mscnt)mscnt = 1;hscnt = (mdiv * mscnt * BIT(drefclkdiv) / refclkdiv) -CLKMGR_VCOCALIB_HSCNT_CONST;vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |((mscnt << CLKMGR_VCOCALIB_MSCNT_OFFSET) &CLKMGR_VCOCALIB_MSCNT_MASK);/* Dump all the pll calibration settings for debug purposes */debug("mdiv : %d\n", mdiv);debug("arefclkdiv : %d\n", arefclkdiv);debug("drefclkdiv : %d\n", drefclkdiv);debug("refclkdiv : %d\n", refclkdiv);debug("mscnt : %d\n", mscnt);debug("hscnt : %d\n", hscnt);debug("vcocalib : 0x%08x\n", vcocalib);return vcocalib;+}
+/*
- Setup clocks while making no assumptions about previous state of the clocks.
- */
+static void clk_basic_init(struct udevice *dev,
const struct cm_config * const cfg)+{
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);u32 vcocalib;u32 rdata;if (!cfg)return;/* Put both PLLs in bypass */clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);/* Put both PLLs in Reset and Power Down */CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLGLOB,CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLGLOB,CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);/* setup main PLL dividers where calculate the vcocalib value */vcocalib = calc_vocalib_pll(cfg->main_pll_pllm, cfg->main_pll_pllglob);CM_REG_WRITEL(plat, cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,CLKMGR_MAINPLL_PLLGLOB);CM_REG_WRITEL(plat, cfg->main_pll_fdbck, CLKMGR_MAINPLL_FDBCK);CM_REG_WRITEL(plat, vcocalib, CLKMGR_MAINPLL_VCOCALIB);CM_REG_WRITEL(plat, cfg->main_pll_pllc0, CLKMGR_MAINPLL_PLLC0);CM_REG_WRITEL(plat, cfg->main_pll_pllc1, CLKMGR_MAINPLL_PLLC1);CM_REG_WRITEL(plat, cfg->main_pll_pllc2, CLKMGR_MAINPLL_PLLC2);CM_REG_WRITEL(plat, cfg->main_pll_pllc3, CLKMGR_MAINPLL_PLLC3);CM_REG_WRITEL(plat, cfg->main_pll_pllm, CLKMGR_MAINPLL_PLLM);CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);/* setup peripheral PLL dividers where calculate the vcocalib value */vcocalib = calc_vocalib_pll(cfg->per_pll_pllm, cfg->per_pll_pllglob);CM_REG_WRITEL(plat, cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_RST_MASK,CLKMGR_PERPLL_PLLGLOB);CM_REG_WRITEL(plat, cfg->per_pll_fdbck, CLKMGR_PERPLL_FDBCK);CM_REG_WRITEL(plat, vcocalib, CLKMGR_PERPLL_VCOCALIB);CM_REG_WRITEL(plat, cfg->per_pll_pllc0, CLKMGR_PERPLL_PLLC0);CM_REG_WRITEL(plat, cfg->per_pll_pllc1, CLKMGR_PERPLL_PLLC1);CM_REG_WRITEL(plat, cfg->per_pll_pllc2, CLKMGR_PERPLL_PLLC2);CM_REG_WRITEL(plat, cfg->per_pll_pllc3, CLKMGR_PERPLL_PLLC3);CM_REG_WRITEL(plat, cfg->per_pll_pllm, CLKMGR_PERPLL_PLLM);CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);/* Take both PLL out of reset and power up */CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLGLOB,CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLGLOB,CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);/* Membus programming to set mainpll and perripll to* source synchronous mode*/membus_read_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE, &rdata,MEMBUS_TIMEOUT);membus_write_pll(plat, MEMBUS_MAINPLL, MEMBUS_ADDR_CLKSLICE,(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),MEMBUS_TIMEOUT);membus_read_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE, &rdata,MEMBUS_TIMEOUT);membus_write_pll(plat, MEMBUS_PERPLL, MEMBUS_ADDR_CLKSLICE,(rdata | MEMBUS_CLKSLICE_SYNC_MODE_EN),MEMBUS_TIMEOUT);cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);/* Configure ping pong counters in altera group */CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);CM_REG_WRITEL(plat, cfg->alt_s2fuser0ctr, CLKMGR_ALTR_S2FUSER0CTR);CM_REG_WRITEL(plat, cfg->alt_s2fuser1ctr, CLKMGR_ALTR_S2FUSER1CTR);CM_REG_WRITEL(plat, cfg->alt_psirefctr, CLKMGR_ALTR_PSIREFCTR);CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_MAINPLL_LOSTLOCK);CM_REG_WRITEL(plat, CLKMGR_LOSTLOCK_SET_MASK, CLKMGR_PERPLL_LOSTLOCK);CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_MAINPLL_PLLGLOB) |CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,CLKMGR_MAINPLL_PLLGLOB);CM_REG_WRITEL(plat, CM_REG_READL(plat, CLKMGR_PERPLL_PLLGLOB) |CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,CLKMGR_PERPLL_PLLGLOB);/* Take all PLLs out of bypass */clk_write_bypass_mainpll(plat, 0);clk_write_bypass_perpll(plat, 0);/* Clear the loss of lock bits (write 1 to clear) */CM_REG_CLRBITS(plat, CLKMGR_INTRCLR,CLKMGR_INTER_PERPLLLOST_MASK |CLKMGR_INTER_MAINPLLLOST_MASK);/* Take all ping pong counters out of reset */CM_REG_CLRBITS(plat, CLKMGR_ALTR_EXTCNTRST,CLKMGR_ALT_EXTCNTRST_ALLCNTRST);/* Out of boot mode */clk_write_ctrl(plat,CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE);+}
+static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat,
u32 pllglob_reg, u32 pllm_reg)+{
u64 fref, arefdiv, mdiv, reg, vco;reg = CM_REG_READL(plat, pllglob_reg);fref = (reg & CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;switch (fref) {case CLKMGR_VCO_PSRC_EOSC1:fref = cm_get_osc_clk_hz();break;case CLKMGR_VCO_PSRC_INTOSC:fref = cm_get_intosc_clk_hz();break;case CLKMGR_VCO_PSRC_F2S:fref = cm_get_fpga_clk_hz();break;}arefdiv = (reg & CLKMGR_PLLGLOB_AREFCLKDIV_MASK) >>CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET;mdiv = CM_REG_READL(plat, pllm_reg) & CLKMGR_PLLM_MDIV_MASK;vco = fref / arefdiv;vco = vco * mdiv;return vco;+}
+static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat) +{
return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB,CLKMGR_MAINPLL_PLLM);+}
+static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat) +{
return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB,CLKMGR_PERPLL_PLLM);+}
+static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg) +{
u32 clksrc = CM_REG_READL(plat, reg);return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET;+}
+static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg,
u32 main_reg, u32 per_reg)+{
u64 clock;u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);switch (clklsrc) {case CLKMGR_CLKSRC_MAIN:clock = clk_get_main_vco_clk_hz(plat);clock /= (CM_REG_READL(plat, main_reg) &CLKMGR_CLKCNT_MSK);break;case CLKMGR_CLKSRC_PER:clock = clk_get_per_vco_clk_hz(plat);clock /= (CM_REG_READL(plat, per_reg) &CLKMGR_CLKCNT_MSK);break;case CLKMGR_CLKSRC_OSC1:clock = cm_get_osc_clk_hz();break;case CLKMGR_CLKSRC_INTOSC:clock = cm_get_intosc_clk_hz();break;case CLKMGR_CLKSRC_FPGA:clock = cm_get_fpga_clk_hz();break;default:return 0;}return clock;+}
+static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat) +{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK,CLKMGR_MAINPLL_PLLC0,CLKMGR_PERPLL_PLLC0);clock /= 1 + (CM_REG_READL(plat, CLKMGR_MAINPLL_MPUCLK) &CLKMGR_CLKCNT_MSK);return clock;+}
+static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat) +{
return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK,CLKMGR_MAINPLL_PLLC1,CLKMGR_PERPLL_PLLC1);+}
+static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat) +{
u64 clock = clk_get_l3_main_clk_hz(plat);clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>CLKMGR_NOCDIV_L4MAIN_OFFSET) &CLKMGR_NOCDIV_DIVIDER_MASK);return clock;+}
+static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat) +{
u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR,CLKMGR_MAINPLL_PLLC3,CLKMGR_PERPLL_PLLC3);clock /= 1 + (CM_REG_READL(plat, CLKMGR_ALTR_SDMMCCTR) &CLKMGR_CLKCNT_MSK);return clock / 4;+}
+static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat) +{
u64 clock = clk_get_l3_main_clk_hz(plat);clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>CLKMGR_NOCDIV_L4SPCLK_OFFSET) &CLKMGR_NOCDIV_DIVIDER_MASK);return clock;+}
+static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat) +{
u64 clock = clk_get_l3_main_clk_hz(plat);clock /= BIT((CM_REG_READL(plat, CLKMGR_MAINPLL_NOCDIV) >>CLKMGR_NOCDIV_L4MPCLK_OFFSET) &CLKMGR_NOCDIV_DIVIDER_MASK);return clock;+}
+static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat) +{
if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE)return clk_get_l3_main_clk_hz(plat) / 2;return clk_get_l3_main_clk_hz(plat) / 4;+}
+static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id) +{
bool emacsel_a;u32 ctl;u32 ctr_reg;u32 clock;u32 div;u32 reg;/* Get EMAC clock source */ctl = CM_REG_READL(plat, CLKMGR_PERPLL_EMACCTL);if (emac_id == SOCFPGA_SOC64_EMAC0_CLK)ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET) &CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK;else if (emac_id == SOCFPGA_SOC64_EMAC1_CLK)ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET) &CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK;else if (emac_id == SOCFPGA_SOC64_EMAC2_CLK)ctl = (ctl >> CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET) &CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK;elsereturn 0;if (ctl) {/* EMAC B source */emacsel_a = false;ctr_reg = CLKMGR_ALTR_EMACBCTR;} else {/* EMAC A source */emacsel_a = true;ctr_reg = CLKMGR_ALTR_EMACACTR;}reg = CM_REG_READL(plat, ctr_reg);clock = (reg & CLKMGR_ALT_EMACCTR_SRC_MASK)>> CLKMGR_ALT_EMACCTR_SRC_OFFSET;div = (reg & CLKMGR_ALT_EMACCTR_CNT_MASK)>> CLKMGR_ALT_EMACCTR_CNT_OFFSET;switch (clock) {case CLKMGR_CLKSRC_MAIN:clock = clk_get_main_vco_clk_hz(plat);if (emacsel_a) {clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC2) &CLKMGR_CLKCNT_MSK);} else {clock /= (CM_REG_READL(plat, CLKMGR_MAINPLL_PLLC3) &CLKMGR_CLKCNT_MSK);}break;case CLKMGR_CLKSRC_PER:clock = clk_get_per_vco_clk_hz(plat);if (emacsel_a) {clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC2) &CLKMGR_CLKCNT_MSK);} else {clock /= (CM_REG_READL(plat, CLKMGR_PERPLL_PLLC3) &CLKMGR_CLKCNT_MSK);}break;case CLKMGR_CLKSRC_OSC1:clock = cm_get_osc_clk_hz();break;case CLKMGR_CLKSRC_INTOSC:clock = cm_get_intosc_clk_hz();break;case CLKMGR_CLKSRC_FPGA:clock = cm_get_fpga_clk_hz();break;}clock /= 1 + div;return clock;+}
+static ulong socfpga_clk_get_rate(struct clk *clk) +{
struct socfpga_clk_platdata *plat = dev_get_platdata(clk->dev);switch (clk->id) {case SOCFPGA_SOC64_MPU_CLK:return clk_get_mpu_clk_hz(plat);case SOCFPGA_SOC64_L4_MAIN_CLK:return clk_get_l4_main_clk_hz(plat);case SOCFPGA_SOC64_L4_SYS_FREE_CLK:return clk_get_l4_sys_free_clk_hz(plat);case SOCFPGA_SOC64_L4_MP_CLK:return clk_get_l4_mp_clk_hz(plat);case SOCFPGA_SOC64_L4_SP_CLK:return clk_get_l4_sp_clk_hz(plat);case SOCFPGA_SOC64_SDMMC_CLK:return clk_get_sdmmc_clk_hz(plat);case SOCFPGA_SOC64_EMAC0_CLK:case SOCFPGA_SOC64_EMAC1_CLK:case SOCFPGA_SOC64_EMAC2_CLK:return clk_get_emac_clk_hz(plat, clk->id);case SOCFPGA_SOC64_USB_CLK:return clk_get_l4_mp_clk_hz(plat);default:return -ENXIO;}+}
+static int socfpga_clk_probe(struct udevice *dev) +{
const struct cm_config *cm_default_cfg = cm_get_default_config();clk_basic_init(dev, cm_default_cfg);return 0;+}
+static int socfpga_clk_ofdata_to_platdata(struct udevice *dev) +{
struct socfpga_clk_platdata *plat = dev_get_platdata(dev);fdt_addr_t addr;addr = devfdt_get_addr(dev);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->regs = (void __iomem *)addr;return 0;+}
+static struct clk_ops socfpga_clk_ops = {
.get_rate = socfpga_clk_get_rate,+};
+static const struct udevice_id socfpga_clk_match[] = {
{ .compatible = "intel,agilex-clkmgr" },{}+};
+U_BOOT_DRIVER(socfpga_agilex_clk) = {
.name = "clk-agilex",.id = UCLASS_CLK,.of_match = socfpga_clk_match,.ops = &socfpga_clk_ops,.probe = socfpga_clk_probe,.ofdata_to_platdata = socfpga_clk_ofdata_to_platdata,.platdata_auto_alloc_size = sizeof(struct socfpga_clk_platdata),+}; diff --git a/drivers/clk/altera/clk-agilex.h b/drivers/clk/altera/clk-agilex.h new file mode 100644 index 0000000000..3cf2afa006 --- /dev/null +++ b/drivers/clk/altera/clk-agilex.h @@ -0,0 +1,237 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CLK_AGILEX_ +#define _CLK_AGILEX_
+#define CM_REG_READL(plat, reg) \
readl(plat->regs + (reg))+#define CM_REG_WRITEL(plat, data, reg) \
writel(data, plat->regs + (reg))+#define CM_REG_CLRBITS(plat, reg, clear) \
clrbits_le32(plat->regs + (reg), (clear))+#define CM_REG_SETBITS(plat, reg, set) \
setbits_le32(plat->regs + (reg), (set))+struct cm_config {
/* main group */u32 main_pll_mpuclk;u32 main_pll_nocclk;u32 main_pll_nocdiv;u32 main_pll_pllglob;u32 main_pll_fdbck;u32 main_pll_pllc0;u32 main_pll_pllc1;u32 main_pll_pllc2;u32 main_pll_pllc3;u32 main_pll_pllm;/* peripheral group */u32 per_pll_emacctl;u32 per_pll_gpiodiv;u32 per_pll_pllglob;u32 per_pll_fdbck;u32 per_pll_pllc0;u32 per_pll_pllc1;u32 per_pll_pllc2;u32 per_pll_pllc3;u32 per_pll_pllm;/* altera group */u32 alt_emacactr;u32 alt_emacbctr;u32 alt_emacptpctr;u32 alt_gpiodbctr;u32 alt_sdmmcctr;u32 alt_s2fuser0ctr;u32 alt_s2fuser1ctr;u32 alt_psirefctr;/* incoming clock */u32 hps_osc_clk_hz;u32 fpga_clk_hz;u32 spare[3];+};
+/* Clock Manager registers */ +#define CLKMGR_CTRL 0 +#define CLKMGR_STAT 4 +#define CLKMGR_TESTIOCTRL 8 +#define CLKMGR_INTRGEN 0x0c +#define CLKMGR_INTRMSK 0x10 +#define CLKMGR_INTRCLR 0x14 +#define CLKMGR_INTRSTS 0x18 +#define CLKMGR_INTRSTK 0x1c +#define CLKMGR_INTRRAW 0x20
+/* Clock Manager Main PPL group registers */ +#define CLKMGR_MAINPLL_EN 0x24 +#define CLKMGR_MAINPLL_ENS 0x28 +#define CLKMGR_MAINPLL_ENR 0x2c +#define CLKMGR_MAINPLL_BYPASS 0x30 +#define CLKMGR_MAINPLL_BYPASSS 0x34 +#define CLKMGR_MAINPLL_BYPASSR 0x38 +#define CLKMGR_MAINPLL_MPUCLK 0x3c +#define CLKMGR_MAINPLL_NOCCLK 0x40 +#define CLKMGR_MAINPLL_NOCDIV 0x44 +#define CLKMGR_MAINPLL_PLLGLOB 0x48 +#define CLKMGR_MAINPLL_FDBCK 0x4c +#define CLKMGR_MAINPLL_MEM 0x50 +#define CLKMGR_MAINPLL_MEMSTAT 0x54 +#define CLKMGR_MAINPLL_PLLC0 0x58 +#define CLKMGR_MAINPLL_PLLC1 0x5c +#define CLKMGR_MAINPLL_VCOCALIB 0x60 +#define CLKMGR_MAINPLL_PLLC2 0x64 +#define CLKMGR_MAINPLL_PLLC3 0x68 +#define CLKMGR_MAINPLL_PLLM 0x6c +#define CLKMGR_MAINPLL_FHOP 0x70 +#define CLKMGR_MAINPLL_SSC 0x74 +#define CLKMGR_MAINPLL_LOSTLOCK 0x78
+/* Clock Manager Peripheral PPL group registers */ +#define CLKMGR_PERPLL_EN 0x7c +#define CLKMGR_PERPLL_ENS 0x80 +#define CLKMGR_PERPLL_ENR 0x84 +#define CLKMGR_PERPLL_BYPASS 0x88 +#define CLKMGR_PERPLL_BYPASSS 0x8c +#define CLKMGR_PERPLL_BYPASSR 0x90 +#define CLKMGR_PERPLL_EMACCTL 0x94 +#define CLKMGR_PERPLL_GPIODIV 0x98 +#define CLKMGR_PERPLL_PLLGLOB 0x9c +#define CLKMGR_PERPLL_FDBCK 0xa0 +#define CLKMGR_PERPLL_MEM 0xa4 +#define CLKMGR_PERPLL_MEMSTAT 0xa8 +#define CLKMGR_PERPLL_PLLC0 0xac +#define CLKMGR_PERPLL_PLLC1 0xb0 +#define CLKMGR_PERPLL_VCOCALIB 0xb4 +#define CLKMGR_PERPLL_PLLC2 0xb8 +#define CLKMGR_PERPLL_PLLC3 0xbc +#define CLKMGR_PERPLL_PLLM 0xc0 +#define CLKMGR_PERPLL_FHOP 0xc4 +#define CLKMGR_PERPLL_SSC 0xc8 +#define CLKMGR_PERPLL_LOSTLOCK 0xcc
+/* Clock Manager Altera group registers */ +#define CLKMGR_ALTR_JTAG 0xd0 +#define CLKMGR_ALTR_EMACACTR 0xd4 +#define CLKMGR_ALTR_EMACBCTR 0xd8 +#define CLKMGR_ALTR_EMACPTPCTR 0xdc +#define CLKMGR_ALTR_GPIODBCTR 0xe0 +#define CLKMGR_ALTR_SDMMCCTR 0xe4 +#define CLKMGR_ALTR_S2FUSER0CTR 0xe8 +#define CLKMGR_ALTR_S2FUSER1CTR 0xec +#define CLKMGR_ALTR_PSIREFCTR 0xf0 +#define CLKMGR_ALTR_EXTCNTRST 0xf4
+#define CLKMGR_CTRL_BOOTMODE BIT(0)
+#define CLKMGR_STAT_BUSY BIT(0) +#define CLKMGR_STAT_MAINPLL_LOCKED BIT(8) +#define CLKMGR_STAT_MAIN_TRANS BIT(9) +#define CLKMGR_STAT_PERPLL_LOCKED BIT(16) +#define CLKMGR_STAT_PERF_TRANS BIT(17) +#define CLKMGR_STAT_BOOTMODE BIT(24) +#define CLKMGR_STAT_BOOTCLKSRC BIT(25)
+#define CLKMGR_STAT_ALLPLL_LOCKED_MASK \
(CLKMGR_STAT_MAINPLL_LOCKED | CLKMGR_STAT_PERPLL_LOCKED)+#define CLKMGR_INTER_MAINPLLLOCKED_MASK 0x00000001 +#define CLKMGR_INTER_PERPLLLOCKED_MASK 0x00000002 +#define CLKMGR_INTER_MAINPLLLOST_MASK 0x00000004 +#define CLKMGR_INTER_PERPLLLOST_MASK 0x00000008
+#define CLKMGR_CLKSRC_MASK GENMASK(18, 16) +#define CLKMGR_CLKSRC_OFFSET 16 +#define CLKMGR_CLKSRC_MAIN 0 +#define CLKMGR_CLKSRC_PER 1 +#define CLKMGR_CLKSRC_OSC1 2 +#define CLKMGR_CLKSRC_INTOSC 3 +#define CLKMGR_CLKSRC_FPGA 4 +#define CLKMGR_CLKCNT_MSK GENMASK(10, 0)
+#define CLKMGR_BYPASS_MAINPLL_ALL 0x7 +#define CLKMGR_BYPASS_PERPLL_ALL 0x7f
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET 0 +#define CLKMGR_NOCDIV_L4MPCLK_OFFSET 8 +#define CLKMGR_NOCDIV_L4SPCLK_OFFSET 16 +#define CLKMGR_NOCDIV_CSATCLK_OFFSET 24 +#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET 26 +#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET 28 +#define CLKMGR_NOCDIV_DIVIDER_MASK 0x3
+#define CLKMGR_PLLGLOB_PD_MASK BIT(0) +#define CLKMGR_PLLGLOB_RST_MASK BIT(1) +#define CLKMGR_PLLGLOB_AREFCLKDIV_MASK GENMASK(11, 8) +#define CLKMGR_PLLGLOB_DREFCLKDIV_MASK GENMASK(13, 12) +#define CLKMGR_PLLGLOB_REFCLKDIV_MASK GENMASK(13, 8) +#define CLKMGR_PLLGLOB_MODCLKDIV_MASK GENMASK(24, 27) +#define CLKMGR_PLLGLOB_AREFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_DREFCLKDIV_OFFSET 12 +#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET 8 +#define CLKMGR_PLLGLOB_MODCLKDIV_OFFSET 24 +#define CLKMGR_PLLGLOB_VCO_PSRC_MASK GENMASK(17, 16) +#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET 16 +#define CLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK BIT(29)
+#define CLKMGR_VCO_PSRC_EOSC1 0 +#define CLKMGR_VCO_PSRC_INTOSC 1 +#define CLKMGR_VCO_PSRC_F2S 2
+#define CLKMGR_MEM_REQ_SET_MSK BIT(24) +#define CLKMGR_MEM_WR_SET_MSK BIT(25) +#define CLKMGR_MEM_ERR_MSK BIT(26) +#define CLKMGR_MEM_WDAT_LSB_OFFSET 16 +#define CLKMGR_MEM_ADDR_MASK GENMASK(15, 0) +#define CLKMGR_MEM_ADDR_START 0x00004000
+#define CLKMGR_PLLCX_EN_SET_MSK BIT(27) +#define CLKMGR_PLLCX_MUTE_SET_MSK BIT(28)
+#define CLKMGR_VCOCALIB_MSCNT_MASK GENMASK(23, 16) +#define CLKMGR_VCOCALIB_MSCNT_OFFSET 16 +#define CLKMGR_VCOCALIB_HSCNT_MASK GENMASK(9, 0) +#define CLKMGR_VCOCALIB_MSCNT_CONST 100 +#define CLKMGR_VCOCALIB_HSCNT_CONST 4
+#define CLKMGR_PLLM_MDIV_MASK GENMASK(9, 0)
+#define CLKMGR_LOSTLOCK_SET_MASK BIT(0)
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_OFFSET 26 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC0SELB_MASK BIT(26) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_OFFSET 27 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC1SELB_MASK BIT(27) +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_OFFSET 28 +#define CLKMGR_PERPLLGRP_EMACCTL_EMAC2SELB_MASK BIT(28)
+#define CLKMGR_ALT_EMACCTR_SRC_OFFSET 16 +#define CLKMGR_ALT_EMACCTR_SRC_MASK GENMASK(18, 16) +#define CLKMGR_ALT_EMACCTR_CNT_OFFSET 0 +#define CLKMGR_ALT_EMACCTR_CNT_MASK GENMASK(10, 0)
+#define CLKMGR_ALT_EXTCNTRST_EMACACNTRST BIT(0) +#define CLKMGR_ALT_EXTCNTRST_EMACBCNTRST BIT(1) +#define CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST BIT(2) +#define CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST BIT(3) +#define CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST BIT(4) +#define CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST BIT(5) +#define CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST BIT(6) +#define CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST BIT(7) +#define CLKMGR_ALT_EXTCNTRST_ALLCNTRST \
(CLKMGR_ALT_EXTCNTRST_EMACACNTRST | \CLKMGR_ALT_EXTCNTRST_EMACBCNTRST | \CLKMGR_ALT_EXTCNTRST_EMACPTPCNTRST | \CLKMGR_ALT_EXTCNTRST_GPIODBCNTRST | \CLKMGR_ALT_EXTCNTRST_SDMMCCNTRST | \CLKMGR_ALT_EXTCNTRST_S2FUSER0CNTRST | \CLKMGR_ALT_EXTCNTRST_S2FUSER1CNTRST | \CLKMGR_ALT_EXTCNTRST_PSIREFCNTRST)+#endif /* _CLK_AGILEX_ */ diff --git a/include/dt-bindings/clock/socfpga-soc64-clock.h b/include/dt-bindings/clock/socfpga-soc64-clock.h new file mode 100644 index 0000000000..6a05f63676 --- /dev/null +++ b/include/dt-bindings/clock/socfpga-soc64-clock.h @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2017-2019, Intel Corporation
- */
+#ifndef __SOCFPGA_SOC64_CLOCK_H +#define __SOCFPGA_SOC64_CLOCK_H
+/* fixed rate clocks */ +#define SOCFPGA_SOC64_OSC1 0 +#define SOCFPGA_SOC64_CB_INTOSC_HS_DIV2_CLK 1 +#define SOCFPGA_SOC64_CB_INTOSC_LS_CLK 2 +#define SOCFPGA_SOC64_F2S_FREE_CLK 3
+/* fixed factor clocks */ +#define SOCFPGA_SOC64_L4_SYS_FREE_CLK 4 +#define SOCFPGA_SOC64_MPU_PERIPH_CLK 5 +#define SOCFPGA_SOC64_MPU_L2RAM_CLK 6 +#define SOCFPGA_SOC64_SDMMC_CIU_CLK 7
+/* PLL clocks */ +#define SOCFPGA_SOC64_MAIN_PLL_CLK 8 +#define SOCFPGA_SOC64_PERIPH_PLL_CLK 9 +#define SOCFPGA_SOC64_BOOT_CLK 10
+/* Periph clocks */ +#define SOCFPGA_SOC64_MAIN_MPU_BASE_CLK 11 +#define SOCFPGA_SOC64_MAIN_NOC_BASE_CLK 12 +#define SOCFPGA_SOC64_MAIN_EMACA_CLK 13 +#define SOCFPGA_SOC64_MAIN_EMACB_CLK 14 +#define SOCFPGA_SOC64_MAIN_EMAC_PTP_CLK 15 +#define SOCFPGA_SOC64_MAIN_GPIO_DB_CLK 16 +#define SOCFPGA_SOC64_MAIN_SDMMC_CLK 17 +#define SOCFPGA_SOC64_MAIN_S2F_USR0_CLK 18 +#define SOCFPGA_SOC64_MAIN_S2F_USR1_CLK 19 +#define SOCFPGA_SOC64_MAIN_PSI_REF_CLK 20
+#define SOCFPGA_SOC64_PERI_MPU_BASE_CLK 21 +#define SOCFPGA_SOC64_PERI_NOC_BASE_CLK 22 +#define SOCFPGA_SOC64_PERI_EMACA_CLK 23 +#define SOCFPGA_SOC64_PERI_EMACB_CLK 24 +#define SOCFPGA_SOC64_PERI_EMAC_PTP_CLK 25 +#define SOCFPGA_SOC64_PERI_GPIO_DB_CLK 26 +#define SOCFPGA_SOC64_PERI_SDMMC_CLK 27 +#define SOCFPGA_SOC64_PERI_S2F_USR0_CLK 28 +#define SOCFPGA_SOC64_PERI_S2F_USR1_CLK 29 +#define SOCFPGA_SOC64_PERI_PSI_REF_CLK 30
+#define SOCFPGA_SOC64_MPU_FREE_CLK 31 +#define SOCFPGA_SOC64_NOC_FREE_CLK 32 +#define SOCFPGA_SOC64_S2F_USR0_CLK 33 +#define SOCFPGA_SOC64_NOC_CLK 34 +#define SOCFPGA_SOC64_EMAC_A_FREE_CLK 35 +#define SOCFPGA_SOC64_EMAC_B_FREE_CLK 36 +#define SOCFPGA_SOC64_EMAC_PTP_FREE_CLK 37 +#define SOCFPGA_SOC64_GPIO_DB_FREE_CLK 38 +#define SOCFPGA_SOC64_SDMMC_FREE_CLK 39 +#define SOCFPGA_SOC64_S2F_USER1_FREE_CLK 40 +#define SOCFPGA_SOC64_PSI_REF_FREE_CLK 41
+/* Gate clocks */ +#define SOCFPGA_SOC64_MPU_CLK 42 +#define SOCFPGA_SOC64_L4_MAIN_CLK 43 +#define SOCFPGA_SOC64_L4_MP_CLK 44 +#define SOCFPGA_SOC64_L4_SP_CLK 45 +#define SOCFPGA_SOC64_CS_AT_CLK 46 +#define SOCFPGA_SOC64_CS_TRACE_CLK 47 +#define SOCFPGA_SOC64_CS_PDBG_CLK 48 +#define SOCFPGA_SOC64_CS_TIMER_CLK 49 +#define SOCFPGA_SOC64_S2F_USER0_CLK 50 +#define SOCFPGA_SOC64_S2F_USER1_CLK 51 +#define SOCFPGA_SOC64_EMAC0_CLK 52 +#define SOCFPGA_SOC64_EMAC1_CLK 53 +#define SOCFPGA_SOC64_EMAC2_CLK 54 +#define SOCFPGA_SOC64_EMAC_PTP_CLK 55 +#define SOCFPGA_SOC64_GPIO_DB_CLK 56 +#define SOCFPGA_SOC64_SDMMC_CLK 57 +#define SOCFPGA_SOC64_PSI_REF_CLK 58 +#define SOCFPGA_SOC64_USB_CLK 59 +#define SOCFPGA_SOC64_SPI_M_CLK 60 +#define SOCFPGA_SOC64_NAND_CLK 61 +#define SOCFPGA_SOC64_NUM_CLKS 62
+#endif /* __SOCFPGA_SOC64_CLOCK_H */
2.19.0
Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Change to use SYSMGR_SOC64* prefix.
v3: - Improved commit message. - Rename STRATIX10_* to SOCFPGA_SOC64_* - Include clock_manager_soc64.h and clk-agilex.h.
v2: - Get clocks from clock DM. --- arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++++++++++++++++++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 ++++ 4 files changed, 104 insertions(+) create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index dab34d0ef2..a403b46b47 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += clock_manager_agilex.o +endif + ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c new file mode 100644 index 0000000000..9e0b3ef29d --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <clk.h> +#include <common.h> +#include <dm.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <dt-bindings/clock/socfpga-soc64-clock.h> + +DECLARE_GLOBAL_DATA_PTR; + +static ulong cm_get_rate_dm(u32 id) +{ + struct udevice *dev; + struct clk clk; + ulong rate; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(socfpga_agilex_clk), + &dev); + if (ret) + return 0; + + clk.id = id; + ret = clk_request(dev, &clk); + if (ret < 0) + return 0; + + rate = clk_get_rate(&clk); + + clk_free(&clk); + + if ((rate == (unsigned long)-ENOSYS) || + (rate == (unsigned long)-ENXIO) || + (rate == (unsigned long)-EIO)) { + debug("%s id %u: clk_get_rate err: %ld\n", + __func__, id, rate); + return 0; + } + + return rate; +} + +static u32 cm_get_rate_dm_khz(u32 id) +{ + return cm_get_rate_dm(id) / 1000; +} + +unsigned long cm_get_mpu_clk_hz(void) +{ + return cm_get_rate_dm(SOCFPGA_SOC64_MPU_CLK); +} + +unsigned int cm_get_l4_sys_free_clk_hz(void) +{ + return cm_get_rate_dm(SOCFPGA_SOC64_L4_SYS_FREE_CLK); +} + +u32 cm_get_qspi_controller_clk_hz(void) +{ + return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0); +} + +void cm_print_clock_quick_summary(void) +{ + printf("MPU %10d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_MPU_CLK)); + printf("L4 Main %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MAIN_CLK)); + printf("L4 sys free %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SYS_FREE_CLK)); + printf("L4 MP %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MP_CLK)); + printf("L4 SP %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SP_CLK)); + printf("SDMMC %8d kHz\n", + cm_get_rate_dm_khz(SOCFPGA_SOC64_SDMMC_CLK)); +} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 4f9d10dd78..5d3ee2a83f 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/clock_manager_agilex.h> #endif
#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h new file mode 100644 index 0000000000..386e82a4e3 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _CLOCK_MANAGER_AGILEX_ +#define _CLOCK_MANAGER_AGILEX_ + +unsigned long cm_get_mpu_clk_hz(void); + +#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex.h" + +#endif /* _CLOCK_MANAGER_AGILEX_ */
On Thu, Sep 12, 2019 at 12:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add clock wrapper functions call to clock DM functions to get clock frequency and used in cm_print_clock_quick_summary().
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
This whole patch looks like a hack to me. However, I was facing the same problem when porting gen5 to DM_CLK (and I haven't found a better way). For now, this is probably OK, but could you find a way to solve this in a cleaner way (without referencing driver includes from arch)? That would be great!
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Change to use SYSMGR_SOC64* prefix.
v3:
- Improved commit message.
- Rename STRATIX10_* to SOCFPGA_SOC64_*
- Include clock_manager_soc64.h and clk-agilex.h.
v2:
- Get clocks from clock DM.
arch/arm/mach-socfpga/Makefile | 4 + arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++++++++++++++++++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 ++++ 4 files changed, 104 insertions(+) create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index dab34d0ef2..a403b46b47 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -39,6 +39,10 @@ obj-y += wrap_pinmux_config_s10.o obj-y += wrap_pll_config_s10.o endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += clock_manager_agilex.o +endif
ifdef CONFIG_SPL_BUILD ifdef CONFIG_TARGET_SOCFPGA_GEN5 obj-y += spl_gen5.o diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c b/arch/arm/mach-socfpga/clock_manager_agilex.c new file mode 100644 index 0000000000..9e0b3ef29d --- /dev/null +++ b/arch/arm/mach-socfpga/clock_manager_agilex.c @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <clk.h> +#include <common.h> +#include <dm.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <dt-bindings/clock/socfpga-soc64-clock.h>
+DECLARE_GLOBAL_DATA_PTR;
+static ulong cm_get_rate_dm(u32 id) +{
struct udevice *dev;struct clk clk;ulong rate;int ret;ret = uclass_get_device_by_driver(UCLASS_CLK,DM_GET_DRIVER(socfpga_agilex_clk),&dev);if (ret)return 0;clk.id = id;ret = clk_request(dev, &clk);if (ret < 0)return 0;rate = clk_get_rate(&clk);clk_free(&clk);if ((rate == (unsigned long)-ENOSYS) ||(rate == (unsigned long)-ENXIO) ||(rate == (unsigned long)-EIO)) {debug("%s id %u: clk_get_rate err: %ld\n",__func__, id, rate);return 0;}return rate;+}
+static u32 cm_get_rate_dm_khz(u32 id) +{
return cm_get_rate_dm(id) / 1000;+}
+unsigned long cm_get_mpu_clk_hz(void) +{
return cm_get_rate_dm(SOCFPGA_SOC64_MPU_CLK);+}
+unsigned int cm_get_l4_sys_free_clk_hz(void) +{
return cm_get_rate_dm(SOCFPGA_SOC64_L4_SYS_FREE_CLK);+}
+u32 cm_get_qspi_controller_clk_hz(void) +{
return readl(socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD0);+}
+void cm_print_clock_quick_summary(void) +{
printf("MPU %10d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_MPU_CLK));printf("L4 Main %8d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MAIN_CLK));printf("L4 sys free %8d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SYS_FREE_CLK));printf("L4 MP %8d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_MP_CLK));printf("L4 SP %8d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_L4_SP_CLK));printf("SDMMC %8d kHz\n",cm_get_rate_dm_khz(SOCFPGA_SOC64_SDMMC_CLK));+} diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 4f9d10dd78..5d3ee2a83f 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -20,6 +20,8 @@ void cm_print_clock_quick_summary(void); #include <asm/arch/clock_manager_arria10.h> #elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10) #include <asm/arch/clock_manager_s10.h> +#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) +#include <asm/arch/clock_manager_agilex.h> #endif
#endif /* _CLOCK_MANAGER_H_ */ diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h new file mode 100644 index 0000000000..386e82a4e3 --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CLOCK_MANAGER_AGILEX_ +#define _CLOCK_MANAGER_AGILEX_
+unsigned long cm_get_mpu_clk_hz(void);
+#include <asm/arch/clock_manager_soc64.h> +#include "../../../../../drivers/clk/altera/clk-agilex.h"
+#endif /* _CLOCK_MANAGER_AGILEX_ */
2.19.0
Add Cache Coherency Unit (CCU) support for Agilex. CCU is to ensures consistency of shared data between multi masters in the system.
Software need to initialize CCU's directories and coherency agent interfaces in CCU IP.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++++++++++++++++++ .../mach-socfpga/include/mach/ccu_agilex.h | 67 +++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index a403b46b47..6f39dc06ed 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -58,6 +58,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += firewall.o obj-y += spl_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += ccu_agilex.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/ccu_agilex.c b/arch/arm/mach-socfpga/ccu_agilex.c new file mode 100644 index 0000000000..f27a48b523 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_agilex.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ +#include <asm/io.h> +#include <wait_bit.h> +#include <asm/arch/ccu_agilex.h> + +static void ccu_init_dirs(void) +{ + ulong i, f; + int ret; + u32 num_of_dirs; + u32 num_of_snoop_filters; + u32 reg; + + num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR))); + num_of_snoop_filters = + CSIDR_NUMSFS_GET(readl(CCU_REG_ADDR(CSIDR))) + 1; + + /* Initialize each snoop filter in each directory */ + for (f = 0; f < num_of_snoop_filters; f++) { + reg = f << DIRUSFMCR_SFID_SHIFT; + for (i = 0; i < num_of_dirs; i++) { + /* Initialize all entries */ + writel(reg, CCU_DIR_REG_ADDR(i, DIRUSFMCR)); + + /* Poll snoop filter maintenance operation active + * bit become 0. + */ + ret = wait_for_bit_le32((const void *) + CCU_DIR_REG_ADDR(i, DIRUSFMAR), + BIT(0), false, 1000, false); + if (ret) { + puts("CCU: Directory initialization failed!\n"); + hang(); + } + + /* Enable snoop filter, a bit per snoop filter */ + setbits_le32((ulong)CCU_DIR_REG_ADDR(i, DIRUSFER), + BIT(f)); + } + } +} + +void ccu_init_coh_agent_intf(void) +{ + u32 num_of_coh_agent_intf; + u32 num_of_dirs; + u32 reg; + u32 type; + u32 i, dir; + + num_of_coh_agent_intf = + CSUIDR_NUMCAIUS_GET(readl(CCU_REG_ADDR(CSUIDR))); + num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR))); + + for (i = 0; i < num_of_coh_agent_intf; i++) { + reg = readl((ulong)CCU_CAIU_REG_ADDR(i, CAIUIDR)); + if (CAIUIDR_CA_GET(reg)) { + /* Caching agent bit is enabled, enable caching agent + * snoop in each directory + */ + for (dir = 0; dir < num_of_dirs; dir++) { + setbits_le32((ulong) + CCU_DIR_REG_ADDR(dir, DIRUCASER0), + BIT(i)); + } + } + + type = CAIUIDR_TYPE_GET(reg); + if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT || + type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) { + /* DVM support is enabled, enable ACE DVM snoop*/ + setbits_le32((ulong)(CCU_REG_ADDR(CSADSER0)), + BIT(i)); + } + } +} + +static void ocram_bypass_firewall(void) +{ + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_01_REG)), + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_02_REG)), + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_03_REG)), + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); + clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_04_REG)), + OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK); +} + +void ccu_init(void) +{ + ccu_init_dirs(); + ccu_init_coh_agent_intf(); + ocram_bypass_firewall(); +} diff --git a/arch/arm/mach-socfpga/include/mach/ccu_agilex.h b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h new file mode 100644 index 0000000000..4e5373e0ad --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#ifndef _CCU_AGILEX_H_ +#define _CCU_AGILEX_H_ + +/* Directory */ +#define DIRUSFER 0x80010 +#define DIRUCASER0 0x80040 +#define DIRUMRHER 0x80070 +#define DIRUSFMCR 0x80080 +#define DIRUSFMAR 0x80084 + +#define DIRUSFMCR_SFID_SHIFT 16 + +/* Coherent cache agent interface */ +#define CAIUIDR 0x00ffc + +#define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15) +#define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16) +#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0 +#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1 + +/* Coherent subsystem */ +#define CSADSER0 0xff040 +#define CSUIDR 0xffff8 +#define CSIDR 0xffffc + +#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0) +#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16) +#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24) + +#define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18) + +#define DIR_REG_OFF 0x1000 +#define CAIU_REG_OFF 0x1000 +#define COHMEM_REG_OFF 0x1000 + +#define CCU_REG_ADDR(reg) \ + (SOCFPGA_CCU_ADDRESS + (reg)) + +#define CCU_DIR_REG_ADDR(dir, reg) \ + (CCU_REG_ADDR(reg) + ((dir) * DIR_REG_OFF)) + +#define CCU_CAIU_REG_ADDR(caiu, reg) \ + (CCU_REG_ADDR(reg) + ((caiu) * CAIU_REG_OFF)) + +/* Coherent CPU BYPASS OCRAM */ +#define COH_CPU0_BYPASS_OC_BASE (SOCFPGA_CCU_ADDRESS + 0x100200) + +#define OCRAM_BLK_CGF_01_REG 0x4 +#define OCRAM_BLK_CGF_02_REG 0x8 +#define OCRAM_BLK_CGF_03_REG 0xc +#define OCRAM_BLK_CGF_04_REG 0x10 +#define OCRAM_SECURE_REGIONS 4 + +#define OCRAM_PRIVILEGED_MASK BIT(29) +#define OCRAM_SECURE_MASK BIT(30) + +#define COH_CPU0_BYPASS_REG_ADDR(reg) \ + (COH_CPU0_BYPASS_OC_BASE + (reg)) + +void ccu_init(void); + +#endif /* _CCU_AGILEX_H_ */
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add Cache Coherency Unit (CCU) support for Agilex. CCU is to ensures consistency of shared data between multi masters in the system.
Wouldn't this better fit into drivers/cache instead of adding yet more arch code?
Regards, Simon
Software need to initialize CCU's directories and coherency agent interfaces in CCU IP.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++++++++++++++++++ .../mach-socfpga/include/mach/ccu_agilex.h | 67 +++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index a403b46b47..6f39dc06ed 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -58,6 +58,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += firewall.o obj-y += spl_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += ccu_agilex.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/ccu_agilex.c b/arch/arm/mach-socfpga/ccu_agilex.c new file mode 100644 index 0000000000..f27a48b523 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_agilex.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <asm/io.h> +#include <wait_bit.h> +#include <asm/arch/ccu_agilex.h>
+static void ccu_init_dirs(void) +{
ulong i, f;int ret;u32 num_of_dirs;u32 num_of_snoop_filters;u32 reg;num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));num_of_snoop_filters =CSIDR_NUMSFS_GET(readl(CCU_REG_ADDR(CSIDR))) + 1;/* Initialize each snoop filter in each directory */for (f = 0; f < num_of_snoop_filters; f++) {reg = f << DIRUSFMCR_SFID_SHIFT;for (i = 0; i < num_of_dirs; i++) {/* Initialize all entries */writel(reg, CCU_DIR_REG_ADDR(i, DIRUSFMCR));/* Poll snoop filter maintenance operation active* bit become 0.*/ret = wait_for_bit_le32((const void *)CCU_DIR_REG_ADDR(i, DIRUSFMAR),BIT(0), false, 1000, false);if (ret) {puts("CCU: Directory initialization failed!\n");hang();}/* Enable snoop filter, a bit per snoop filter */setbits_le32((ulong)CCU_DIR_REG_ADDR(i, DIRUSFER),BIT(f));}}+}
+void ccu_init_coh_agent_intf(void) +{
u32 num_of_coh_agent_intf;u32 num_of_dirs;u32 reg;u32 type;u32 i, dir;num_of_coh_agent_intf =CSUIDR_NUMCAIUS_GET(readl(CCU_REG_ADDR(CSUIDR)));num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));for (i = 0; i < num_of_coh_agent_intf; i++) {reg = readl((ulong)CCU_CAIU_REG_ADDR(i, CAIUIDR));if (CAIUIDR_CA_GET(reg)) {/* Caching agent bit is enabled, enable caching agent* snoop in each directory*/for (dir = 0; dir < num_of_dirs; dir++) {setbits_le32((ulong)CCU_DIR_REG_ADDR(dir, DIRUCASER0),BIT(i));}}type = CAIUIDR_TYPE_GET(reg);if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {/* DVM support is enabled, enable ACE DVM snoop*/setbits_le32((ulong)(CCU_REG_ADDR(CSADSER0)),BIT(i));}}+}
+static void ocram_bypass_firewall(void) +{
clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_01_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_02_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_03_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_04_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);+}
+void ccu_init(void) +{
ccu_init_dirs();ccu_init_coh_agent_intf();ocram_bypass_firewall();+} diff --git a/arch/arm/mach-socfpga/include/mach/ccu_agilex.h b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h new file mode 100644 index 0000000000..4e5373e0ad --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CCU_AGILEX_H_ +#define _CCU_AGILEX_H_
+/* Directory */ +#define DIRUSFER 0x80010 +#define DIRUCASER0 0x80040 +#define DIRUMRHER 0x80070 +#define DIRUSFMCR 0x80080 +#define DIRUSFMAR 0x80084
+#define DIRUSFMCR_SFID_SHIFT 16
+/* Coherent cache agent interface */ +#define CAIUIDR 0x00ffc
+#define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15) +#define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16) +#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0 +#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
+/* Coherent subsystem */ +#define CSADSER0 0xff040 +#define CSUIDR 0xffff8 +#define CSIDR 0xffffc
+#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0) +#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16) +#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
+#define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
+#define DIR_REG_OFF 0x1000 +#define CAIU_REG_OFF 0x1000 +#define COHMEM_REG_OFF 0x1000
+#define CCU_REG_ADDR(reg) \
(SOCFPGA_CCU_ADDRESS + (reg))+#define CCU_DIR_REG_ADDR(dir, reg) \
(CCU_REG_ADDR(reg) + ((dir) * DIR_REG_OFF))+#define CCU_CAIU_REG_ADDR(caiu, reg) \
(CCU_REG_ADDR(reg) + ((caiu) * CAIU_REG_OFF))+/* Coherent CPU BYPASS OCRAM */ +#define COH_CPU0_BYPASS_OC_BASE (SOCFPGA_CCU_ADDRESS + 0x100200)
+#define OCRAM_BLK_CGF_01_REG 0x4 +#define OCRAM_BLK_CGF_02_REG 0x8 +#define OCRAM_BLK_CGF_03_REG 0xc +#define OCRAM_BLK_CGF_04_REG 0x10 +#define OCRAM_SECURE_REGIONS 4
+#define OCRAM_PRIVILEGED_MASK BIT(29) +#define OCRAM_SECURE_MASK BIT(30)
+#define COH_CPU0_BYPASS_REG_ADDR(reg) \
(COH_CPU0_BYPASS_OC_BASE + (reg))+void ccu_init(void);
+#endif /* _CCU_AGILEX_H_ */
2.19.0
On Wed, Oct 2, 2019 at 4:42 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add Cache Coherency Unit (CCU) support for Agilex. CCU is to ensures consistency of shared data between multi masters in the system.
Wouldn't this better fit into drivers/cache instead of adding yet more arch code?
Even CCU is slightly different from normal cache controller, but we should able to use cache DM for it. Will change this.
Regards Ley Foon
Software need to initialize CCU's directories and coherency agent interfaces in CCU IP.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
arch/arm/mach-socfpga/Makefile | 3 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++++++++++++++++++ .../mach-socfpga/include/mach/ccu_agilex.h | 67 +++++++++++++ 3 files changed, 169 insertions(+) create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index a403b46b47..6f39dc06ed 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -58,6 +58,9 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10 obj-y += firewall.o obj-y += spl_s10.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX +obj-y += ccu_agilex.o +endif endif
ifdef CONFIG_TARGET_SOCFPGA_GEN5 diff --git a/arch/arm/mach-socfpga/ccu_agilex.c b/arch/arm/mach-socfpga/ccu_agilex.c new file mode 100644 index 0000000000..f27a48b523 --- /dev/null +++ b/arch/arm/mach-socfpga/ccu_agilex.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <asm/io.h> +#include <wait_bit.h> +#include <asm/arch/ccu_agilex.h>
+static void ccu_init_dirs(void) +{
ulong i, f;int ret;u32 num_of_dirs;u32 num_of_snoop_filters;u32 reg;num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));num_of_snoop_filters =CSIDR_NUMSFS_GET(readl(CCU_REG_ADDR(CSIDR))) + 1;/* Initialize each snoop filter in each directory */for (f = 0; f < num_of_snoop_filters; f++) {reg = f << DIRUSFMCR_SFID_SHIFT;for (i = 0; i < num_of_dirs; i++) {/* Initialize all entries */writel(reg, CCU_DIR_REG_ADDR(i, DIRUSFMCR));/* Poll snoop filter maintenance operation active* bit become 0.*/ret = wait_for_bit_le32((const void *)CCU_DIR_REG_ADDR(i, DIRUSFMAR),BIT(0), false, 1000, false);if (ret) {puts("CCU: Directory initialization failed!\n");hang();}/* Enable snoop filter, a bit per snoop filter */setbits_le32((ulong)CCU_DIR_REG_ADDR(i, DIRUSFER),BIT(f));}}+}
+void ccu_init_coh_agent_intf(void) +{
u32 num_of_coh_agent_intf;u32 num_of_dirs;u32 reg;u32 type;u32 i, dir;num_of_coh_agent_intf =CSUIDR_NUMCAIUS_GET(readl(CCU_REG_ADDR(CSUIDR)));num_of_dirs = CSUIDR_NUMDIRUS_GET(readl(CCU_REG_ADDR(CSUIDR)));for (i = 0; i < num_of_coh_agent_intf; i++) {reg = readl((ulong)CCU_CAIU_REG_ADDR(i, CAIUIDR));if (CAIUIDR_CA_GET(reg)) {/* Caching agent bit is enabled, enable caching agent* snoop in each directory*/for (dir = 0; dir < num_of_dirs; dir++) {setbits_le32((ulong)CCU_DIR_REG_ADDR(dir, DIRUCASER0),BIT(i));}}type = CAIUIDR_TYPE_GET(reg);if (type == CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT ||type == CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT) {/* DVM support is enabled, enable ACE DVM snoop*/setbits_le32((ulong)(CCU_REG_ADDR(CSADSER0)),BIT(i));}}+}
+static void ocram_bypass_firewall(void) +{
clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_01_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_02_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_03_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);clrbits_le32((ulong)(COH_CPU0_BYPASS_REG_ADDR(OCRAM_BLK_CGF_04_REG)),OCRAM_PRIVILEGED_MASK | OCRAM_SECURE_MASK);+}
+void ccu_init(void) +{
ccu_init_dirs();ccu_init_coh_agent_intf();ocram_bypass_firewall();+} diff --git a/arch/arm/mach-socfpga/include/mach/ccu_agilex.h b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h new file mode 100644 index 0000000000..4e5373e0ad --- /dev/null +++ b/arch/arm/mach-socfpga/include/mach/ccu_agilex.h @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#ifndef _CCU_AGILEX_H_ +#define _CCU_AGILEX_H_
+/* Directory */ +#define DIRUSFER 0x80010 +#define DIRUCASER0 0x80040 +#define DIRUMRHER 0x80070 +#define DIRUSFMCR 0x80080 +#define DIRUSFMAR 0x80084
+#define DIRUSFMCR_SFID_SHIFT 16
+/* Coherent cache agent interface */ +#define CAIUIDR 0x00ffc
+#define CAIUIDR_CA_GET(v) (((v) & 0x00008000) >> 15) +#define CAIUIDR_TYPE_GET(v) (((v) & 0x000f0000) >> 16) +#define CAIUIDR_TYPE_ACE_CAI_DVM_SUPPORT 0 +#define CAIUIDR_TYPE_ACELITE_CAI_DVM_SUPPORT 1
+/* Coherent subsystem */ +#define CSADSER0 0xff040 +#define CSUIDR 0xffff8 +#define CSIDR 0xffffc
+#define CSUIDR_NUMCAIUS_GET(v) (((v) & 0x0000007f) >> 0) +#define CSUIDR_NUMDIRUS_GET(v) (((v) & 0x003f0000) >> 16) +#define CSUIDR_NUMCMIUS_GET(v) (((v) & 0x3f000000) >> 24)
+#define CSIDR_NUMSFS_GET(v) (((v) & 0x007c0000) >> 18)
+#define DIR_REG_OFF 0x1000 +#define CAIU_REG_OFF 0x1000 +#define COHMEM_REG_OFF 0x1000
+#define CCU_REG_ADDR(reg) \
(SOCFPGA_CCU_ADDRESS + (reg))+#define CCU_DIR_REG_ADDR(dir, reg) \
(CCU_REG_ADDR(reg) + ((dir) * DIR_REG_OFF))+#define CCU_CAIU_REG_ADDR(caiu, reg) \
(CCU_REG_ADDR(reg) + ((caiu) * CAIU_REG_OFF))+/* Coherent CPU BYPASS OCRAM */ +#define COH_CPU0_BYPASS_OC_BASE (SOCFPGA_CCU_ADDRESS + 0x100200)
+#define OCRAM_BLK_CGF_01_REG 0x4 +#define OCRAM_BLK_CGF_02_REG 0x8 +#define OCRAM_BLK_CGF_03_REG 0xc +#define OCRAM_BLK_CGF_04_REG 0x10 +#define OCRAM_SECURE_REGIONS 4
+#define OCRAM_PRIVILEGED_MASK BIT(29) +#define OCRAM_SECURE_MASK BIT(30)
+#define COH_CPU0_BYPASS_REG_ADDR(reg) \
(COH_CPU0_BYPASS_OC_BASE + (reg))+void ccu_init(void);
+#endif /* _CCU_AGILEX_H_ */
2.19.0
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++++++-- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 5 +++-- 2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h index ba0f1fd1b2..abf04d9b04 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -26,8 +26,13 @@ #define S10_HANDOFF_OFFSET_LENGTH 0x4 #define S10_HANDOFF_OFFSET_DATA 0x10
-#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) -#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#ifdef TARGET_SOCFPGA_STRATIX10 +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#else +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600) +#endif
#define S10_HANDOFF_SIZE 4096
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index b002f38215..d27accab57 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_OSC); + + u32 clock = readl(HANDOFF_CLOCK_OSC);
writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1); #endif @@ -48,7 +49,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD - u32 clock = readl(S10_HANDOFF_CLOCK_FPGA); + u32 clock = readl(HANDOFF_CLOCK_FPGA);
writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2); #endif
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add clock handoff offset for Agilex. Remove S10 prefix to avoid confusion.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 9 +++++++-- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 5 +++-- 2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_s10.h b/arch/arm/mach-socfpga/include/mach/handoff_s10.h index ba0f1fd1b2..abf04d9b04 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_s10.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_s10.h @@ -26,8 +26,13 @@ #define S10_HANDOFF_OFFSET_LENGTH 0x4 #define S10_HANDOFF_OFFSET_DATA 0x10
-#define S10_HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) -#define S10_HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#ifdef TARGET_SOCFPGA_STRATIX10 +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x608) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x60C) +#else +#define HANDOFF_CLOCK_OSC (S10_HANDOFF_BASE + 0x5fc) +#define HANDOFF_CLOCK_FPGA (S10_HANDOFF_BASE + 0x600) +#endif
#define S10_HANDOFF_SIZE 4096
diff --git a/arch/arm/mach-socfpga/wrap_pll_config_s10.c b/arch/arm/mach-socfpga/wrap_pll_config_s10.c index b002f38215..d27accab57 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config_s10.c +++ b/arch/arm/mach-socfpga/wrap_pll_config_s10.c @@ -33,7 +33,8 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(void) { #ifdef CONFIG_SPL_BUILD
u32 clock = readl(S10_HANDOFF_CLOCK_OSC);
u32 clock = readl(HANDOFF_CLOCK_OSC); writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);#endif @@ -48,7 +49,7 @@ const unsigned int cm_get_intosc_clk_hz(void) const unsigned int cm_get_fpga_clk_hz(void) { #ifdef CONFIG_SPL_BUILD
u32 clock = readl(S10_HANDOFF_CLOCK_FPGA);
u32 clock = readl(HANDOFF_CLOCK_FPGA); writel(clock, socfpga_sysmgr_base + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);#endif
2.19.0
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Change to use base address from DT.
v3: - Change sdram_common.* to sdram_soc64.* --- drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram_s10.c | 296 +---------------- drivers/ddr/altera/sdram_s10.h | 148 +-------- drivers/ddr/altera/sdram_soc64.c | 304 ++++++++++++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 70 ++-- 5 files changed, 341 insertions(+), 479 deletions(-) create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 341ac0d73b..eb8da13b7d 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 9578aa743d..fcab3ae3e4 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -14,28 +14,14 @@ #include "sdram_s10.h" #include <wait_bit.h> #include <asm/arch/firewall.h> -#include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> #include <linux/sizes.h>
-struct altera_sdram_priv { - struct ram_info info; - struct reset_ctl_bulk resets; -}; - -struct altera_sdram_platdata { - void __iomem *hmc; - void __iomem *ddr_sch; - void __iomem *iomhc; -}; - DECLARE_GLOBAL_DATA_PTR;
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
-#define PGTABLE_OFF 0x4000 - /* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -62,28 +48,6 @@ u32 ddr_config[] = { DDR_CONFIG(1, 4, 10, 17), };
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) -{ - return readl(plat->iomhc + reg); -} - -static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) -{ - return readl(plat->hmc + reg); -} - -static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, - u32 data, u32 reg) -{ - return writel(data, plat->hmc + reg); -} - -static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, - u32 reg) -{ - return writel(data, plat->ddr_sch + reg); -} - int match_ddr_conf(u32 ddr_conf) { int i; @@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf) return 0; }
-static int emif_clear(struct altera_sdram_platdata *plat) -{ - hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); - - return wait_for_bit_le32((const void *)(plat->hmc + - RSTHANDSHAKESTAT), - DDR_HMC_RSTHANDSHAKE_MASK, - false, 1000, false); -} - -static int emif_reset(struct altera_sdram_platdata *plat) -{ - u32 c2s, s2c, ret; - - c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; - s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; - - debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", - c2s, s2c, hmc_readl(plat, NIOSRESERVED0), - hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), - hmc_readl(plat, DRAMSTS)); - - if (s2c && emif_clear(plat)) { - printf("DDR: emif_clear() failed\n"); - return -1; - } - - debug("DDR: Triggerring emif reset\n"); - hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); - - /* if seq2core[3] = 0, we are good */ - ret = wait_for_bit_le32((const void *)(plat->hmc + - RSTHANDSHAKESTAT), - DDR_HMC_SEQ2CORE_INT_RESP_MASK, - false, 1000, false); - if (ret) { - printf("DDR: failed to get ack from EMIF\n"); - return ret; - } - - ret = emif_clear(plat); - if (ret) { - printf("DDR: emif_clear() failed\n"); - return ret; - } - - debug("DDR: %s triggered successly\n", __func__); - return 0; -} - -static int poll_hmc_clock_status(void) -{ - return wait_for_bit_le32((const void *)(socfpga_sysmgr_base + - SYSMGR_SOC64_HMC_CLK), - SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); -} - -static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) -{ - phys_size_t i; - - if (addr % CONFIG_SYS_CACHELINE_SIZE) { - printf("DDR: address 0x%llx is not cacheline size aligned.\n", - addr); - hang(); - } - - if (size % CONFIG_SYS_CACHELINE_SIZE) { - printf("DDR: size 0x%llx is not multiple of cacheline size\n", - size); - hang(); - } - - /* Use DC ZVA instruction to clear memory to zeros by a cache line */ - for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { - asm volatile("dc zva, %0" - : - : "r"(addr) - : "memory"); - addr += CONFIG_SYS_CACHELINE_SIZE; - } -} - -static void sdram_init_ecc_bits(bd_t *bd) -{ - phys_size_t size, size_init; - phys_addr_t start_addr; - int bank = 0; - unsigned int start = get_timer(0); - - icache_enable(); - - start_addr = bd->bi_dram[0].start; - size = bd->bi_dram[0].size; - - /* Initialize small block for page table */ - memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); - gd->arch.tlb_addr = start_addr + PGTABLE_OFF; - gd->arch.tlb_size = PGTABLE_SIZE; - start_addr += PGTABLE_SIZE + PGTABLE_OFF; - size -= (PGTABLE_OFF + PGTABLE_SIZE); - dcache_enable(); - - while (1) { - while (size) { - size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); - sdram_clear_mem(start_addr, size_init); - size -= size_init; - start_addr += size_init; - WATCHDOG_RESET(); - } - - bank++; - if (bank >= CONFIG_NR_DRAM_BANKS) - break; - - start_addr = bd->bi_dram[bank].start; - size = bd->bi_dram[bank].size; - } - - dcache_disable(); - icache_disable(); - - printf("SDRAM-ECC: Initialized success with %d ms\n", - (unsigned int)get_timer(start)); -} - -static void sdram_size_check(bd_t *bd) -{ - phys_size_t total_ram_check = 0; - phys_size_t ram_check = 0; - phys_addr_t start = 0; - int bank; - - /* Sanity check ensure correct SDRAM size specified */ - debug("DDR: Running SDRAM size sanity check\n"); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start = bd->bi_dram[bank].start; - while (ram_check < bd->bi_dram[bank].size) { - ram_check += get_ram_size((void *)(start + ram_check), - (phys_size_t)SZ_1G); - } - total_ram_check += ram_check; - ram_check = 0; - } - - /* If the ram_size is 2GB smaller, we can assume the IO space is - * not mapped in. gd->ram_size is the actual size of the dram - * not the accessible size. - */ - if (total_ram_check != gd->ram_size) { - puts("DDR: SDRAM size check failed!\n"); - hang(); - } - - debug("DDR: SDRAM size check passed!\n"); -} - -/** - * sdram_calculate_size() - Calculate SDRAM size - * - * Calculate SDRAM device size based on SDRAM controller parameters. - * Size is specified in bytes. - */ -static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) -{ - u32 dramaddrw = hmc_readl(plat, DRAMADDRW); - - phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + - DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); - - size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & - DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); - - return size; -} - /** * sdram_mmr_init_full() - Function to initialize SDRAM MMR * * Initialize the SDRAM MMR. */ -static int sdram_mmr_init_full(struct udevice *dev) +int sdram_mmr_init_full(struct udevice *dev) { struct altera_sdram_platdata *plat = dev->platdata; struct altera_sdram_priv *priv = dev_get_priv(dev); @@ -534,80 +317,3 @@ static int sdram_mmr_init_full(struct udevice *dev) return 0; }
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev) -{ - struct altera_sdram_platdata *plat = dev->platdata; - fdt_addr_t addr; - - addr = dev_read_addr_index(dev, 0); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->ddr_sch = (void __iomem *)addr; - - addr = dev_read_addr_index(dev, 1); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->iomhc = (void __iomem *)addr; - - addr = dev_read_addr_index(dev, 2); - if (addr == FDT_ADDR_T_NONE) - return -EINVAL; - plat->hmc = (void __iomem *)addr; - - return 0; -} - -static int altera_sdram_probe(struct udevice *dev) -{ - int ret; - struct altera_sdram_priv *priv = dev_get_priv(dev); - - ret = reset_get_bulk(dev, &priv->resets); - if (ret) { - dev_err(dev, "Can't get reset: %d\n", ret); - return -ENODEV; - } - reset_deassert_bulk(&priv->resets); - - if (sdram_mmr_init_full(dev) != 0) { - puts("SDRAM init failed.\n"); - goto failed; - } - - return 0; - -failed: - reset_release_bulk(&priv->resets); - return -ENODEV; -} - -static int altera_sdram_get_info(struct udevice *dev, - struct ram_info *info) -{ - struct altera_sdram_priv *priv = dev_get_priv(dev); - - info->base = priv->info.base; - info->size = priv->info.size; - - return 0; -} - -static struct ram_ops altera_sdram_ops = { - .get_info = altera_sdram_get_info, -}; - -static const struct udevice_id altera_sdram_ids[] = { - { .compatible = "altr,sdr-ctl-s10" }, - { /* sentinel */ } -}; - -U_BOOT_DRIVER(altera_sdram) = { - .name = "altr_sdr_ctl", - .id = UCLASS_RAM, - .of_match = altera_sdram_ids, - .ops = &altera_sdram_ops, - .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, - .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), - .probe = altera_sdram_probe, - .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), -}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h index 096c06cba2..cca4cb35ec 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_s10.h @@ -11,48 +11,6 @@ #define DDR_READ_LATENCY_DELAY 40 #define DDR_ACTIVATE_FAWBANK 0x1
-/* ECC HMC registers */ -#define DDRIOCTRL 0x8 -#define DDRCALSTAT 0xc -#define DRAMADDRWIDTH 0xe0 -#define ECCCTRL1 0x100 -#define ECCCTRL2 0x104 -#define ERRINTEN 0x110 -#define ERRINTENS 0x114 -#define INTMODE 0x11c -#define INTSTAT 0x120 -#define AUTOWB_CORRADDR 0x138 -#define ECC_REG2WRECCDATABUS 0x144 -#define ECC_DIAGON 0x150 -#define ECC_DECSTAT 0x154 -#define HPSINTFCSEL 0x210 -#define RSTHANDSHAKECTRL 0x214 -#define RSTHANDSHAKESTAT 0x218 - -#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 -#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) -#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) -#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) -#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) -#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) -#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) -#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) -#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff -#define DDR_HMC_CORE2SEQ_INT_REQ 0xF -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) -#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f - -#define DDR_HMC_ERRINTEN_INTMASK \ - (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ - DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK) - /* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -79,110 +37,6 @@ #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
-/* HMC MMR IO48 registers */ -#define CTRLCFG0 0x28 -#define CTRLCFG1 0x2c -#define DRAMTIMING0 0x50 -#define CALTIMING0 0x7c -#define CALTIMING1 0x80 -#define CALTIMING2 0x84 -#define CALTIMING3 0x88 -#define CALTIMING4 0x8c -#define CALTIMING9 0xa0 -#define DRAMADDRW 0xa8 -#define DRAMSTS 0xec -#define NIOSRESERVED0 0x110 -#define NIOSRESERVED1 0x114 -#define NIOSRESERVED2 0x118 - -#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \ - (((x) >> 0) & 0x1F) -#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \ - (((x) >> 5) & 0x1F) -#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \ - (((x) >> 10) & 0xF) -#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \ - (((x) >> 14) & 0x3) -#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \ - (((x) >> 16) & 0x7) - -#define CTRLCFG0_CFG_MEMTYPE(x) \ - (((x) >> 0) & 0xF) -#define CTRLCFG0_CFG_DIMM_TYPE(x) \ - (((x) >> 4) & 0x7) -#define CTRLCFG0_CFG_AC_POS(x) \ - (((x) >> 7) & 0x3) -#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \ - (((x) >> 9) & 0x1F) - -#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \ - (((x) >> 0) & 0x1F) -#define CTRLCFG1_CFG_ADDR_ORDER(x) \ - (((x) >> 5) & 0x3) -#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \ - (((x) >> 7) & 0x1) - -#define DRAMTIMING0_CFG_TCL(x) \ - (((x) >> 0) & 0x7F) - -#define CALTIMING0_CFG_ACT_TO_RDWR(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_PCH(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_ACT(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \ - (((x) >> 18) & 0x3F) - -#define CALTIMING1_CFG_RD_TO_RD(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING1_CFG_RD_TO_RD_DC(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING1_CFG_RD_TO_RD_DB(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING1_CFG_RD_TO_WR(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING1_CFG_RD_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING2_CFG_RD_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING2_CFG_WR_TO_WR(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING2_CFG_WR_TO_WR_DC(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING3_CFG_WR_TO_WR_DB(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD_DC(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING3_CFG_WR_TO_RD_DB(x) \ - (((x) >> 18) & 0x3F) -#define CALTIMING3_CFG_WR_TO_PCH(x) \ - (((x) >> 24) & 0x3F) - -#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \ - (((x) >> 0) & 0x3F) -#define CALTIMING4_CFG_PCH_TO_VALID(x) \ - (((x) >> 6) & 0x3F) -#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \ - (((x) >> 12) & 0x3F) -#define CALTIMING4_CFG_ARF_TO_VALID(x) \ - (((x) >> 18) & 0xFF) -#define CALTIMING4_CFG_PDN_TO_VALID(x) \ - (((x) >> 26) & 0x3F) - -#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \ - (((x) >> 0) & 0xFF) - -/* Firewall DDR scheduler MPFE */ -#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 -#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) +#include "sdram_soc64.h"
#endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c new file mode 100644 index 0000000000..3097e0671c --- /dev/null +++ b/drivers/ddr/altera/sdram_soc64.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016-2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <linux/sizes.h> + +#define PGTABLE_OFF 0x4000 + +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) +{ + return readl(plat->iomhc + reg); +} + +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) +{ + return readl(plat->hmc + reg); +} + +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, + u32 data, u32 reg) +{ + return writel(data, plat->hmc + reg); +} + +u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, + u32 reg) +{ + return writel(data, plat->ddr_sch + reg); +} + +int emif_clear(struct altera_sdram_platdata *plat) +{ + hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL); + + return wait_for_bit_le32((const void *)(plat->hmc + + RSTHANDSHAKESTAT), + DDR_HMC_RSTHANDSHAKE_MASK, + false, 1000, false); +} + +int emif_reset(struct altera_sdram_platdata *plat) +{ + u32 c2s, s2c, ret; + + c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK; + s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK; + + debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n", + c2s, s2c, hmc_readl(plat, NIOSRESERVED0), + hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2), + hmc_readl(plat, DRAMSTS)); + + if (s2c && emif_clear(plat)) { + printf("DDR: emif_clear() failed\n"); + return -1; + } + + debug("DDR: Triggerring emif reset\n"); + hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL); + + /* if seq2core[3] = 0, we are good */ + ret = wait_for_bit_le32((const void *)(plat->hmc + + RSTHANDSHAKESTAT), + DDR_HMC_SEQ2CORE_INT_RESP_MASK, + false, 1000, false); + if (ret) { + printf("DDR: failed to get ack from EMIF\n"); + return ret; + } + + ret = emif_clear(plat); + if (ret) { + printf("DDR: emif_clear() failed\n"); + return ret; + } + + debug("DDR: %s triggered successly\n", __func__); + return 0; +} + +int poll_hmc_clock_status(void) +{ + return wait_for_bit_le32((const void *)(socfpga_sysmgr_base + + SYSMGR_SOC64_HMC_CLK), + SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false); +} + +void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{ + phys_size_t i; + + if (addr % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: address 0x%llx is not cacheline size aligned.\n", + addr); + hang(); + } + + if (size % CONFIG_SYS_CACHELINE_SIZE) { + printf("DDR: size 0x%llx is not multiple of cacheline size\n", + size); + hang(); + } + + /* Use DC ZVA instruction to clear memory to zeros by a cache line */ + for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) { + asm volatile("dc zva, %0" + : + : "r"(addr) + : "memory"); + addr += CONFIG_SYS_CACHELINE_SIZE; + } +} + +void sdram_init_ecc_bits(bd_t *bd) +{ + phys_size_t size, size_init; + phys_addr_t start_addr; + int bank = 0; + unsigned int start = get_timer(0); + + icache_enable(); + + start_addr = bd->bi_dram[0].start; + size = bd->bi_dram[0].size; + + /* Initialize small block for page table */ + memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF); + gd->arch.tlb_addr = start_addr + PGTABLE_OFF; + gd->arch.tlb_size = PGTABLE_SIZE; + start_addr += PGTABLE_SIZE + PGTABLE_OFF; + size -= (PGTABLE_OFF + PGTABLE_SIZE); + dcache_enable(); + + while (1) { + while (size) { + size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size); + sdram_clear_mem(start_addr, size_init); + size -= size_init; + start_addr += size_init; + WATCHDOG_RESET(); + } + + bank++; + if (bank >= CONFIG_NR_DRAM_BANKS) + break; + + start_addr = bd->bi_dram[bank].start; + size = bd->bi_dram[bank].size; + } + + dcache_disable(); + icache_disable(); + + printf("SDRAM-ECC: Initialized success with %d ms\n", + (unsigned int)get_timer(start)); +} + +void sdram_size_check(bd_t *bd) +{ + phys_size_t total_ram_check = 0; + phys_size_t ram_check = 0; + phys_addr_t start = 0; + int bank; + + /* Sanity check ensure correct SDRAM size specified */ + debug("DDR: Running SDRAM size sanity check\n"); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start = bd->bi_dram[bank].start; + while (ram_check < bd->bi_dram[bank].size) { + ram_check += get_ram_size((void *)(start + ram_check), + (phys_size_t)SZ_1G); + } + total_ram_check += ram_check; + ram_check = 0; + } + + /* If the ram_size is 2GB smaller, we can assume the IO space is + * not mapped in. gd->ram_size is the actual size of the dram + * not the accessible size. + */ + if (total_ram_check != gd->ram_size) { + puts("DDR: SDRAM size check failed!\n"); + hang(); + } + + debug("DDR: SDRAM size check passed!\n"); +} + +/** + * sdram_calculate_size() - Calculate SDRAM size + * + * Calculate SDRAM device size based on SDRAM controller parameters. + * Size is specified in bytes. + */ +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) +{ + u32 dramaddrw = hmc_readl(plat, DRAMADDRW); + + phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) + + DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw)); + + size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) & + DDR_HMC_DDRIOCTRL_IOSIZE_MSK)); + + return size; +} + +static int altera_sdram_ofdata_to_platdata(struct udevice *dev) +{ + struct altera_sdram_platdata *plat = dev->platdata; + fdt_addr_t addr; + + addr = dev_read_addr_index(dev, 0); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->ddr_sch = (void __iomem *)addr; + + addr = dev_read_addr_index(dev, 1); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->iomhc = (void __iomem *)addr; + + addr = dev_read_addr_index(dev, 2); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + plat->hmc = (void __iomem *)addr; + + return 0; +} + +static int altera_sdram_probe(struct udevice *dev) +{ + int ret; + struct altera_sdram_priv *priv = dev_get_priv(dev); + + ret = reset_get_bulk(dev, &priv->resets); + if (ret) { + dev_err(dev, "Can't get reset: %d\n", ret); + return -ENODEV; + } + reset_deassert_bulk(&priv->resets); + + if (sdram_mmr_init_full(dev) != 0) { + puts("SDRAM init failed.\n"); + goto failed; + } + + return 0; + +failed: + reset_release_bulk(&priv->resets); + return -ENODEV; +} + +static int altera_sdram_get_info(struct udevice *dev, + struct ram_info *info) +{ + struct altera_sdram_priv *priv = dev_get_priv(dev); + + info->base = priv->info.base; + info->size = priv->info.size; + + return 0; +} + +static struct ram_ops altera_sdram_ops = { + .get_info = altera_sdram_get_info, +}; + +static const struct udevice_id altera_sdram_ids[] = { + { .compatible = "altr,sdr-ctl-s10" }, + { .compatible = "intel,sdr-ctl-agilex" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(altera_sdram) = { + .name = "altr_sdr_ctl", + .id = UCLASS_RAM, + .of_match = altera_sdram_ids, + .ops = &altera_sdram_ops, + .ofdata_to_platdata = altera_sdram_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata), + .probe = altera_sdram_probe, + .priv_auto_alloc_size = sizeof(struct altera_sdram_priv), +}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_soc64.h similarity index 79% copy from drivers/ddr/altera/sdram_s10.h copy to drivers/ddr/altera/sdram_soc64.h index 096c06cba2..7d018e76d8 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,15 +1,24 @@ -/* SPDX-License-Identifier: GPL-2.0 - * - * Copyright (C) 2017-2018 Intel Corporation <www.intel.com> - * +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2017-2019 Intel Corporation <www.intel.com> */
-#ifndef _SDRAM_S10_H_ -#define _SDRAM_S10_H_ +#ifndef _SDRAM_SOC64_H_ +#define _SDRAM_SOC64_H_
-#define DDR_TWR 15 -#define DDR_READ_LATENCY_DELAY 40 -#define DDR_ACTIVATE_FAWBANK 0x1 +#include <common.h> +#include <linux/sizes.h> + +struct altera_sdram_priv { + struct ram_info info; + struct reset_ctl_bulk resets; +}; + +struct altera_sdram_platdata { + void __iomem *hmc; + void __iomem *ddr_sch; + void __iomem *iomhc; +};
/* ECC HMC registers */ #define DDRIOCTRL 0x8 @@ -53,32 +62,6 @@ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-/* NOC DDR scheduler */ -#define DDR_SCH_ID_COREID 0 -#define DDR_SCH_ID_REVID 0x4 -#define DDR_SCH_DDRCONF 0x8 -#define DDR_SCH_DDRTIMING 0xc -#define DDR_SCH_DDRMODE 0x10 -#define DDR_SCH_READ_LATENCY 0x14 -#define DDR_SCH_ACTIVATE 0x38 -#define DDR_SCH_DEVTODEV 0x3c -#define DDR_SCH_DDR4TIMING 0x40 - -#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 -#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 -#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 -#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 -#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 -#define DDR_SCH_DDRTIMING_WRTORD_OFF 26 -#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 -#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 -#define DDR_SCH_ACTIVATE_RRD_OFF 0 -#define DDR_SCH_ACTIVATE_FAW_OFF 4 -#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 -#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 -#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 -#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4 - /* HMC MMR IO48 registers */ #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c @@ -185,4 +168,19 @@ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 #define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-#endif /* _SDRAM_S10_H_ */ +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat, + u32 data, u32 reg); +u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data, + u32 reg); +int emif_clear(struct altera_sdram_platdata *plat); +int emif_reset(struct altera_sdram_platdata *plat); +int poll_hmc_clock_status(void); +void sdram_clear_mem(phys_addr_t addr, phys_size_t size); +void sdram_init_ecc_bits(bd_t *bd); +void sdram_size_check(bd_t *bd); +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat); +int sdram_mmr_init_full(struct udevice *dev); + +#endif /* _SDRAM_SOC64_H_ */
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v4:
- Change to use base address from DT.
I know someone has requested this, but I would have preferred it to be in a separate patch. At least you need to put this into the commit message: the patch says you're restructuring, but it does more by reading the base address from DT.
Regards, Simon
v3:
- Change sdram_common.* to sdram_soc64.*
drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram_s10.c | 296 +---------------- drivers/ddr/altera/sdram_s10.h | 148 +-------- drivers/ddr/altera/sdram_soc64.c | 304 ++++++++++++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 70 ++-- 5 files changed, 341 insertions(+), 479 deletions(-) create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 341ac0d73b..eb8da13b7d 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 9578aa743d..fcab3ae3e4 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -14,28 +14,14 @@ #include "sdram_s10.h" #include <wait_bit.h> #include <asm/arch/firewall.h> -#include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> #include <linux/sizes.h>
-struct altera_sdram_priv {
struct ram_info info;struct reset_ctl_bulk resets;-};
-struct altera_sdram_platdata {
void __iomem *hmc;void __iomem *ddr_sch;void __iomem *iomhc;-};
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
-#define PGTABLE_OFF 0x4000
/* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -62,28 +48,6 @@ u32 ddr_config[] = { DDR_CONFIG(1, 4, 10, 17), };
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) -{
return readl(plat->iomhc + reg);-}
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) -{
return readl(plat->hmc + reg);-}
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg)-{
return writel(data, plat->hmc + reg);-}
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg)-{
return writel(data, plat->ddr_sch + reg);-}
int match_ddr_conf(u32 ddr_conf) { int i; @@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf) return 0; }
-static int emif_clear(struct altera_sdram_platdata *plat) -{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);return wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_RSTHANDSHAKE_MASK,false, 1000, false);-}
-static int emif_reset(struct altera_sdram_platdata *plat) -{
u32 c2s, s2c, ret;c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",c2s, s2c, hmc_readl(plat, NIOSRESERVED0),hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),hmc_readl(plat, DRAMSTS));if (s2c && emif_clear(plat)) {printf("DDR: emif_clear() failed\n");return -1;}debug("DDR: Triggerring emif reset\n");hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);/* if seq2core[3] = 0, we are good */ret = wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_SEQ2CORE_INT_RESP_MASK,false, 1000, false);if (ret) {printf("DDR: failed to get ack from EMIF\n");return ret;}ret = emif_clear(plat);if (ret) {printf("DDR: emif_clear() failed\n");return ret;}debug("DDR: %s triggered successly\n", __func__);return 0;-}
-static int poll_hmc_clock_status(void) -{
return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +SYSMGR_SOC64_HMC_CLK),SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);-}
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) -{
phys_size_t i;if (addr % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: address 0x%llx is not cacheline size aligned.\n",addr);hang();}if (size % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: size 0x%llx is not multiple of cacheline size\n",size);hang();}/* Use DC ZVA instruction to clear memory to zeros by a cache line */for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {asm volatile("dc zva, %0":: "r"(addr): "memory");addr += CONFIG_SYS_CACHELINE_SIZE;}-}
-static void sdram_init_ecc_bits(bd_t *bd) -{
phys_size_t size, size_init;phys_addr_t start_addr;int bank = 0;unsigned int start = get_timer(0);icache_enable();start_addr = bd->bi_dram[0].start;size = bd->bi_dram[0].size;/* Initialize small block for page table */memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);gd->arch.tlb_addr = start_addr + PGTABLE_OFF;gd->arch.tlb_size = PGTABLE_SIZE;start_addr += PGTABLE_SIZE + PGTABLE_OFF;size -= (PGTABLE_OFF + PGTABLE_SIZE);dcache_enable();while (1) {while (size) {size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);sdram_clear_mem(start_addr, size_init);size -= size_init;start_addr += size_init;WATCHDOG_RESET();}bank++;if (bank >= CONFIG_NR_DRAM_BANKS)break;start_addr = bd->bi_dram[bank].start;size = bd->bi_dram[bank].size;}dcache_disable();icache_disable();printf("SDRAM-ECC: Initialized success with %d ms\n",(unsigned int)get_timer(start));-}
-static void sdram_size_check(bd_t *bd) -{
phys_size_t total_ram_check = 0;phys_size_t ram_check = 0;phys_addr_t start = 0;int bank;/* Sanity check ensure correct SDRAM size specified */debug("DDR: Running SDRAM size sanity check\n");for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {start = bd->bi_dram[bank].start;while (ram_check < bd->bi_dram[bank].size) {ram_check += get_ram_size((void *)(start + ram_check),(phys_size_t)SZ_1G);}total_ram_check += ram_check;ram_check = 0;}/* If the ram_size is 2GB smaller, we can assume the IO space is* not mapped in. gd->ram_size is the actual size of the dram* not the accessible size.*/if (total_ram_check != gd->ram_size) {puts("DDR: SDRAM size check failed!\n");hang();}debug("DDR: SDRAM size check passed!\n");-}
-/**
- sdram_calculate_size() - Calculate SDRAM size
- Calculate SDRAM device size based on SDRAM controller parameters.
- Size is specified in bytes.
- */
-static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) -{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &DDR_HMC_DDRIOCTRL_IOSIZE_MSK));return size;-}
/**
- sdram_mmr_init_full() - Function to initialize SDRAM MMR
- Initialize the SDRAM MMR.
*/ -static int sdram_mmr_init_full(struct udevice *dev) +int sdram_mmr_init_full(struct udevice *dev) { struct altera_sdram_platdata *plat = dev->platdata; struct altera_sdram_priv *priv = dev_get_priv(dev); @@ -534,80 +317,3 @@ static int sdram_mmr_init_full(struct udevice *dev) return 0; }
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev) -{
struct altera_sdram_platdata *plat = dev->platdata;fdt_addr_t addr;addr = dev_read_addr_index(dev, 0);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->ddr_sch = (void __iomem *)addr;addr = dev_read_addr_index(dev, 1);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->iomhc = (void __iomem *)addr;addr = dev_read_addr_index(dev, 2);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->hmc = (void __iomem *)addr;return 0;-}
-static int altera_sdram_probe(struct udevice *dev) -{
int ret;struct altera_sdram_priv *priv = dev_get_priv(dev);ret = reset_get_bulk(dev, &priv->resets);if (ret) {dev_err(dev, "Can't get reset: %d\n", ret);return -ENODEV;}reset_deassert_bulk(&priv->resets);if (sdram_mmr_init_full(dev) != 0) {puts("SDRAM init failed.\n");goto failed;}return 0;-failed:
reset_release_bulk(&priv->resets);return -ENODEV;-}
-static int altera_sdram_get_info(struct udevice *dev,
struct ram_info *info)-{
struct altera_sdram_priv *priv = dev_get_priv(dev);info->base = priv->info.base;info->size = priv->info.size;return 0;-}
-static struct ram_ops altera_sdram_ops = {
.get_info = altera_sdram_get_info,-};
-static const struct udevice_id altera_sdram_ids[] = {
{ .compatible = "altr,sdr-ctl-s10" },{ /* sentinel */ }-};
-U_BOOT_DRIVER(altera_sdram) = {
.name = "altr_sdr_ctl",.id = UCLASS_RAM,.of_match = altera_sdram_ids,.ops = &altera_sdram_ops,.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),.probe = altera_sdram_probe,.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),-}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h index 096c06cba2..cca4cb35ec 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_s10.h @@ -11,48 +11,6 @@ #define DDR_READ_LATENCY_DELAY 40 #define DDR_ACTIVATE_FAWBANK 0x1
-/* ECC HMC registers */ -#define DDRIOCTRL 0x8 -#define DDRCALSTAT 0xc -#define DRAMADDRWIDTH 0xe0 -#define ECCCTRL1 0x100 -#define ECCCTRL2 0x104 -#define ERRINTEN 0x110 -#define ERRINTENS 0x114 -#define INTMODE 0x11c -#define INTSTAT 0x120 -#define AUTOWB_CORRADDR 0x138 -#define ECC_REG2WRECCDATABUS 0x144 -#define ECC_DIAGON 0x150 -#define ECC_DECSTAT 0x154 -#define HPSINTFCSEL 0x210 -#define RSTHANDSHAKECTRL 0x214 -#define RSTHANDSHAKESTAT 0x218
-#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 -#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) -#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) -#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) -#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) -#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) -#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) -#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) -#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff -#define DDR_HMC_CORE2SEQ_INT_REQ 0xF -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) -#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
-#define DDR_HMC_ERRINTEN_INTMASK \
(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)/* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -79,110 +37,6 @@ #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
-/* HMC MMR IO48 registers */ -#define CTRLCFG0 0x28 -#define CTRLCFG1 0x2c -#define DRAMTIMING0 0x50 -#define CALTIMING0 0x7c -#define CALTIMING1 0x80 -#define CALTIMING2 0x84 -#define CALTIMING3 0x88 -#define CALTIMING4 0x8c -#define CALTIMING9 0xa0 -#define DRAMADDRW 0xa8 -#define DRAMSTS 0xec -#define NIOSRESERVED0 0x110 -#define NIOSRESERVED1 0x114 -#define NIOSRESERVED2 0x118
-#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
(((x) >> 0) & 0x1F)-#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
(((x) >> 5) & 0x1F)-#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
(((x) >> 10) & 0xF)-#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
(((x) >> 14) & 0x3)-#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
(((x) >> 16) & 0x7)-#define CTRLCFG0_CFG_MEMTYPE(x) \
(((x) >> 0) & 0xF)-#define CTRLCFG0_CFG_DIMM_TYPE(x) \
(((x) >> 4) & 0x7)-#define CTRLCFG0_CFG_AC_POS(x) \
(((x) >> 7) & 0x3)-#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
(((x) >> 9) & 0x1F)-#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
(((x) >> 0) & 0x1F)-#define CTRLCFG1_CFG_ADDR_ORDER(x) \
(((x) >> 5) & 0x3)-#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
(((x) >> 7) & 0x1)-#define DRAMTIMING0_CFG_TCL(x) \
(((x) >> 0) & 0x7F)-#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_PCH(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_ACT(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING1_CFG_RD_TO_WR(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING2_CFG_WR_TO_WR(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING3_CFG_WR_TO_PCH(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING4_CFG_PCH_TO_VALID(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING4_CFG_ARF_TO_VALID(x) \
(((x) >> 18) & 0xFF)-#define CALTIMING4_CFG_PDN_TO_VALID(x) \
(((x) >> 26) & 0x3F)-#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)-/* Firewall DDR scheduler MPFE */ -#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 -#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) +#include "sdram_soc64.h"
#endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c new file mode 100644 index 0000000000..3097e0671c --- /dev/null +++ b/drivers/ddr/altera/sdram_soc64.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <linux/sizes.h>
+#define PGTABLE_OFF 0x4000
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) +{
return readl(plat->iomhc + reg);+}
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) +{
return readl(plat->hmc + reg);+}
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg)+{
return writel(data, plat->hmc + reg);+}
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg)+{
return writel(data, plat->ddr_sch + reg);+}
+int emif_clear(struct altera_sdram_platdata *plat) +{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);return wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_RSTHANDSHAKE_MASK,false, 1000, false);+}
+int emif_reset(struct altera_sdram_platdata *plat) +{
u32 c2s, s2c, ret;c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",c2s, s2c, hmc_readl(plat, NIOSRESERVED0),hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),hmc_readl(plat, DRAMSTS));if (s2c && emif_clear(plat)) {printf("DDR: emif_clear() failed\n");return -1;}debug("DDR: Triggerring emif reset\n");hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);/* if seq2core[3] = 0, we are good */ret = wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_SEQ2CORE_INT_RESP_MASK,false, 1000, false);if (ret) {printf("DDR: failed to get ack from EMIF\n");return ret;}ret = emif_clear(plat);if (ret) {printf("DDR: emif_clear() failed\n");return ret;}debug("DDR: %s triggered successly\n", __func__);return 0;+}
+int poll_hmc_clock_status(void) +{
return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +SYSMGR_SOC64_HMC_CLK),SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);+}
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{
phys_size_t i;if (addr % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: address 0x%llx is not cacheline size aligned.\n",addr);hang();}if (size % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: size 0x%llx is not multiple of cacheline size\n",size);hang();}/* Use DC ZVA instruction to clear memory to zeros by a cache line */for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {asm volatile("dc zva, %0":: "r"(addr): "memory");addr += CONFIG_SYS_CACHELINE_SIZE;}+}
+void sdram_init_ecc_bits(bd_t *bd) +{
phys_size_t size, size_init;phys_addr_t start_addr;int bank = 0;unsigned int start = get_timer(0);icache_enable();start_addr = bd->bi_dram[0].start;size = bd->bi_dram[0].size;/* Initialize small block for page table */memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);gd->arch.tlb_addr = start_addr + PGTABLE_OFF;gd->arch.tlb_size = PGTABLE_SIZE;start_addr += PGTABLE_SIZE + PGTABLE_OFF;size -= (PGTABLE_OFF + PGTABLE_SIZE);dcache_enable();while (1) {while (size) {size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);sdram_clear_mem(start_addr, size_init);size -= size_init;start_addr += size_init;WATCHDOG_RESET();}bank++;if (bank >= CONFIG_NR_DRAM_BANKS)break;start_addr = bd->bi_dram[bank].start;size = bd->bi_dram[bank].size;}dcache_disable();icache_disable();printf("SDRAM-ECC: Initialized success with %d ms\n",(unsigned int)get_timer(start));+}
+void sdram_size_check(bd_t *bd) +{
phys_size_t total_ram_check = 0;phys_size_t ram_check = 0;phys_addr_t start = 0;int bank;/* Sanity check ensure correct SDRAM size specified */debug("DDR: Running SDRAM size sanity check\n");for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {start = bd->bi_dram[bank].start;while (ram_check < bd->bi_dram[bank].size) {ram_check += get_ram_size((void *)(start + ram_check),(phys_size_t)SZ_1G);}total_ram_check += ram_check;ram_check = 0;}/* If the ram_size is 2GB smaller, we can assume the IO space is* not mapped in. gd->ram_size is the actual size of the dram* not the accessible size.*/if (total_ram_check != gd->ram_size) {puts("DDR: SDRAM size check failed!\n");hang();}debug("DDR: SDRAM size check passed!\n");+}
+/**
- sdram_calculate_size() - Calculate SDRAM size
- Calculate SDRAM device size based on SDRAM controller parameters.
- Size is specified in bytes.
- */
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) +{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &DDR_HMC_DDRIOCTRL_IOSIZE_MSK));return size;+}
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev) +{
struct altera_sdram_platdata *plat = dev->platdata;fdt_addr_t addr;addr = dev_read_addr_index(dev, 0);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->ddr_sch = (void __iomem *)addr;addr = dev_read_addr_index(dev, 1);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->iomhc = (void __iomem *)addr;addr = dev_read_addr_index(dev, 2);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->hmc = (void __iomem *)addr;return 0;+}
+static int altera_sdram_probe(struct udevice *dev) +{
int ret;struct altera_sdram_priv *priv = dev_get_priv(dev);ret = reset_get_bulk(dev, &priv->resets);if (ret) {dev_err(dev, "Can't get reset: %d\n", ret);return -ENODEV;}reset_deassert_bulk(&priv->resets);if (sdram_mmr_init_full(dev) != 0) {puts("SDRAM init failed.\n");goto failed;}return 0;+failed:
reset_release_bulk(&priv->resets);return -ENODEV;+}
+static int altera_sdram_get_info(struct udevice *dev,
struct ram_info *info)+{
struct altera_sdram_priv *priv = dev_get_priv(dev);info->base = priv->info.base;info->size = priv->info.size;return 0;+}
+static struct ram_ops altera_sdram_ops = {
.get_info = altera_sdram_get_info,+};
+static const struct udevice_id altera_sdram_ids[] = {
{ .compatible = "altr,sdr-ctl-s10" },{ .compatible = "intel,sdr-ctl-agilex" },{ /* sentinel */ }+};
+U_BOOT_DRIVER(altera_sdram) = {
.name = "altr_sdr_ctl",.id = UCLASS_RAM,.of_match = altera_sdram_ids,.ops = &altera_sdram_ops,.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),.probe = altera_sdram_probe,.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),+}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_soc64.h similarity index 79% copy from drivers/ddr/altera/sdram_s10.h copy to drivers/ddr/altera/sdram_soc64.h index 096c06cba2..7d018e76d8 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,15 +1,24 @@ -/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+/* SPDX-License-Identifier: GPL-2.0 */ +/*
*/
- Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
-#ifndef _SDRAM_S10_H_ -#define _SDRAM_S10_H_ +#ifndef _SDRAM_SOC64_H_ +#define _SDRAM_SOC64_H_
-#define DDR_TWR 15 -#define DDR_READ_LATENCY_DELAY 40 -#define DDR_ACTIVATE_FAWBANK 0x1 +#include <common.h> +#include <linux/sizes.h>
+struct altera_sdram_priv {
struct ram_info info;struct reset_ctl_bulk resets;+};
+struct altera_sdram_platdata {
void __iomem *hmc;void __iomem *ddr_sch;void __iomem *iomhc;+};
/* ECC HMC registers */ #define DDRIOCTRL 0x8 @@ -53,32 +62,6 @@ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-/* NOC DDR scheduler */ -#define DDR_SCH_ID_COREID 0 -#define DDR_SCH_ID_REVID 0x4 -#define DDR_SCH_DDRCONF 0x8 -#define DDR_SCH_DDRTIMING 0xc -#define DDR_SCH_DDRMODE 0x10 -#define DDR_SCH_READ_LATENCY 0x14 -#define DDR_SCH_ACTIVATE 0x38 -#define DDR_SCH_DEVTODEV 0x3c -#define DDR_SCH_DDR4TIMING 0x40
-#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 -#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 -#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 -#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 -#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 -#define DDR_SCH_DDRTIMING_WRTORD_OFF 26 -#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 -#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 -#define DDR_SCH_ACTIVATE_RRD_OFF 0 -#define DDR_SCH_ACTIVATE_FAW_OFF 4 -#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 -#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 -#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 -#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
/* HMC MMR IO48 registers */ #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c @@ -185,4 +168,19 @@ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 #define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-#endif /* _SDRAM_S10_H_ */ +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg);+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg);+int emif_clear(struct altera_sdram_platdata *plat); +int emif_reset(struct altera_sdram_platdata *plat); +int poll_hmc_clock_status(void); +void sdram_clear_mem(phys_addr_t addr, phys_size_t size); +void sdram_init_ecc_bits(bd_t *bd); +void sdram_size_check(bd_t *bd); +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat); +int sdram_mmr_init_full(struct udevice *dev);
+#endif /* _SDRAM_SOC64_H_ */
2.19.0
On Wed, Oct 2, 2019 at 5:09 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Restructure Stratix 10 SDRAM driver. Move common code to separate file, in preparation to support SDRAM driver for Agilex.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
v4:
- Change to use base address from DT.
I know someone has requested this, but I would have preferred it to be in a separate patch. At least you need to put this into the commit message: the patch says you're restructuring, but it does more by reading the base address from DT.
Sorry for misleading, because I compared between v3 and v4 patches. Change to use DT base address is in patch "arm: socfpga: Convert system manager from struct to defines" not this patch. Will remove this v4 history.
Regards Ley Foon
v3:
- Change sdram_common.* to sdram_soc64.*
drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/sdram_s10.c | 296 +---------------- drivers/ddr/altera/sdram_s10.h | 148 +-------- drivers/ddr/altera/sdram_soc64.c | 304 ++++++++++++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 70 ++-- 5 files changed, 341 insertions(+), 479 deletions(-) create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%)
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 341ac0d73b..eb8da13b7d 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o -obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o endif diff --git a/drivers/ddr/altera/sdram_s10.c b/drivers/ddr/altera/sdram_s10.c index 9578aa743d..fcab3ae3e4 100644 --- a/drivers/ddr/altera/sdram_s10.c +++ b/drivers/ddr/altera/sdram_s10.c @@ -14,28 +14,14 @@ #include "sdram_s10.h" #include <wait_bit.h> #include <asm/arch/firewall.h> -#include <asm/arch/system_manager.h> #include <asm/arch/reset_manager.h> #include <asm/io.h> #include <linux/sizes.h>
-struct altera_sdram_priv {
struct ram_info info;struct reset_ctl_bulk resets;-};
-struct altera_sdram_platdata {
void __iomem *hmc;void __iomem *ddr_sch;void __iomem *iomhc;-};
DECLARE_GLOBAL_DATA_PTR;
#define DDR_CONFIG(A, B, C, R) (((A) << 24) | ((B) << 16) | ((C) << 8) | (R))
-#define PGTABLE_OFF 0x4000
/* The followring are the supported configurations */ u32 ddr_config[] = { /* DDR_CONFIG(Address order,Bank,Column,Row) */ @@ -62,28 +48,6 @@ u32 ddr_config[] = { DDR_CONFIG(1, 4, 10, 17), };
-static u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) -{
return readl(plat->iomhc + reg);-}
-static u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) -{
return readl(plat->hmc + reg);-}
-static u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg)-{
return writel(data, plat->hmc + reg);-}
-static u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg)-{
return writel(data, plat->ddr_sch + reg);-}
int match_ddr_conf(u32 ddr_conf) { int i; @@ -95,193 +59,12 @@ int match_ddr_conf(u32 ddr_conf) return 0; }
-static int emif_clear(struct altera_sdram_platdata *plat) -{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);return wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_RSTHANDSHAKE_MASK,false, 1000, false);-}
-static int emif_reset(struct altera_sdram_platdata *plat) -{
u32 c2s, s2c, ret;c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",c2s, s2c, hmc_readl(plat, NIOSRESERVED0),hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),hmc_readl(plat, DRAMSTS));if (s2c && emif_clear(plat)) {printf("DDR: emif_clear() failed\n");return -1;}debug("DDR: Triggerring emif reset\n");hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);/* if seq2core[3] = 0, we are good */ret = wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_SEQ2CORE_INT_RESP_MASK,false, 1000, false);if (ret) {printf("DDR: failed to get ack from EMIF\n");return ret;}ret = emif_clear(plat);if (ret) {printf("DDR: emif_clear() failed\n");return ret;}debug("DDR: %s triggered successly\n", __func__);return 0;-}
-static int poll_hmc_clock_status(void) -{
return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +SYSMGR_SOC64_HMC_CLK),SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);-}
-static void sdram_clear_mem(phys_addr_t addr, phys_size_t size) -{
phys_size_t i;if (addr % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: address 0x%llx is not cacheline size aligned.\n",addr);hang();}if (size % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: size 0x%llx is not multiple of cacheline size\n",size);hang();}/* Use DC ZVA instruction to clear memory to zeros by a cache line */for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {asm volatile("dc zva, %0":: "r"(addr): "memory");addr += CONFIG_SYS_CACHELINE_SIZE;}-}
-static void sdram_init_ecc_bits(bd_t *bd) -{
phys_size_t size, size_init;phys_addr_t start_addr;int bank = 0;unsigned int start = get_timer(0);icache_enable();start_addr = bd->bi_dram[0].start;size = bd->bi_dram[0].size;/* Initialize small block for page table */memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);gd->arch.tlb_addr = start_addr + PGTABLE_OFF;gd->arch.tlb_size = PGTABLE_SIZE;start_addr += PGTABLE_SIZE + PGTABLE_OFF;size -= (PGTABLE_OFF + PGTABLE_SIZE);dcache_enable();while (1) {while (size) {size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);sdram_clear_mem(start_addr, size_init);size -= size_init;start_addr += size_init;WATCHDOG_RESET();}bank++;if (bank >= CONFIG_NR_DRAM_BANKS)break;start_addr = bd->bi_dram[bank].start;size = bd->bi_dram[bank].size;}dcache_disable();icache_disable();printf("SDRAM-ECC: Initialized success with %d ms\n",(unsigned int)get_timer(start));-}
-static void sdram_size_check(bd_t *bd) -{
phys_size_t total_ram_check = 0;phys_size_t ram_check = 0;phys_addr_t start = 0;int bank;/* Sanity check ensure correct SDRAM size specified */debug("DDR: Running SDRAM size sanity check\n");for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {start = bd->bi_dram[bank].start;while (ram_check < bd->bi_dram[bank].size) {ram_check += get_ram_size((void *)(start + ram_check),(phys_size_t)SZ_1G);}total_ram_check += ram_check;ram_check = 0;}/* If the ram_size is 2GB smaller, we can assume the IO space is* not mapped in. gd->ram_size is the actual size of the dram* not the accessible size.*/if (total_ram_check != gd->ram_size) {puts("DDR: SDRAM size check failed!\n");hang();}debug("DDR: SDRAM size check passed!\n");-}
-/**
- sdram_calculate_size() - Calculate SDRAM size
- Calculate SDRAM device size based on SDRAM controller parameters.
- Size is specified in bytes.
- */
-static phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) -{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &DDR_HMC_DDRIOCTRL_IOSIZE_MSK));return size;-}
/**
- sdram_mmr_init_full() - Function to initialize SDRAM MMR
- Initialize the SDRAM MMR.
*/ -static int sdram_mmr_init_full(struct udevice *dev) +int sdram_mmr_init_full(struct udevice *dev) { struct altera_sdram_platdata *plat = dev->platdata; struct altera_sdram_priv *priv = dev_get_priv(dev); @@ -534,80 +317,3 @@ static int sdram_mmr_init_full(struct udevice *dev) return 0; }
-static int altera_sdram_ofdata_to_platdata(struct udevice *dev) -{
struct altera_sdram_platdata *plat = dev->platdata;fdt_addr_t addr;addr = dev_read_addr_index(dev, 0);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->ddr_sch = (void __iomem *)addr;addr = dev_read_addr_index(dev, 1);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->iomhc = (void __iomem *)addr;addr = dev_read_addr_index(dev, 2);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->hmc = (void __iomem *)addr;return 0;-}
-static int altera_sdram_probe(struct udevice *dev) -{
int ret;struct altera_sdram_priv *priv = dev_get_priv(dev);ret = reset_get_bulk(dev, &priv->resets);if (ret) {dev_err(dev, "Can't get reset: %d\n", ret);return -ENODEV;}reset_deassert_bulk(&priv->resets);if (sdram_mmr_init_full(dev) != 0) {puts("SDRAM init failed.\n");goto failed;}return 0;-failed:
reset_release_bulk(&priv->resets);return -ENODEV;-}
-static int altera_sdram_get_info(struct udevice *dev,
struct ram_info *info)-{
struct altera_sdram_priv *priv = dev_get_priv(dev);info->base = priv->info.base;info->size = priv->info.size;return 0;-}
-static struct ram_ops altera_sdram_ops = {
.get_info = altera_sdram_get_info,-};
-static const struct udevice_id altera_sdram_ids[] = {
{ .compatible = "altr,sdr-ctl-s10" },{ /* sentinel */ }-};
-U_BOOT_DRIVER(altera_sdram) = {
.name = "altr_sdr_ctl",.id = UCLASS_RAM,.of_match = altera_sdram_ids,.ops = &altera_sdram_ops,.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),.probe = altera_sdram_probe,.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),-}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_s10.h index 096c06cba2..cca4cb35ec 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_s10.h @@ -11,48 +11,6 @@ #define DDR_READ_LATENCY_DELAY 40 #define DDR_ACTIVATE_FAWBANK 0x1
-/* ECC HMC registers */ -#define DDRIOCTRL 0x8 -#define DDRCALSTAT 0xc -#define DRAMADDRWIDTH 0xe0 -#define ECCCTRL1 0x100 -#define ECCCTRL2 0x104 -#define ERRINTEN 0x110 -#define ERRINTENS 0x114 -#define INTMODE 0x11c -#define INTSTAT 0x120 -#define AUTOWB_CORRADDR 0x138 -#define ECC_REG2WRECCDATABUS 0x144 -#define ECC_DIAGON 0x150 -#define ECC_DECSTAT 0x154 -#define HPSINTFCSEL 0x210 -#define RSTHANDSHAKECTRL 0x214 -#define RSTHANDSHAKESTAT 0x218
-#define DDR_HMC_DDRIOCTRL_IOSIZE_MSK 0x00000003 -#define DDR_HMC_DDRCALSTAT_CAL_MSK BIT(0) -#define DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK BIT(16) -#define DDR_HMC_ECCCTL_CNT_RST_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL_ECC_EN_SET_MSK BIT(0) -#define DDR_HMC_ECCCTL2_RMW_EN_SET_MSK BIT(8) -#define DDR_HMC_ECCCTL2_AWB_EN_SET_MSK BIT(0) -#define DDR_HMC_ECC_DIAGON_ECCDIAGON_EN_SET_MSK BIT(16) -#define DDR_HMC_ECC_DIAGON_WRDIAGON_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK BIT(0) -#define DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_SERRPENA_SET_MSK BIT(0) -#define DDR_HMC_INTSTAT_DERRPENA_SET_MSK BIT(1) -#define DDR_HMC_INTSTAT_ADDRMTCFLG_SET_MSK BIT(16) -#define DDR_HMC_INTMODE_INTMODE_SET_MSK BIT(0) -#define DDR_HMC_RSTHANDSHAKE_MASK 0x000000ff -#define DDR_HMC_CORE2SEQ_INT_REQ 0xF -#define DDR_HMC_SEQ2CORE_INT_RESP_MASK BIT(3) -#define DDR_HMC_HPSINTFCSEL_ENABLE_MASK 0x001f1f1f
-#define DDR_HMC_ERRINTEN_INTMASK \
(DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)/* NOC DDR scheduler */ #define DDR_SCH_ID_COREID 0 #define DDR_SCH_ID_REVID 0x4 @@ -79,110 +37,6 @@ #define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 #define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
-/* HMC MMR IO48 registers */ -#define CTRLCFG0 0x28 -#define CTRLCFG1 0x2c -#define DRAMTIMING0 0x50 -#define CALTIMING0 0x7c -#define CALTIMING1 0x80 -#define CALTIMING2 0x84 -#define CALTIMING3 0x88 -#define CALTIMING4 0x8c -#define CALTIMING9 0xa0 -#define DRAMADDRW 0xa8 -#define DRAMSTS 0xec -#define NIOSRESERVED0 0x110 -#define NIOSRESERVED1 0x114 -#define NIOSRESERVED2 0x118
-#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x) \
(((x) >> 0) & 0x1F)-#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x) \
(((x) >> 5) & 0x1F)-#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
(((x) >> 10) & 0xF)-#define DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(x) \
(((x) >> 14) & 0x3)-#define DRAMADDRW_CFG_CS_ADDR_WIDTH(x) \
(((x) >> 16) & 0x7)-#define CTRLCFG0_CFG_MEMTYPE(x) \
(((x) >> 0) & 0xF)-#define CTRLCFG0_CFG_DIMM_TYPE(x) \
(((x) >> 4) & 0x7)-#define CTRLCFG0_CFG_AC_POS(x) \
(((x) >> 7) & 0x3)-#define CTRLCFG0_CFG_CTRL_BURST_LEN(x) \
(((x) >> 9) & 0x1F)-#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
(((x) >> 0) & 0x1F)-#define CTRLCFG1_CFG_ADDR_ORDER(x) \
(((x) >> 5) & 0x3)-#define CTRLCFG1_CFG_CTRL_EN_ECC(x) \
(((x) >> 7) & 0x1)-#define DRAMTIMING0_CFG_TCL(x) \
(((x) >> 0) & 0x7F)-#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_PCH(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_ACT(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING0_CFG_ACT_TO_ACT_DB(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING1_CFG_RD_TO_WR(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING1_CFG_RD_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING2_CFG_WR_TO_WR(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING2_CFG_WR_TO_WR_DC(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING3_CFG_WR_TO_RD_DB(x) \
(((x) >> 18) & 0x3F)-#define CALTIMING3_CFG_WR_TO_PCH(x) \
(((x) >> 24) & 0x3F)-#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
(((x) >> 0) & 0x3F)-#define CALTIMING4_CFG_PCH_TO_VALID(x) \
(((x) >> 6) & 0x3F)-#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
(((x) >> 12) & 0x3F)-#define CALTIMING4_CFG_ARF_TO_VALID(x) \
(((x) >> 18) & 0xFF)-#define CALTIMING4_CFG_PDN_TO_VALID(x) \
(((x) >> 26) & 0x3F)-#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
(((x) >> 0) & 0xFF)-/* Firewall DDR scheduler MPFE */ -#define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 -#define FW_HMC_ADAPTOR_MPU_MASK BIT(0) +#include "sdram_soc64.h"
#endif /* _SDRAM_S10_H_ */ diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c new file mode 100644 index 0000000000..3097e0671c --- /dev/null +++ b/drivers/ddr/altera/sdram_soc64.c @@ -0,0 +1,304 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/system_manager.h> +#include <asm/arch/reset_manager.h> +#include <asm/io.h> +#include <linux/sizes.h>
+#define PGTABLE_OFF 0x4000
+u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg) +{
return readl(plat->iomhc + reg);+}
+u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg) +{
return readl(plat->hmc + reg);+}
+u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg)+{
return writel(data, plat->hmc + reg);+}
+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg)+{
return writel(data, plat->ddr_sch + reg);+}
+int emif_clear(struct altera_sdram_platdata *plat) +{
hmc_ecc_writel(plat, 0, RSTHANDSHAKECTRL);return wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_RSTHANDSHAKE_MASK,false, 1000, false);+}
+int emif_reset(struct altera_sdram_platdata *plat) +{
u32 c2s, s2c, ret;c2s = hmc_ecc_readl(plat, RSTHANDSHAKECTRL) & DDR_HMC_RSTHANDSHAKE_MASK;s2c = hmc_ecc_readl(plat, RSTHANDSHAKESTAT) & DDR_HMC_RSTHANDSHAKE_MASK;debug("DDR: c2s=%08x s2c=%08x nr0=%08x nr1=%08x nr2=%08x dst=%08x\n",c2s, s2c, hmc_readl(plat, NIOSRESERVED0),hmc_readl(plat, NIOSRESERVED1), hmc_readl(plat, NIOSRESERVED2),hmc_readl(plat, DRAMSTS));if (s2c && emif_clear(plat)) {printf("DDR: emif_clear() failed\n");return -1;}debug("DDR: Triggerring emif reset\n");hmc_ecc_writel(plat, DDR_HMC_CORE2SEQ_INT_REQ, RSTHANDSHAKECTRL);/* if seq2core[3] = 0, we are good */ret = wait_for_bit_le32((const void *)(plat->hmc +RSTHANDSHAKESTAT),DDR_HMC_SEQ2CORE_INT_RESP_MASK,false, 1000, false);if (ret) {printf("DDR: failed to get ack from EMIF\n");return ret;}ret = emif_clear(plat);if (ret) {printf("DDR: emif_clear() failed\n");return ret;}debug("DDR: %s triggered successly\n", __func__);return 0;+}
+int poll_hmc_clock_status(void) +{
return wait_for_bit_le32((const void *)(socfpga_sysmgr_base +SYSMGR_SOC64_HMC_CLK),SYSMGR_HMC_CLK_STATUS_MSK, true, 1000, false);+}
+void sdram_clear_mem(phys_addr_t addr, phys_size_t size) +{
phys_size_t i;if (addr % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: address 0x%llx is not cacheline size aligned.\n",addr);hang();}if (size % CONFIG_SYS_CACHELINE_SIZE) {printf("DDR: size 0x%llx is not multiple of cacheline size\n",size);hang();}/* Use DC ZVA instruction to clear memory to zeros by a cache line */for (i = 0; i < size; i = i + CONFIG_SYS_CACHELINE_SIZE) {asm volatile("dc zva, %0":: "r"(addr): "memory");addr += CONFIG_SYS_CACHELINE_SIZE;}+}
+void sdram_init_ecc_bits(bd_t *bd) +{
phys_size_t size, size_init;phys_addr_t start_addr;int bank = 0;unsigned int start = get_timer(0);icache_enable();start_addr = bd->bi_dram[0].start;size = bd->bi_dram[0].size;/* Initialize small block for page table */memset((void *)start_addr, 0, PGTABLE_SIZE + PGTABLE_OFF);gd->arch.tlb_addr = start_addr + PGTABLE_OFF;gd->arch.tlb_size = PGTABLE_SIZE;start_addr += PGTABLE_SIZE + PGTABLE_OFF;size -= (PGTABLE_OFF + PGTABLE_SIZE);dcache_enable();while (1) {while (size) {size_init = min((phys_addr_t)SZ_1G, (phys_addr_t)size);sdram_clear_mem(start_addr, size_init);size -= size_init;start_addr += size_init;WATCHDOG_RESET();}bank++;if (bank >= CONFIG_NR_DRAM_BANKS)break;start_addr = bd->bi_dram[bank].start;size = bd->bi_dram[bank].size;}dcache_disable();icache_disable();printf("SDRAM-ECC: Initialized success with %d ms\n",(unsigned int)get_timer(start));+}
+void sdram_size_check(bd_t *bd) +{
phys_size_t total_ram_check = 0;phys_size_t ram_check = 0;phys_addr_t start = 0;int bank;/* Sanity check ensure correct SDRAM size specified */debug("DDR: Running SDRAM size sanity check\n");for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {start = bd->bi_dram[bank].start;while (ram_check < bd->bi_dram[bank].size) {ram_check += get_ram_size((void *)(start + ram_check),(phys_size_t)SZ_1G);}total_ram_check += ram_check;ram_check = 0;}/* If the ram_size is 2GB smaller, we can assume the IO space is* not mapped in. gd->ram_size is the actual size of the dram* not the accessible size.*/if (total_ram_check != gd->ram_size) {puts("DDR: SDRAM size check failed!\n");hang();}debug("DDR: SDRAM size check passed!\n");+}
+/**
- sdram_calculate_size() - Calculate SDRAM size
- Calculate SDRAM device size based on SDRAM controller parameters.
- Size is specified in bytes.
- */
+phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat) +{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);phys_size_t size = 1 << (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +DRAMADDRW_CFG_COL_ADDR_WIDTH(dramaddrw));size *= (2 << (hmc_ecc_readl(plat, DDRIOCTRL) &DDR_HMC_DDRIOCTRL_IOSIZE_MSK));return size;+}
+static int altera_sdram_ofdata_to_platdata(struct udevice *dev) +{
struct altera_sdram_platdata *plat = dev->platdata;fdt_addr_t addr;addr = dev_read_addr_index(dev, 0);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->ddr_sch = (void __iomem *)addr;addr = dev_read_addr_index(dev, 1);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->iomhc = (void __iomem *)addr;addr = dev_read_addr_index(dev, 2);if (addr == FDT_ADDR_T_NONE)return -EINVAL;plat->hmc = (void __iomem *)addr;return 0;+}
+static int altera_sdram_probe(struct udevice *dev) +{
int ret;struct altera_sdram_priv *priv = dev_get_priv(dev);ret = reset_get_bulk(dev, &priv->resets);if (ret) {dev_err(dev, "Can't get reset: %d\n", ret);return -ENODEV;}reset_deassert_bulk(&priv->resets);if (sdram_mmr_init_full(dev) != 0) {puts("SDRAM init failed.\n");goto failed;}return 0;+failed:
reset_release_bulk(&priv->resets);return -ENODEV;+}
+static int altera_sdram_get_info(struct udevice *dev,
struct ram_info *info)+{
struct altera_sdram_priv *priv = dev_get_priv(dev);info->base = priv->info.base;info->size = priv->info.size;return 0;+}
+static struct ram_ops altera_sdram_ops = {
.get_info = altera_sdram_get_info,+};
+static const struct udevice_id altera_sdram_ids[] = {
{ .compatible = "altr,sdr-ctl-s10" },{ .compatible = "intel,sdr-ctl-agilex" },{ /* sentinel */ }+};
+U_BOOT_DRIVER(altera_sdram) = {
.name = "altr_sdr_ctl",.id = UCLASS_RAM,.of_match = altera_sdram_ids,.ops = &altera_sdram_ops,.ofdata_to_platdata = altera_sdram_ofdata_to_platdata,.platdata_auto_alloc_size = sizeof(struct altera_sdram_platdata),.probe = altera_sdram_probe,.priv_auto_alloc_size = sizeof(struct altera_sdram_priv),+}; diff --git a/drivers/ddr/altera/sdram_s10.h b/drivers/ddr/altera/sdram_soc64.h similarity index 79% copy from drivers/ddr/altera/sdram_s10.h copy to drivers/ddr/altera/sdram_soc64.h index 096c06cba2..7d018e76d8 100644 --- a/drivers/ddr/altera/sdram_s10.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -1,15 +1,24 @@ -/* SPDX-License-Identifier: GPL-2.0
- Copyright (C) 2017-2018 Intel Corporation <www.intel.com>
+/* SPDX-License-Identifier: GPL-2.0 */ +/*
*/
- Copyright (C) 2017-2019 Intel Corporation <www.intel.com>
-#ifndef _SDRAM_S10_H_ -#define _SDRAM_S10_H_ +#ifndef _SDRAM_SOC64_H_ +#define _SDRAM_SOC64_H_
-#define DDR_TWR 15 -#define DDR_READ_LATENCY_DELAY 40 -#define DDR_ACTIVATE_FAWBANK 0x1 +#include <common.h> +#include <linux/sizes.h>
+struct altera_sdram_priv {
struct ram_info info;struct reset_ctl_bulk resets;+};
+struct altera_sdram_platdata {
void __iomem *hmc;void __iomem *ddr_sch;void __iomem *iomhc;+};
/* ECC HMC registers */ #define DDRIOCTRL 0x8 @@ -53,32 +62,6 @@ (DDR_HMC_ERRINTEN_SERRINTEN_EN_SET_MSK | \ DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK)
-/* NOC DDR scheduler */ -#define DDR_SCH_ID_COREID 0 -#define DDR_SCH_ID_REVID 0x4 -#define DDR_SCH_DDRCONF 0x8 -#define DDR_SCH_DDRTIMING 0xc -#define DDR_SCH_DDRMODE 0x10 -#define DDR_SCH_READ_LATENCY 0x14 -#define DDR_SCH_ACTIVATE 0x38 -#define DDR_SCH_DEVTODEV 0x3c -#define DDR_SCH_DDR4TIMING 0x40
-#define DDR_SCH_DDRTIMING_ACTTOACT_OFF 0 -#define DDR_SCH_DDRTIMING_RDTOMISS_OFF 6 -#define DDR_SCH_DDRTIMING_WRTOMISS_OFF 12 -#define DDR_SCH_DDRTIMING_BURSTLEN_OFF 18 -#define DDR_SCH_DDRTIMING_RDTOWR_OFF 21 -#define DDR_SCH_DDRTIMING_WRTORD_OFF 26 -#define DDR_SCH_DDRTIMING_BWRATIO_OFF 31 -#define DDR_SCH_DDRMOD_BWRATIOEXTENDED_OFF 1 -#define DDR_SCH_ACTIVATE_RRD_OFF 0 -#define DDR_SCH_ACTIVATE_FAW_OFF 4 -#define DDR_SCH_ACTIVATE_FAWBANK_OFF 10 -#define DDR_SCH_DEVTODEV_BUSRDTORD_OFF 0 -#define DDR_SCH_DEVTODEV_BUSRDTOWR_OFF 2 -#define DDR_SCH_DEVTODEV_BUSWRTORD_OFF 4
/* HMC MMR IO48 registers */ #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c @@ -185,4 +168,19 @@ #define FW_HMC_ADAPTOR_REG_ADDR 0xf8020004 #define FW_HMC_ADAPTOR_MPU_MASK BIT(0)
-#endif /* _SDRAM_S10_H_ */ +u32 hmc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_readl(struct altera_sdram_platdata *plat, u32 reg); +u32 hmc_ecc_writel(struct altera_sdram_platdata *plat,
u32 data, u32 reg);+u32 ddr_sch_writel(struct altera_sdram_platdata *plat, u32 data,
u32 reg);+int emif_clear(struct altera_sdram_platdata *plat); +int emif_reset(struct altera_sdram_platdata *plat); +int poll_hmc_clock_status(void); +void sdram_clear_mem(phys_addr_t addr, phys_size_t size); +void sdram_init_ecc_bits(bd_t *bd); +void sdram_size_check(bd_t *bd); +phys_size_t sdram_calculate_size(struct altera_sdram_platdata *plat); +int sdram_mmr_init_full(struct udevice *dev);
+#endif /* _SDRAM_SOC64_H_ */
2.19.0
Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Fixed checkpatch warnings
v3: - Use sdmmc_soc64.* - Change compatible string to use "intel" (intel,sdr-ctl-agilex). - Improve error handing if DDR size mismatched. --- drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_agilex.c | 168 ++++++++++++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.h | 1 + 4 files changed, 173 insertions(+), 3 deletions(-) create mode 100644 drivers/ddr/altera/sdram_agilex.c
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b1c1be3b5..8f590dc5f6 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL - depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 - select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 - select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX + select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX help Enable DDR SDRAM controller for the SoCFPGA devices. diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index eb8da13b7d..39dfee5d5a 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o endif diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c new file mode 100644 index 0000000000..cc7679a6e4 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <linux/sizes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int sdram_mmr_init_full(struct udevice *dev) +{ + struct altera_sdram_platdata *plat = dev->platdata; + struct altera_sdram_priv *priv = dev_get_priv(dev); + u32 i; + int ret; + phys_size_t hw_size; + bd_t bd = {0}; + + /* Ensure HMC clock is running */ + if (poll_hmc_clock_status()) { + debug("DDR: Error as HMC clock was not running\n"); + return -EPERM; + } + + /* Trying 3 times to do a calibration */ + for (i = 0; i < 3; i++) { + ret = wait_for_bit_le32((const void *)(plat->hmc + + DDRCALSTAT), + DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000, + false); + if (!ret) + break; + + emif_reset(plat); + } + + if (ret) { + puts("DDR: Error as SDRAM calibration failed\n"); + return -EPERM; + } + debug("DDR: Calibration success\n"); + + /* + * Configure the DDR IO size + * niosreserve0: Used to indicate DDR width & + * bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit) + * bit[8] = 1 if user-mode OCT is present + * bit[9] = 1 if warm reset compiled into EMIF Cal Code + * bit[10] = 1 if warm reset is on during generation in EMIF Cal + * niosreserve1: IP ADCDS version encoded as 16 bit value + * bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta, + * 3=EAP, 4-6 are reserved) + * bit[5:3] = Service Pack # (e.g. 1) + * bit[9:6] = Minor Release # + * bit[14:10] = Major Release # + */ + /* Configure DDR IO size x16, x32 and x64 mode */ + u32 update_value; + + update_value = hmc_readl(plat, NIOSRESERVED0); + update_value = (update_value & 0xFF) >> 5; + + /* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */ + update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4); + hmc_ecc_writel(plat, update_value, DDRIOCTRL); + + /* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */ + hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH); + + /* assigning the SDRAM size */ + phys_size_t size = sdram_calculate_size(plat); + + if (size <= 0) + hw_size = PHYS_SDRAM_1_SIZE; + else + hw_size = size; + + /* Get bank configuration from devicetree */ + ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL, + (phys_size_t *)&gd->ram_size, &bd); + if (ret) { + puts("DDR: Failed to decode memory node\n"); + return -ENXIO; + } + + if (gd->ram_size != hw_size) { + printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n", + gd->ram_size >> 20); + printf(" mismatch with hardware (%lld MiB).\n", + hw_size >> 20); + } + + if (gd->ram_size > hw_size) { + printf("DDR: Error: DRAM size from device tree is greater\n"); + printf(" than hardware size.\n"); + hang(); + } + + printf("DDR: %lld MiB\n", gd->ram_size >> 20); + + /* This enables nonsecure access to DDR */ + /* mpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, + FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT); + FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT); + + /* nonmpuregion0addr_limit */ + FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1, + FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT); + + /* Enable mpuregion0enable and nonmpuregion0enable */ + FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE, + FW_MPU_DDR_SCR_EN_SET); + + u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1); + + /* Enable or disable the DDR ECC */ + if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) { + setbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK)); + setbits_le32(plat->hmc + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + setbits_le32(plat->hmc + ERRINTEN, + DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK); + + /* Enable non-secure writes to HMC Adapter for SDRAM ECC */ + writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR); + + if (!cpu_has_been_warmreset()) + sdram_init_ecc_bits(&bd); + } else { + clrbits_le32(plat->hmc + ECCCTRL1, + (DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_CNT_RST_SET_MSK | + DDR_HMC_ECCCTL_ECC_EN_SET_MSK)); + clrbits_le32(plat->hmc + ECCCTRL2, + (DDR_HMC_ECCCTL2_RMW_EN_SET_MSK | + DDR_HMC_ECCCTL2_AWB_EN_SET_MSK)); + } + + sdram_size_check(&bd); + + priv->info.base = bd.bi_dram[0].start; + priv->info.size = gd->ram_size; + + debug("DDR: HMC init success\n"); + return 0; +} diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7d018e76d8..7b25a80ae2 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -65,6 +65,7 @@ struct altera_sdram_platdata { /* HMC MMR IO48 registers */ #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c +#define CTRLCFG3 0x34 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c #define CALTIMING1 0x80
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add SDRAM driver for Agilex SoC.
Signed-off-by: Tien Fong Chee tien.fong.chee@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Fixed checkpatch warnings
v3:
- Use sdmmc_soc64.*
- Change compatible string to use "intel" (intel,sdr-ctl-agilex).
- Improve error handing if DDR size mismatched.
drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 1 + drivers/ddr/altera/sdram_agilex.c | 168 ++++++++++++++++++++++++++++++ drivers/ddr/altera/sdram_soc64.h | 1 + 4 files changed, 173 insertions(+), 3 deletions(-) create mode 100644 drivers/ddr/altera/sdram_agilex.c
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig index 2b1c1be3b5..8f590dc5f6 100644 --- a/drivers/ddr/altera/Kconfig +++ b/drivers/ddr/altera/Kconfig @@ -1,8 +1,8 @@ config SPL_ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver in SPL" depends on SPL
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10select RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10select SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEXselect RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEXselect SPL_RAM if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX help Enable DDR SDRAM controller for the SoCFPGA devices.diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index eb8da13b7d..39dfee5d5a 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -10,4 +10,5 @@ ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o endif diff --git a/drivers/ddr/altera/sdram_agilex.c b/drivers/ddr/altera/sdram_agilex.c new file mode 100644 index 0000000000..cc7679a6e4 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex.c @@ -0,0 +1,168 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+#include <common.h> +#include <dm.h> +#include <errno.h> +#include <div64.h> +#include <fdtdec.h> +#include <ram.h> +#include <reset.h> +#include "sdram_soc64.h" +#include <wait_bit.h> +#include <asm/arch/firewall.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <asm/io.h> +#include <linux/sizes.h>
+DECLARE_GLOBAL_DATA_PTR;
+int sdram_mmr_init_full(struct udevice *dev) +{
struct altera_sdram_platdata *plat = dev->platdata;struct altera_sdram_priv *priv = dev_get_priv(dev);u32 i;int ret;phys_size_t hw_size;bd_t bd = {0};/* Ensure HMC clock is running */if (poll_hmc_clock_status()) {debug("DDR: Error as HMC clock was not running\n");return -EPERM;}/* Trying 3 times to do a calibration */for (i = 0; i < 3; i++) {ret = wait_for_bit_le32((const void *)(plat->hmc +DDRCALSTAT),DDR_HMC_DDRCALSTAT_CAL_MSK, true, 1000,false);if (!ret)break;emif_reset(plat);}if (ret) {puts("DDR: Error as SDRAM calibration failed\n");return -EPERM;}debug("DDR: Calibration success\n");/** Configure the DDR IO size* niosreserve0: Used to indicate DDR width &* bit[7:0] = Number of data bits (bit[6:5] 0x01=32bit, 0x10=64bit)* bit[8] = 1 if user-mode OCT is present* bit[9] = 1 if warm reset compiled into EMIF Cal Code* bit[10] = 1 if warm reset is on during generation in EMIF Cal* niosreserve1: IP ADCDS version encoded as 16 bit value* bit[2:0] = Variant (0=not special,1=FAE beta, 2=Customer beta,* 3=EAP, 4-6 are reserved)* bit[5:3] = Service Pack # (e.g. 1)* bit[9:6] = Minor Release #* bit[14:10] = Major Release #*//* Configure DDR IO size x16, x32 and x64 mode */u32 update_value;update_value = hmc_readl(plat, NIOSRESERVED0);update_value = (update_value & 0xFF) >> 5;/* Configure DDR data rate 0-HAlf-rate 1-Quarter-rate */update_value |= (hmc_readl(plat, CTRLCFG3) & 0x4);hmc_ecc_writel(plat, update_value, DDRIOCTRL);/* Copy values MMR IOHMC dramaddrw to HMC adp DRAMADDRWIDTH */hmc_ecc_writel(plat, hmc_readl(plat, DRAMADDRW), DRAMADDRWIDTH);/* assigning the SDRAM size */phys_size_t size = sdram_calculate_size(plat);if (size <= 0)hw_size = PHYS_SDRAM_1_SIZE;elsehw_size = size;/* Get bank configuration from devicetree */ret = fdtdec_decode_ram_size(gd->fdt_blob, NULL, 0, NULL,(phys_size_t *)&gd->ram_size, &bd);if (ret) {puts("DDR: Failed to decode memory node\n");return -ENXIO;}if (gd->ram_size != hw_size) {printf("DDR: Warning: DRAM size from device tree (%lld MiB)\n",gd->ram_size >> 20);printf(" mismatch with hardware (%lld MiB).\n",hw_size >> 20);}if (gd->ram_size > hw_size) {printf("DDR: Error: DRAM size from device tree is greater\n");printf(" than hardware size.\n");hang();}printf("DDR: %lld MiB\n", gd->ram_size >> 20);/* This enables nonsecure access to DDR *//* mpuregion0addr_limit */FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT);FW_MPU_DDR_SCR_WRITEL(0x1F, FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT);/* nonmpuregion0addr_limit */FW_MPU_DDR_SCR_WRITEL(gd->ram_size - 1,FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT);/* Enable mpuregion0enable and nonmpuregion0enable */FW_MPU_DDR_SCR_WRITEL(MPUREGION0_ENABLE | NONMPUREGION0_ENABLE,FW_MPU_DDR_SCR_EN_SET);u32 ctrlcfg1 = hmc_readl(plat, CTRLCFG1);/* Enable or disable the DDR ECC */if (CTRLCFG1_CFG_CTRL_EN_ECC(ctrlcfg1)) {setbits_le32(plat->hmc + ECCCTRL1,(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |DDR_HMC_ECCCTL_CNT_RST_SET_MSK |DDR_HMC_ECCCTL_ECC_EN_SET_MSK));clrbits_le32(plat->hmc + ECCCTRL1,(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |DDR_HMC_ECCCTL_CNT_RST_SET_MSK));setbits_le32(plat->hmc + ECCCTRL2,(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));setbits_le32(plat->hmc + ERRINTEN,DDR_HMC_ERRINTEN_DERRINTEN_EN_SET_MSK);/* Enable non-secure writes to HMC Adapter for SDRAM ECC */writel(FW_HMC_ADAPTOR_MPU_MASK, FW_HMC_ADAPTOR_REG_ADDR);if (!cpu_has_been_warmreset())sdram_init_ecc_bits(&bd);} else {clrbits_le32(plat->hmc + ECCCTRL1,(DDR_HMC_ECCCTL_AWB_CNT_RST_SET_MSK |DDR_HMC_ECCCTL_CNT_RST_SET_MSK |DDR_HMC_ECCCTL_ECC_EN_SET_MSK));clrbits_le32(plat->hmc + ECCCTRL2,(DDR_HMC_ECCCTL2_RMW_EN_SET_MSK |DDR_HMC_ECCCTL2_AWB_EN_SET_MSK));}sdram_size_check(&bd);priv->info.base = bd.bi_dram[0].start;priv->info.size = gd->ram_size;debug("DDR: HMC init success\n");return 0;+} diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h index 7d018e76d8..7b25a80ae2 100644 --- a/drivers/ddr/altera/sdram_soc64.h +++ b/drivers/ddr/altera/sdram_soc64.h @@ -65,6 +65,7 @@ struct altera_sdram_platdata { /* HMC MMR IO48 registers */ #define CTRLCFG0 0x28 #define CTRLCFG1 0x2c +#define CTRLCFG3 0x34 #define DRAMTIMING0 0x50 #define CALTIMING0 0x7c
#define CALTIMING1 0x80
2.19.0
Add socdk board support for Intel Agilex SoC
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- board/intel/agilex-socdk/MAINTAINERS | 7 +++++++ board/intel/agilex-socdk/Makefile | 7 +++++++ board/intel/agilex-socdk/socfpga.c | 7 +++++++ 3 files changed, 21 insertions(+) create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c
diff --git a/board/intel/agilex-socdk/MAINTAINERS b/board/intel/agilex-socdk/MAINTAINERS new file mode 100644 index 0000000000..b8e28f0b24 --- /dev/null +++ b/board/intel/agilex-socdk/MAINTAINERS @@ -0,0 +1,7 @@ +SOCFPGA BOARD +M: Ley Foon Tan ley.foon.tan@intel.com +M: Chee Hong Ang chee.hong.ang@intel.com +S: Maintained +F: board/intel/agilex-socdk/ +F: include/configs/socfpga_agilex_socdk.h +F: configs/socfpga_agilex_defconfig diff --git a/board/intel/agilex-socdk/Makefile b/board/intel/agilex-socdk/Makefile new file mode 100644 index 0000000000..b86223a571 --- /dev/null +++ b/board/intel/agilex-socdk/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o diff --git a/board/intel/agilex-socdk/socfpga.c b/board/intel/agilex-socdk/socfpga.c new file mode 100644 index 0000000000..72a3e0836d --- /dev/null +++ b/board/intel/agilex-socdk/socfpga.c @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <common.h>
Add SPL support for Agilex SoC.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
--- v4: - Move spl_early_init() to entry of board_init_f - Add socfpga_get_manager_addr(). - Remove SYSMGR_DMA and SYSMGR_DMA_PERIPH, already set in firewall_setup().
v2: - Change clock driver probing to DM. - Remove unused OSC1TIMER0 reset - Remove debug_uart_init(). UART depends on clock driver setup, no point to call debug_uart_init() after spl_early_init() and clock driver initialization. --- arch/arm/mach-socfpga/Makefile | 1 + arch/arm/mach-socfpga/spl_agilex.c | 95 ++++++++++++++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 arch/arm/mach-socfpga/spl_agilex.c
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 6f39dc06ed..9d334e9e1b 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -60,6 +60,7 @@ obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += ccu_agilex.o +obj-y += spl_agilex.o endif endif
diff --git a/arch/arm/mach-socfpga/spl_agilex.c b/arch/arm/mach-socfpga/spl_agilex.c new file mode 100644 index 0000000000..c05954664d --- /dev/null +++ b/arch/arm/mach-socfpga/spl_agilex.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#include <asm/io.h> +#include <asm/u-boot.h> +#include <asm/utils.h> +#include <common.h> +#include <image.h> +#include <spl.h> +#include <asm/arch/ccu_agilex.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/firewall.h> +#include <asm/arch/mailbox_s10.h> +#include <asm/arch/misc.h> +#include <asm/arch/reset_manager.h> +#include <asm/arch/system_manager.h> +#include <watchdog.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_MMC_SUPPORT +u32 spl_boot_mode(const u32 boot_device) +{ +#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) + return MMCSD_MODE_FS; +#else + return MMCSD_MODE_RAW; +#endif +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + struct udevice *dev; + + ret = spl_early_init(); + if (ret) + hang(); + + socfpga_get_manager_addr(); + +#ifdef CONFIG_HW_WATCHDOG + /* Ensure watchdog is paused when debugging is happening */ + writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, + socfpga_sysmgr_base + SYSMGR_SOC64_WDDBG); + + /* Enable watchdog before initializing the HW */ + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1); + socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0); + hw_watchdog_init(); +#endif + + /* ensure all processors are not released prior Linux boot */ + writeq(0, CPU_RELEASE_ADDR); + + timer_init(); + + sysmgr_pinmux_init(); + + ret = uclass_get_device(UCLASS_CLK, 0, &dev); + if (ret) { + debug("Clock init failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + cm_print_clock_quick_summary(); + + firewall_setup(); + ccu_init(); + +#if CONFIG_IS_ENABLED(ALTERA_SDRAM) + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + hang(); + } +#endif + + mbox_init(); + +#ifdef CONFIG_CADENCE_QSPI + mbox_qspi_open(); +#endif +}
Add device tree files for Agilex SoC platform.
Based on Linux Commit ID 4b36daf9ada30.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
--- v4: - Add u-boot,dm-pre-reloc to sysmgr node.
v3: - Fixed bank 1 memory alias base address to 0x280000000. - Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK. - Include socfpga-soc64-clock.h - Change to "intel,sdr-ctl-agilex" for SDRAM node.
v2: - Add clock property to device node. - Change memory size to 8GB - Enable i2c1 --- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 ++++++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 75 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 +++++ 4 files changed, 707 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aac1b83d49..de79635f34 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -308,6 +308,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \ + socfpga_agilex_socdk.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \ diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi new file mode 100644 index 0000000000..a5732f29db --- /dev/null +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + */ + +/dts-v1/; +#include <dt-bindings/clock/socfpga-soc64-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/altr,rst-mgr-s10.h> + +/ { + compatible = "intel,socfpga-agilex"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x0>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x1>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + enable-method = "psci"; + reg = <0x3>; + }; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <0 120 8>, + <0 121 8>, + <0 122 8>, + <0 123 8>; + interrupt-affinity = <&cpu0>, + <&cpu1>, + <&cpu2>, + <&cpu3>; + interrupt-parent = <&intc>; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + intc: intc@fffc1000 { + compatible = "arm,gic-400", "arm,cortex-a15-gic"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0xfffc1000 0x0 0x1000>, + <0x0 0xfffc2000 0x0 0x2000>, + <0x0 0xfffc4000 0x0 0x2000>, + <0x0 0xfffc6000 0x0 0x2000>; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + device_type = "soc"; + interrupt-parent = <&intc>; + ranges = <0 0 0 0xffffffff>; + + clkmgr: clock-controller@ffd10000 { + compatible = "intel,agilex-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; + + gmac0: ethernet@ff800000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff800000 0x2000>; + interrupts = <0 90 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr SOCFPGA_SOC64_EMAC0_CLK>; + clock-names = "stmmaceth"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 1>; + altr,sysmgr-syscon = <&sysmgr 0x44 0>; + status = "disabled"; + }; + + gmac1: ethernet@ff802000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff802000 0x2000>; + interrupts = <0 91 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr SOCFPGA_SOC64_EMAC1_CLK>; + clock-names = "stmmaceth"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 2>; + altr,sysmgr-syscon = <&sysmgr 0x48 0>; + status = "disabled"; + }; + + gmac2: ethernet@ff804000 { + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; + reg = <0xff804000 0x2000>; + interrupts = <0 92 4>; + interrupt-names = "macirq"; + mac-address = [00 00 00 00 00 00]; + resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; + reset-names = "stmmaceth", "stmmaceth-ocp"; + clocks = <&clkmgr SOCFPGA_SOC64_EMAC2_CLK>; + clock-names = "stmmaceth"; + tx-fifo-depth = <16384>; + rx-fifo-depth = <16384>; + snps,multicast-filter-bins = <256>; + iommus = <&smmu 3>; + altr,sysmgr-syscon = <&sysmgr 0x4c 0>; + status = "disabled"; + }; + + gpio0: gpio@ffc03200 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03200 0x100>; + resets = <&rst GPIO0_RESET>; + status = "disabled"; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 110 4>; + }; + }; + + gpio1: gpio@ffc03300 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dw-apb-gpio"; + reg = <0xffc03300 0x100>; + resets = <&rst GPIO1_RESET>; + status = "disabled"; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + snps,nr-gpios = <24>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <0 111 4>; + }; + }; + + i2c0: i2c@ffc02800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02800 0x100>; + interrupts = <0 103 4>; + resets = <&rst I2C0_RESET>; + reset-names = "i2c"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + i2c1: i2c@ffc02900 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02900 0x100>; + interrupts = <0 104 4>; + resets = <&rst I2C1_RESET>; + reset-names = "i2c"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + i2c2: i2c@ffc02a00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02a00 0x100>; + interrupts = <0 105 4>; + resets = <&rst I2C2_RESET>; + reset-names = "i2c"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + i2c3: i2c@ffc02b00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02b00 0x100>; + interrupts = <0 106 4>; + resets = <&rst I2C3_RESET>; + reset-names = "i2c"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + i2c4: i2c@ffc02c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,designware-i2c"; + reg = <0xffc02c00 0x100>; + interrupts = <0 107 4>; + resets = <&rst I2C4_RESET>; + reset-names = "i2c"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + mmc: dwmmc0@ff808000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-dw-mshc"; + reg = <0xff808000 0x1000>; + interrupts = <0 96 4>; + fifo-depth = <0x400>; + resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>; + reset-names = "reset", "sdmmc-ocp"; + clocks = <&clkmgr SOCFPGA_SOC64_L4_MP_CLK>, + <&clkmgr SOCFPGA_SOC64_SDMMC_CLK>; + clock-names = "biu", "ciu"; + iommus = <&smmu 5>; + status = "disabled"; + }; + + ocram: sram@ffe00000 { + compatible = "mmio-sram"; + reg = <0xffe00000 0x40000>; + }; + + pdma: pdma@ffda0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xffda0000 0x1000>; + interrupts = <0 81 4>, + <0 82 4>, + <0 83 4>, + <0 84 4>, + <0 85 4>, + <0 86 4>, + <0 87 4>, + <0 88 4>, + <0 89 4>; + #dma-cells = <1>; + #dma-channels = <8>; + #dma-requests = <32>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>; + clock-names = "apb_pclk"; + }; + + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + status = "disabled"; + }; + + rst: rstmgr@ffd11000 { + #reset-cells = <1>; + compatible = "altr,rst-mgr"; + reg = <0xffd11000 0x100>; + altr,modrst-offset = <0x20>; + }; + + smmu: iommu@fa000000 { + compatible = "arm,mmu-500", "arm,smmu-v2"; + reg = <0xfa000000 0x40000>; + #global-interrupts = <2>; + #iommu-cells = <1>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>; + clock-names = "iommu"; + interrupt-parent = <&intc>; + interrupts = <0 128 4>, /* Global Secure Fault */ + <0 129 4>, /* Global Non-secure Fault */ + /* Non-secure Context Interrupts (32) */ + <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, + <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, + <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, + <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, + <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, + <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, + <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, + <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; + stream-match-mask = <0x7ff0>; + status = "disabled"; + }; + + spi0: spi@ffda4000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda4000 0x1000>; + interrupts = <0 99 4>; + resets = <&rst SPIM0_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>; + status = "disabled"; + }; + + spi1: spi@ffda5000 { + compatible = "snps,dw-apb-ssi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xffda5000 0x1000>; + interrupts = <0 100 4>; + resets = <&rst SPIM1_RESET>; + reg-io-width = <4>; + num-cs = <4>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>; + status = "disabled"; + }; + + sysmgr: sysmgr@ffd12000 { + compatible = "altr,sys-mgr", "syscon"; + reg = <0xffd12000 0x500>; + }; + + /* Local timer */ + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 13 0xf08>, + <1 14 0xf08>, + <1 11 0xf08>, + <1 10 0xf08>; + }; + + timer0: timer0@ffc03000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 113 4>; + reg = <0xffc03000 0x100>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer1: timer1@ffc03100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 114 4>; + reg = <0xffc03100 0x100>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer2: timer2@ffd00000 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 115 4>; + reg = <0xffd00000 0x100>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + clock-names = "timer"; + }; + + timer3: timer3@ffd00100 { + compatible = "snps,dw-apb-timer"; + interrupts = <0 116 4>; + reg = <0xffd00100 0x100>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + clock-names = "timer"; + }; + + uart0: serial0@ffc02000 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02000 0x100>; + interrupts = <0 108 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART0_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + uart1: serial1@ffc02100 { + compatible = "snps,dw-apb-uart"; + reg = <0xffc02100 0x100>; + interrupts = <0 109 4>; + reg-shift = <2>; + reg-io-width = <4>; + resets = <&rst UART1_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>; + status = "disabled"; + }; + + usbphy0: usbphy@0 { + #phy-cells = <0>; + compatible = "usb-nop-xceiv"; + status = "okay"; + }; + + usb0: usb@ffb00000 { + compatible = "snps,dwc2"; + reg = <0xffb00000 0x40000>; + interrupts = <0 93 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr SOCFPGA_SOC64_USB_CLK>; + iommus = <&smmu 6>; + status = "disabled"; + }; + + usb1: usb@ffb40000 { + compatible = "snps,dwc2"; + reg = <0xffb40000 0x40000>; + interrupts = <0 94 4>; + phys = <&usbphy0>; + phy-names = "usb2-phy"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "dwc2", "dwc2-ecc"; + clocks = <&clkmgr SOCFPGA_SOC64_USB_CLK>; + iommus = <&smmu 7>; + status = "disabled"; + }; + + watchdog0: watchdog@ffd00200 { + compatible = "snps,dw-wdt"; + reg = <0xffd00200 0x100>; + interrupts = <0 117 4>; + resets = <&rst WATCHDOG0_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog1: watchdog@ffd00300 { + compatible = "snps,dw-wdt"; + reg = <0xffd00300 0x100>; + interrupts = <0 118 4>; + resets = <&rst WATCHDOG1_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog2: watchdog@ffd00400 { + compatible = "snps,dw-wdt"; + reg = <0xffd00400 0x100>; + interrupts = <0 125 4>; + resets = <&rst WATCHDOG2_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + watchdog3: watchdog@ffd00500 { + compatible = "snps,dw-wdt"; + reg = <0xffd00500 0x100>; + interrupts = <0 126 4>; + resets = <&rst WATCHDOG3_RESET>; + clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>; + status = "disabled"; + }; + + sdr: sdr@f8011100 { + compatible = "altr,sdr-ctl", "syscon"; + reg = <0xf8011100 0xc0>; + }; + }; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi new file mode 100644 index 0000000000..723fe1e0c8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +/{ + aliases { + spi0 = &qspi; + }; + + memory { + u-boot,dm-pre-reloc; + }; + + soc { + u-boot,dm-pre-reloc; + }; +}; + +&clkmgr { + u-boot,dm-pre-reloc; +}; + +&flash0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <100000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; +}; + +&mmc { + drvsel = <3>; + smplsel = <0>; + u-boot,dm-pre-reloc; +}; + +&porta { + bank-name = "porta"; +}; + +&portb { + bank-name = "portb"; +}; + +&qspi { + u-boot,dm-pre-reloc; +}; + +&rst { + u-boot,dm-pre-reloc; +}; + +&sdr { + compatible = "intel,sdr-ctl-agilex"; + reg = <0xf8000400 0x80>, + <0xf8010000 0x190>, + <0xf8011000 0x500>; + resets = <&rst DDRSCH_RESET>; + u-boot,dm-pre-reloc; +}; + +&sysmgr { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&watchdog0 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts new file mode 100644 index 0000000000..7e653932e8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation + */ + +#include "socfpga_agilex.dtsi" + +/ { + model = "SoCFPGA Agilex SoCDK"; + + aliases { + ethernet0 = &gmac0; + i2c0 = &i2c1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* 8GB */ + reg = <0 0x00000000 0 0x80000000>, + <2 0x80000000 1 0x80000000>; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac0 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <3800>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <1860>; /* 960ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + status = "okay"; + cap-sd-highspeed; + cap-mmc-highspeed; + broken-cd; + bus-width = <4>; +}; + +&qspi { + status = "okay"; + + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <50000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x4000000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x4000000 0x4000000>; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +};
On Thu, Sep 12, 2019 at 12:12 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add device tree files for Agilex SoC platform.
Based on Linux Commit ID 4b36daf9ada30.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
v4:
- Add u-boot,dm-pre-reloc to sysmgr node.
v3:
- Fixed bank 1 memory alias base address to 0x280000000.
- Rename STRATIX10_*_CLK to SOCFPGA_SOC64_*_CLK.
- Include socfpga-soc64-clock.h
- Change to "intel,sdr-ctl-agilex" for SDRAM node.
v2:
- Add clock property to device node.
- Change memory size to 8GB
- Enable i2c1
arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 ++++++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 75 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 +++++ 4 files changed, 707 insertions(+) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index aac1b83d49..de79635f34 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -308,6 +308,7 @@ dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_THUNDERX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \ socfpga_arria5_socdk.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ socfpga_cyclone5_mcvevk.dtb \diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_agilex.dtsi new file mode 100644 index 0000000000..a5732f29db --- /dev/null +++ b/arch/arm/dts/socfpga_agilex.dtsi @@ -0,0 +1,495 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation
- */
+/dts-v1/; +#include <dt-bindings/clock/socfpga-soc64-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+/ {
compatible = "intel,socfpga-agilex";#address-cells = <2>;#size-cells = <2>;cpus {#address-cells = <1>;#size-cells = <0>;cpu0: cpu@0 {compatible = "arm,cortex-a53";device_type = "cpu";enable-method = "psci";reg = <0x0>;};cpu1: cpu@1 {compatible = "arm,cortex-a53";device_type = "cpu";enable-method = "psci";reg = <0x1>;};cpu2: cpu@2 {compatible = "arm,cortex-a53";device_type = "cpu";enable-method = "psci";reg = <0x2>;};cpu3: cpu@3 {compatible = "arm,cortex-a53";device_type = "cpu";enable-method = "psci";reg = <0x3>;};};pmu {compatible = "arm,armv8-pmuv3";interrupts = <0 120 8>,<0 121 8>,<0 122 8>,<0 123 8>;interrupt-affinity = <&cpu0>,<&cpu1>,<&cpu2>,<&cpu3>;interrupt-parent = <&intc>;};psci {compatible = "arm,psci-0.2";method = "smc";};intc: intc@fffc1000 {compatible = "arm,gic-400", "arm,cortex-a15-gic";#interrupt-cells = <3>;interrupt-controller;reg = <0x0 0xfffc1000 0x0 0x1000>,<0x0 0xfffc2000 0x0 0x2000>,<0x0 0xfffc4000 0x0 0x2000>,<0x0 0xfffc6000 0x0 0x2000>;};soc {#address-cells = <1>;#size-cells = <1>;compatible = "simple-bus";device_type = "soc";interrupt-parent = <&intc>;ranges = <0 0 0 0xffffffff>;clkmgr: clock-controller@ffd10000 {compatible = "intel,agilex-clkmgr";reg = <0xffd10000 0x1000>;#clock-cells = <1>;};gmac0: ethernet@ff800000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";reg = <0xff800000 0x2000>;interrupts = <0 90 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;reset-names = "stmmaceth", "stmmaceth-ocp";clocks = <&clkmgr SOCFPGA_SOC64_EMAC0_CLK>;clock-names = "stmmaceth";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 1>;altr,sysmgr-syscon = <&sysmgr 0x44 0>;status = "disabled";};gmac1: ethernet@ff802000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";reg = <0xff802000 0x2000>;interrupts = <0 91 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;reset-names = "stmmaceth", "stmmaceth-ocp";clocks = <&clkmgr SOCFPGA_SOC64_EMAC1_CLK>;clock-names = "stmmaceth";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 2>;altr,sysmgr-syscon = <&sysmgr 0x48 0>;status = "disabled";};gmac2: ethernet@ff804000 {compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";reg = <0xff804000 0x2000>;interrupts = <0 92 4>;interrupt-names = "macirq";mac-address = [00 00 00 00 00 00];resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;reset-names = "stmmaceth", "stmmaceth-ocp";clocks = <&clkmgr SOCFPGA_SOC64_EMAC2_CLK>;clock-names = "stmmaceth";tx-fifo-depth = <16384>;rx-fifo-depth = <16384>;snps,multicast-filter-bins = <256>;iommus = <&smmu 3>;altr,sysmgr-syscon = <&sysmgr 0x4c 0>;status = "disabled";};gpio0: gpio@ffc03200 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0xffc03200 0x100>;resets = <&rst GPIO0_RESET>;status = "disabled";porta: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 110 4>;};};gpio1: gpio@ffc03300 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dw-apb-gpio";reg = <0xffc03300 0x100>;resets = <&rst GPIO1_RESET>;status = "disabled";portb: gpio-controller@0 {compatible = "snps,dw-apb-gpio-port";gpio-controller;#gpio-cells = <2>;snps,nr-gpios = <24>;reg = <0>;interrupt-controller;#interrupt-cells = <2>;interrupts = <0 111 4>;};};i2c0: i2c@ffc02800 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0xffc02800 0x100>;interrupts = <0 103 4>;resets = <&rst I2C0_RESET>;reset-names = "i2c";clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};i2c1: i2c@ffc02900 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0xffc02900 0x100>;interrupts = <0 104 4>;resets = <&rst I2C1_RESET>;reset-names = "i2c";clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};i2c2: i2c@ffc02a00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0xffc02a00 0x100>;interrupts = <0 105 4>;resets = <&rst I2C2_RESET>;reset-names = "i2c";clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};i2c3: i2c@ffc02b00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0xffc02b00 0x100>;interrupts = <0 106 4>;resets = <&rst I2C3_RESET>;reset-names = "i2c";clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};i2c4: i2c@ffc02c00 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,designware-i2c";reg = <0xffc02c00 0x100>;interrupts = <0 107 4>;resets = <&rst I2C4_RESET>;reset-names = "i2c";clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};mmc: dwmmc0@ff808000 {#address-cells = <1>;#size-cells = <0>;compatible = "altr,socfpga-dw-mshc";reg = <0xff808000 0x1000>;interrupts = <0 96 4>;fifo-depth = <0x400>;resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;reset-names = "reset", "sdmmc-ocp";clocks = <&clkmgr SOCFPGA_SOC64_L4_MP_CLK>,<&clkmgr SOCFPGA_SOC64_SDMMC_CLK>;clock-names = "biu", "ciu";iommus = <&smmu 5>;status = "disabled";};ocram: sram@ffe00000 {compatible = "mmio-sram";reg = <0xffe00000 0x40000>;};pdma: pdma@ffda0000 {compatible = "arm,pl330", "arm,primecell";reg = <0xffda0000 0x1000>;interrupts = <0 81 4>,<0 82 4>,<0 83 4>,<0 84 4>,<0 85 4>,<0 86 4>,<0 87 4>,<0 88 4>,<0 89 4>;#dma-cells = <1>;#dma-channels = <8>;#dma-requests = <32>;clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>;clock-names = "apb_pclk";};qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;status = "disabled";};rst: rstmgr@ffd11000 {#reset-cells = <1>;compatible = "altr,rst-mgr";reg = <0xffd11000 0x100>;altr,modrst-offset = <0x20>;};smmu: iommu@fa000000 {compatible = "arm,mmu-500", "arm,smmu-v2";reg = <0xfa000000 0x40000>;#global-interrupts = <2>;#iommu-cells = <1>;clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>;clock-names = "iommu";interrupt-parent = <&intc>;interrupts = <0 128 4>, /* Global Secure Fault */<0 129 4>, /* Global Non-secure Fault *//* Non-secure Context Interrupts (32) */<0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,<0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,<0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,<0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,<0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,<0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;stream-match-mask = <0x7ff0>;status = "disabled";};spi0: spi@ffda4000 {compatible = "snps,dw-apb-ssi";#address-cells = <1>;#size-cells = <0>;reg = <0xffda4000 0x1000>;interrupts = <0 99 4>;resets = <&rst SPIM0_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>;status = "disabled";};spi1: spi@ffda5000 {compatible = "snps,dw-apb-ssi";#address-cells = <1>;#size-cells = <0>;reg = <0xffda5000 0x1000>;interrupts = <0 100 4>;resets = <&rst SPIM1_RESET>;reg-io-width = <4>;num-cs = <4>;clocks = <&clkmgr SOCFPGA_SOC64_L4_MAIN_CLK>;status = "disabled";};sysmgr: sysmgr@ffd12000 {compatible = "altr,sys-mgr", "syscon";reg = <0xffd12000 0x500>;};/* Local timer */timer {compatible = "arm,armv8-timer";interrupts = <1 13 0xf08>,<1 14 0xf08>,<1 11 0xf08>,<1 10 0xf08>;};timer0: timer0@ffc03000 {compatible = "snps,dw-apb-timer";interrupts = <0 113 4>;reg = <0xffc03000 0x100>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;clock-names = "timer";};timer1: timer1@ffc03100 {compatible = "snps,dw-apb-timer";interrupts = <0 114 4>;reg = <0xffc03100 0x100>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;clock-names = "timer";};timer2: timer2@ffd00000 {compatible = "snps,dw-apb-timer";interrupts = <0 115 4>;reg = <0xffd00000 0x100>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;clock-names = "timer";};timer3: timer3@ffd00100 {compatible = "snps,dw-apb-timer";interrupts = <0 116 4>;reg = <0xffd00100 0x100>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;clock-names = "timer";};uart0: serial0@ffc02000 {compatible = "snps,dw-apb-uart";reg = <0xffc02000 0x100>;interrupts = <0 108 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART0_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};uart1: serial1@ffc02100 {compatible = "snps,dw-apb-uart";reg = <0xffc02100 0x100>;interrupts = <0 109 4>;reg-shift = <2>;reg-io-width = <4>;resets = <&rst UART1_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SP_CLK>;status = "disabled";};usbphy0: usbphy@0 {#phy-cells = <0>;compatible = "usb-nop-xceiv";status = "okay";};usb0: usb@ffb00000 {compatible = "snps,dwc2";reg = <0xffb00000 0x40000>;interrupts = <0 93 4>;phys = <&usbphy0>;phy-names = "usb2-phy";resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;reset-names = "dwc2", "dwc2-ecc";clocks = <&clkmgr SOCFPGA_SOC64_USB_CLK>;iommus = <&smmu 6>;status = "disabled";};usb1: usb@ffb40000 {compatible = "snps,dwc2";reg = <0xffb40000 0x40000>;interrupts = <0 94 4>;phys = <&usbphy0>;phy-names = "usb2-phy";resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;reset-names = "dwc2", "dwc2-ecc";clocks = <&clkmgr SOCFPGA_SOC64_USB_CLK>;iommus = <&smmu 7>;status = "disabled";};watchdog0: watchdog@ffd00200 {compatible = "snps,dw-wdt";reg = <0xffd00200 0x100>;interrupts = <0 117 4>;resets = <&rst WATCHDOG0_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>;status = "disabled";};watchdog1: watchdog@ffd00300 {compatible = "snps,dw-wdt";reg = <0xffd00300 0x100>;interrupts = <0 118 4>;resets = <&rst WATCHDOG1_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>;status = "disabled";};watchdog2: watchdog@ffd00400 {compatible = "snps,dw-wdt";reg = <0xffd00400 0x100>;interrupts = <0 125 4>;resets = <&rst WATCHDOG2_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>;status = "disabled";};watchdog3: watchdog@ffd00500 {compatible = "snps,dw-wdt";reg = <0xffd00500 0x100>;interrupts = <0 126 4>;resets = <&rst WATCHDOG3_RESET>;clocks = <&clkmgr SOCFPGA_SOC64_L4_SYS_FREE_CLK>;status = "disabled";};sdr: sdr@f8011100 {compatible = "altr,sdr-ctl", "syscon";reg = <0xf8011100 0xc0>;};};+}; diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi new file mode 100644 index 0000000000..723fe1e0c8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- U-Boot additions
- Copyright (C) 2019 Intel Corporation <www.intel.com>
- */
+/{
aliases {spi0 = &qspi;};memory {u-boot,dm-pre-reloc;};soc {u-boot,dm-pre-reloc;};+};
+&clkmgr {
u-boot,dm-pre-reloc;+};
+&flash0 {
compatible = "jedec,spi-nor";spi-max-frequency = <100000000>;spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;u-boot,dm-pre-reloc;+};
+&mmc {
drvsel = <3>;smplsel = <0>;u-boot,dm-pre-reloc;+};
+&porta {
bank-name = "porta";+};
+&portb {
bank-name = "portb";+};
+&qspi {
u-boot,dm-pre-reloc;+};
+&rst {
u-boot,dm-pre-reloc;+};
+&sdr {
compatible = "intel,sdr-ctl-agilex";reg = <0xf8000400 0x80>,<0xf8010000 0x190>,<0xf8011000 0x500>;resets = <&rst DDRSCH_RESET>;u-boot,dm-pre-reloc;+};
+&sysmgr {
u-boot,dm-pre-reloc;+};
+&uart0 {
u-boot,dm-pre-reloc;+};
+&watchdog0 {
u-boot,dm-pre-reloc;+}; diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts b/arch/arm/dts/socfpga_agilex_socdk.dts new file mode 100644 index 0000000000..7e653932e8 --- /dev/null +++ b/arch/arm/dts/socfpga_agilex_socdk.dts @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2019 Intel Corporation
- */
+#include "socfpga_agilex.dtsi"
+/ {
model = "SoCFPGA Agilex SoCDK";aliases {ethernet0 = &gmac0;i2c0 = &i2c1;serial0 = &uart0;};chosen {stdout-path = "serial0:115200n8";};leds {compatible = "gpio-leds";hps0 {label = "hps_led0";gpios = <&portb 20 GPIO_ACTIVE_HIGH>;};hps1 {label = "hps_led1";gpios = <&portb 19 GPIO_ACTIVE_HIGH>;};hps2 {label = "hps_led2";gpios = <&portb 21 GPIO_ACTIVE_HIGH>;};};memory {device_type = "memory";/* 8GB */reg = <0 0x00000000 0 0x80000000>,<2 0x80000000 1 0x80000000>;};+};
+&gpio1 {
status = "okay";+};
+&gmac0 {
status = "okay";phy-mode = "rgmii";phy-handle = <&phy0>;max-frame-size = <3800>;mdio0 {#address-cells = <1>;#size-cells = <0>;compatible = "snps,dwmac-mdio";phy0: ethernet-phy@0 {reg = <4>;txd0-skew-ps = <0>; /* -420ps */txd1-skew-ps = <0>; /* -420ps */txd2-skew-ps = <0>; /* -420ps */txd3-skew-ps = <0>; /* -420ps */rxd0-skew-ps = <420>; /* 0ps */rxd1-skew-ps = <420>; /* 0ps */rxd2-skew-ps = <420>; /* 0ps */rxd3-skew-ps = <420>; /* 0ps */txen-skew-ps = <0>; /* -420ps */txc-skew-ps = <1860>; /* 960ps */rxdv-skew-ps = <420>; /* 0ps */rxc-skew-ps = <1680>; /* 780ps */};};+};
+&i2c1 {
status = "okay";+};
+&mmc {
status = "okay";cap-sd-highspeed;cap-mmc-highspeed;broken-cd;bus-width = <4>;+};
+&qspi {
status = "okay";flash0: flash@0 {#address-cells = <1>;#size-cells = <1>;compatible = "n25q00a";reg = <0>;spi-max-frequency = <50000000>;m25p,fast-read;cdns,page-size = <256>;cdns,block-size = <16>;cdns,read-delay = <1>;cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;partitions {compatible = "fixed-partitions";#address-cells = <1>;#size-cells = <1>;qspi_boot: partition@0 {label = "Boot and fpga data";reg = <0x0 0x4000000>;};qspi_rootfs: partition@4000000 {label = "Root Filesystem - JFFS2";reg = <0x4000000 0x4000000>;};};};+};
+&uart0 {
status = "okay";+};
+&usb0 {
status = "okay";+};
2.19.0
Add build support for Agilex SoC.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com
--- v3: - Disable CONFIG_USE_TINY_PRINTF
v2: - Remove IC_CLK define, use clock DM method to get i2c clock - Change CONFIG_ENV_SIZE to 4KB since CONFIG_SPI_FLASH_USE_4K_SECTORS is enabled. --- arch/arm/Kconfig | 4 +- arch/arm/mach-socfpga/Kconfig | 15 ++ arch/arm/mach-socfpga/Makefile | 9 ++ configs/socfpga_agilex_defconfig | 59 +++++++ include/configs/socfpga_agilex_socdk.h | 207 +++++++++++++++++++++++++ 5 files changed, 292 insertions(+), 2 deletions(-) create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 include/configs/socfpga_agilex_socdk.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3b0e315061..e6c9d19968 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -888,7 +888,7 @@ config ARCH_SOCFPGA bool "Altera SOCFPGA family" select ARCH_EARLY_INIT_R select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10 - select ARM64 if TARGET_SOCFPGA_STRATIX10 + select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 select DM select DM_SERIAL @@ -900,7 +900,7 @@ config ARCH_SOCFPGA select SPL_LIBGENERIC_SUPPORT select SPL_NAND_SUPPORT if SPL_NAND_DENALI select SPL_OF_CONTROL - select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 + select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX select SPL_SERIAL_SUPPORT select SPL_SYSRESET select SPL_WATCHDOG_SUPPORT diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1d914648e3..b64477a081 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -26,6 +26,14 @@ config SYS_TEXT_BASE default 0x01000040 if TARGET_SOCFPGA_ARRIA10 default 0x01000040 if TARGET_SOCFPGA_GEN5
+config TARGET_SOCFPGA_AGILEX + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select ARMV8_SPIN_TABLE + select CLK + select SPL_CLK if SPL + config TARGET_SOCFPGA_ARRIA5 bool select TARGET_SOCFPGA_GEN5 @@ -72,6 +80,10 @@ choice prompt "Altera SOCFPGA board select" optional
+config TARGET_SOCFPGA_AGILEX_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex)" + select TARGET_SOCFPGA_AGILEX + config TARGET_SOCFPGA_ARIES_MCVEVK bool "Aries MCVEVK (Cyclone V)" select TARGET_SOCFPGA_CYCLONE5 @@ -132,6 +144,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice
config SYS_BOARD + default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -148,6 +161,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK @@ -165,6 +179,7 @@ config SYS_SOC default "socfpga"
config SYS_CONFIG_NAME + default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 9d334e9e1b..30c87b1efd 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -41,6 +41,14 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += clock_manager_agilex.o +obj-y += mailbox_s10.o +obj-y += misc_s10.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-y += system_manager_s10.o +obj-y += timer_s10.o +obj-y += wrap_pinmux_config_s10.o +obj-y += wrap_pll_config_s10.o endif
ifdef CONFIG_SPL_BUILD @@ -60,6 +68,7 @@ obj-y += spl_s10.o endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX obj-y += ccu_agilex.o +obj-y += firewall.o obj-y += spl_agilex.o endif endif diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig new file mode 100644 index 0000000000..daf71ff0eb --- /dev/null +++ b/configs/socfpga_agilex_defconfig @@ -0,0 +1,59 @@ +CONFIG_ARM=y +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y +CONFIG_IDENT_STRING="socfpga_agilex" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_BOOTDELAY=5 +CONFIG_SPL_SPI_LOAD=y +CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_EMBED=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_DM_GPIO=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +# CONFIG_USE_TINY_PRINTF is not set diff --git a/include/configs/socfpga_agilex_socdk.h b/include/configs/socfpga_agilex_socdk.h new file mode 100644 index 0000000000..8ed96ed252 --- /dev/null +++ b/include/configs/socfpga_agilex_socdk.h @@ -0,0 +1,207 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (C) 2019 Intel Corporation <www.intel.com> + * + */ + +#ifndef __CONFIG_SOCFGPA_AGILEX_H__ +#define __CONFIG_SOCFGPA_AGILEX_H__ + +#include <asm/arch/base_addr_s10.h> +#include <asm/arch/handoff_s10.h> + +/* + * U-Boot general configurations + */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_LOADADDR 0x2000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_REMAKE_ELF +/* sysmgr.boot_scratch_cold4 & 5 (64bit) will be used for PSCI_CPU_ON call */ +#define CPU_RELEASE_ADDR 0xFFD12210 +#define CONFIG_SYS_CACHELINE_SIZE 64 +#define CONFIG_SYS_MEM_RESERVE_SECURE 0 /* using OCRAM, not DDR */ + +/* + * U-Boot console configurations + */ +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* Extend size of kernel image for uncompression */ +#define CONFIG_SYS_BOOTM_LEN (32 * 1024 * 1024) + +/* + * U-Boot run time memory configurations + */ +#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR \ + + CONFIG_SYS_INIT_RAM_SIZE \ + - S10_HANDOFF_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_SP_ADDR) +#define CONFIG_SYS_MALLOC_LEN (5 * 1024 * 1024) + +/* + * U-Boot environment configurations + */ +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */ +#define CONFIG_ENV_OFFSET 512 /* just after the MBR */ + +/* + * QSPI support + */ + #ifdef CONFIG_CADENCE_QSPI +/* Enable it if you want to use dual-stacked mode */ +/*#define CONFIG_QSPI_RBF_ADDR 0x720000*/ + +/* Flash device info */ + +/*#define CONFIG_ENV_IS_IN_SPI_FLASH*/ +#ifdef CONFIG_ENV_IS_IN_SPI_FLASH +#undef CONFIG_ENV_OFFSET +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_OFFSET 0x710000 +#define CONFIG_ENV_SIZE (4 * 1024) +#define CONFIG_ENV_SECT_SIZE (4 * 1024) +#endif /* CONFIG_ENV_IS_IN_SPI_FLASH */ + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITIONS +#define MTDIDS_DEFAULT "nor0=ff705000.spi.0" +#endif /* CONFIG_SPL_BUILD */ + +#ifndef __ASSEMBLY__ +unsigned int cm_get_qspi_controller_clk_hz(void); +#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() +#endif + +#endif /* CONFIG_CADENCE_QSPI */ + +/* + * Boot arguments passed to the boot command. The value of + * CONFIG_BOOTARGS goes into the environment value "bootargs". + * Do note the value will override also the chosen node in FDT blob. + */ +#define CONFIG_BOOTARGS "earlycon" +#define CONFIG_BOOTCOMMAND "run fatscript; run mmcload;run linux_qspi_enable;" \ + "run mmcboot" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ + "bootfile=Image\0" \ + "fdt_addr=8000000\0" \ + "fdtimage=socfpga_agilex_socdk.dtb\0" \ + "mmcroot=/dev/mmcblk0p2\0" \ + "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ + " root=${mmcroot} rw rootwait;" \ + "booti ${loadaddr} - ${fdt_addr}\0" \ + "mmcload=mmc rescan;" \ + "load mmc 0:1 ${loadaddr} ${bootfile};" \ + "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ + "linux_qspi_enable=if sf probe; then " \ + "echo Enabling QSPI at Linux DTB...;" \ + "fdt addr ${fdt_addr}; fdt resize;" \ + "fdt set /soc/spi@ff8d2000 status okay;" \ + "fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency " \ + " ${qspi_clock}; fi; \0" \ + "scriptaddr=0x02100000\0" \ + "scriptfile=u-boot.scr\0" \ + "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \ + "then source ${scriptaddr}; fi\0" + +/* + * Generic Interrupt Controller Definitions + */ +#define CONFIG_GICV2 + +/* + * External memory configurations + */ +#define PHYS_SDRAM_1 0x0 +#define PHYS_SDRAM_1_SIZE (1 * 1024 * 1024 * 1024) +#define CONFIG_SYS_SDRAM_BASE 0 +#define CONFIG_SYS_MEMTEST_START 0 +#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE - 0x200000 + +/* + * Serial / UART configurations + */ +#define CONFIG_SYS_NS16550_CLK 100000000 +#define CONFIG_SYS_NS16550_MEM32 + +/* + * Timer & watchdog configurations + */ +#define COUNTER_FREQUENCY 400000000 + +/* + * SDMMC configurations + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 +#endif +/* + * Flash configurations + */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +/* Ethernet on SoC (EMAC) */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_DW_ALTDESCRIPTOR +#endif /* CONFIG_CMD_NET */ + +/* + * L4 Watchdog + */ +#ifdef CONFIG_SPL_BUILD +#define CONFIG_HW_WATCHDOG +#define CONFIG_DESIGNWARE_WATCHDOG +#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS +#ifndef __ASSEMBLY__ +#define CONFIG_DW_WDT_CLOCK_KHZ 100000 +#endif +#define CONFIG_WATCHDOG_TIMEOUT_MSECS 3000 +#endif + +/* + * SPL memory layout + * + * On chip RAM + * 0xFFE0_0000 ...... Start of OCRAM + * SPL code, rwdata + * empty space + * 0xFFEx_xxxx ...... Top of stack (grows down) + * 0xFFEy_yyyy ...... Global Data + * 0xFFEz_zzzz ...... Malloc prior relocation (size CONFIG_SYS_MALLOC_F_LEN) + * 0xFFE3_F000 ...... Hardware handdoff blob (size 4KB) + * 0xFFE3_FFFF ...... End of OCRAM + * + * SDRAM + * 0x0000_0000 ...... Start of SDRAM_1 + * unused / empty space for image loading + * Size 64MB ...... MALLOC (size CONFIG_SYS_SPL_MALLOC_SIZE) + * Size 1MB ...... BSS (size CONFIG_SPL_BSS_MAX_SIZE) + * 0x8000_0000 ...... End of SDRAM_1 (assume 2GB) + * + */ +#define CONFIG_SPL_TARGET "spl/u-boot-spl.hex" +#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SPL_BSS_START_ADDR (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE \ + - CONFIG_SPL_BSS_MAX_SIZE) +#define CONFIG_SYS_SPL_MALLOC_SIZE (CONFIG_SYS_MALLOC_LEN) +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR \ + - CONFIG_SYS_SPL_MALLOC_SIZE) + +/* SPL SDMMC boot support */ +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" + +#endif /* __CONFIG_H */
On Thu, Sep 12, 2019 at 6:11 PM Ley Foon Tan ley.foon.tan@intel.com wrote:
This is 4th version of patchset to add Intel Agilex SoC[1] support. Most of changes are related to _SOC64 prefix change and use base address from DT for managers access. Detail changelog can find in commit message.
This patchset needs to apply after patchset in [2] for manager driver struct to defines conversion.
Patch status: No change: Patch 1, 4, 6, 7, 10, 11, 14, 17 Have changes: Patch 2, 3, 5, 8, 9, 12, 13, 15, 16
Detail change log is in patch commit message.
Intel Agilex SoC is with a 64-bit quad core ARM Cortex-A53 MPCore hard processor system (HPS). New IPs in Agilex are CCU, clock manager and SDRAM, other IPs have minor changes compared to Stratix 10.
Intel Agilex HPS TRM: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/...
v3->v4:
- Rename _S10 to _SOC64 perfix for S10 and Agilex common defines.
- Use base address from DT for managers access.
- Add u-boot,dm-pre-reloc to sysmgr node in dts
History:
Ley Foon Tan (17): arm: socfpga: agilex: Add base address for Intel Agilex SoC arm: socfpga: Move firewall code to firewall file arm: socfpga: Move Stratix10 and Agilex reset manager common code arm: socfpga: agilex: Add reset manager support arm: socfpga: Move Stratix10 and Agilex system manager common code arm: socfpga: agilex: Add system manager support arm: socfpga: Move Stratix10 and Agilex clock manager common code clk: agilex: Add clock driver for Agilex arm: socfpga: agilex: Add clock wrapper functions arm: socfpga: agilex: Add CCU support for Agilex arm: agilex: Add clock handoff offset for Agilex ddr: altera: Restructure Stratix 10 SDRAM driver ddr: altera: agilex: Add SDRAM driver for Agilex board: intel: agilex: Add socdk board support for Intel Agilex SoC arm: socfpga: agilex: Add SPL for Agilex SoC arm: dts: agilex: Add base dtsi and devkit dts arm: socfpga: agilex: Enable Agilex SoC build
arch/arm/Kconfig | 4 +- arch/arm/dts/Makefile | 1 + arch/arm/dts/socfpga_agilex.dtsi | 495 +++++++++++++++ arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi | 75 +++ arch/arm/dts/socfpga_agilex_socdk.dts | 136 ++++ arch/arm/mach-socfpga/Kconfig | 15 + arch/arm/mach-socfpga/Makefile | 18 + arch/arm/mach-socfpga/ccu_agilex.c | 99 +++ arch/arm/mach-socfpga/clock_manager_agilex.c | 84 +++ arch/arm/mach-socfpga/clock_manager_s10.c | 2 +- .../mach-socfpga/{spl_s10.c => firewall.c} | 122 +--- .../mach-socfpga/include/mach/base_addr_s10.h | 4 + .../mach-socfpga/include/mach/ccu_agilex.h | 67 ++ .../mach-socfpga/include/mach/clock_manager.h | 2 + .../include/mach/clock_manager_agilex.h | 14 + .../include/mach/clock_manager_s10.h | 16 +- .../include/mach/clock_manager_soc64.h | 23 + .../mach/{firewall_s10.h => firewall.h} | 10 +- .../mach-socfpga/include/mach/handoff_s10.h | 9 +- .../mach-socfpga/include/mach/reset_manager.h | 2 + .../include/mach/reset_manager_agilex.h | 11 + .../include/mach/reset_manager_s10.h | 87 +-- .../include/mach/reset_manager_soc64.h | 38 ++ .../include/mach/system_manager.h | 2 + .../include/mach/system_manager_agilex.h | 11 + .../include/mach/system_manager_s10.h | 116 +--- .../include/mach/system_manager_soc64.h | 123 ++++ arch/arm/mach-socfpga/mailbox_s10.c | 2 +- arch/arm/mach-socfpga/misc.c | 4 + arch/arm/mach-socfpga/misc_s10.c | 4 +- arch/arm/mach-socfpga/reset_manager_s10.c | 34 +- arch/arm/mach-socfpga/spl_agilex.c | 95 +++ arch/arm/mach-socfpga/spl_s10.c | 95 +-- arch/arm/mach-socfpga/system_manager_s10.c | 26 +- arch/arm/mach-socfpga/wrap_pll_config_s10.c | 13 +- board/intel/agilex-socdk/MAINTAINERS | 7 + board/intel/agilex-socdk/Makefile | 7 + board/intel/agilex-socdk/socfpga.c | 7 + configs/socfpga_agilex_defconfig | 59 ++ drivers/clk/altera/Makefile | 1 + drivers/clk/altera/clk-agilex.c | 579 ++++++++++++++++++ drivers/clk/altera/clk-agilex.h | 237 +++++++ drivers/ddr/altera/Kconfig | 6 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex.c | 168 +++++ drivers/ddr/altera/sdram_s10.c | 298 +-------- drivers/ddr/altera/sdram_s10.h | 148 +---- drivers/ddr/altera/sdram_soc64.c | 304 +++++++++ .../ddr/altera/{sdram_s10.h => sdram_soc64.h} | 71 ++- include/configs/socfpga_agilex_socdk.h | 207 +++++++ .../dt-bindings/clock/socfpga-soc64-clock.h | 84 +++ 51 files changed, 3105 insertions(+), 940 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex_socdk.dts create mode 100644 arch/arm/mach-socfpga/ccu_agilex.c create mode 100644 arch/arm/mach-socfpga/clock_manager_agilex.c copy arch/arm/mach-socfpga/{spl_s10.c => firewall.c} (54%) create mode 100644 arch/arm/mach-socfpga/include/mach/ccu_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_soc64.h rename arch/arm/mach-socfpga/include/mach/{firewall_s10.h => firewall.h} (94%) create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_agilex.h create mode 100644 arch/arm/mach-socfpga/include/mach/system_manager_soc64.h create mode 100644 arch/arm/mach-socfpga/spl_agilex.c create mode 100644 board/intel/agilex-socdk/MAINTAINERS create mode 100644 board/intel/agilex-socdk/Makefile create mode 100644 board/intel/agilex-socdk/socfpga.c create mode 100644 configs/socfpga_agilex_defconfig create mode 100644 drivers/clk/altera/clk-agilex.c create mode 100644 drivers/clk/altera/clk-agilex.h create mode 100644 drivers/ddr/altera/sdram_agilex.c create mode 100644 drivers/ddr/altera/sdram_soc64.c copy drivers/ddr/altera/{sdram_s10.h => sdram_soc64.h} (79%) create mode 100644 include/configs/socfpga_agilex_socdk.h create mode 100644 include/dt-bindings/clock/socfpga-soc64-clock.h
-- 2.19.0
Hi Marek and Simon
Any further comment for this series?
Thanks.
Regards Ley Foon
participants (3)
-
Ley Foon Tan -
Ley Foon Tan -
Simon Goldschmidt