[U-Boot] [PATCH 0/12]: Add more framework to OMAP3 SPL, port more boards
Hey all,
This is related to, but a bit different from the RFT thread I made with beagleboard SPL patches. I've incorporated the feedback about splitting the changes up a lot more and after talking with Scott Wood on IRC after the ML thread, I've created an omap3 specific file with the NAND related stuff these boards need (since it would have gotten very big for what's really needed here at this stage). The series is checkpatch.pl clean.
What we have in patches 1-6 is bugfixing and cleanup of the SDRC code. It's worth noting that without these changes we do some very 'funny' (read: wrong) things on some platforms like omap3_evm where we find 384MB memory when there's really only 256MB (and maybe 256 on the 128MB boards, not sure).
Patch 7 adds another hook for SDRC boards to be able to say what timings they have because on say beagle or omap3_evm, we have a few choices. We also convert devkit8000 here.
Patch 8 adds a new CONFIG (CONFIG_SPL_OMAP3_POP_PROBE) and file so that OMAP3 boards which have a PoP chip for NAND/DDR can find out what they are and decide on timings based on that.
Patches 9 and 10 convert Beagleboard and OMAP3 EVM to SPL.
Patches 11 and 12 convert the am3517 evm and am3517 crane boards (which don't use SDRC but EMIF4) to SPL as well (given Ilya Yanok fixed a bug in <asm/arch-omap3/cpu.h for emif4 this is just a mechanical change).
We update the comment in make_cs1_contiguous() to be a little bit more clear (it's been copy/pasted from other silicons) and then explain in dram_init() why we need to always try this.
Note that in the previous behavior we were always calling this on boards that never had cs1 populated anyhow so making sure we do this always is fine and will correct things like omap3evm detecting an invalid amount of memory (384MB).
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap3/sdrc.c | 23 +++++++++++------------ 1 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 0dd1955..66ce33f 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -58,10 +58,9 @@ u32 is_mem_sdr(void)
/* * make_cs1_contiguous - - * - For es2 and above remap cs1 behind cs0 to allow command line - * mem=xyz use all memory with out discontinuous support compiled in. - * Could do it at the ATAG, but there really is two banks... - * - Called as part of 2nd phase DDR init. + * - When we have CS1 populated we want to have it mapped after cs0 to allow + * command line mem=xyz use all memory with out discontinuous support + * compiled in. We could do it in the ATAG, but there really is two banks... */ void make_cs1_contiguous(void) { @@ -207,16 +206,16 @@ int dram_init(void)
size0 = get_sdr_cs_size(CS0); /* - * If a second bank of DDR is attached to CS1 this is - * where it can be started. Early init code will init - * memory on CS0. + * We always need to have cs_cfg point at where the second + * bank would be, if present. Failure to do so can lead to + * strange situations where memory isn't detected and + * configured correctly. CS0 will already have been setup + * at this point. */ - if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { - do_sdrc_init(CS1, NOT_EARLY); - make_cs1_contiguous(); + make_cs1_contiguous(); + do_sdrc_init(CS1, NOT_EARLY); + size1 = get_sdr_cs_size(CS1);
- size1 = get_sdr_cs_size(CS1); - } gd->ram_size = size0 + size1;
return 0;
Since we go through the sequence to setup the SDRC timings more than once, break this logic out into its own function and have that function call mem_ok() to make sure the memory is usable.
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap3/sdrc.c | 116 ++++++++++++++++++++------------------ 1 files changed, 61 insertions(+), 55 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 66ce33f..2756024 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -108,14 +108,45 @@ u32 get_sdr_cs_offset(u32 cs) }
/* + * write_sdrc_timings - + * - Takes CS and associated timings and initalize SDRAM + * - Test CS to make sure it's OK for use + */ +static void write_sdrc_timings(u32 cs, struct sdrc_actim *sdrc_actim_base, + u32 mcfg, u32 ctrla, u32 ctrlb, u32 rfr_ctrl, u32 mr) +{ + /* Setup timings we got from the board. */ + writel(mcfg, &sdrc_base->cs[cs].mcfg); + writel(ctrla, &sdrc_actim_base->ctrla); + writel(ctrlb, &sdrc_actim_base->ctrlb); + writel(rfr_ctrl, &sdrc_base->cs[cs].rfr_ctrl); + writel(CMD_NOP, &sdrc_base->cs[cs].manual); + writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + writel(mr, &sdrc_base->cs[cs].mr); + + /* + * Test ram in this bank + * Disable if bad or not present + */ + if (!mem_ok(cs)) + writel(0, &sdrc_base->cs[cs].mcfg); +} + +/* * do_sdrc_init - - * - Initialize the SDRAM for use. - * - code called once in C-Stack only context for CS0 and a possible 2nd - * time depending on memory configuration from stack+global context + * - Code called once in C-Stack only context for CS0 and with early being + * true and a possible 2nd time depending on memory configuration from + * stack+global context. */ void do_sdrc_init(u32 cs, u32 early) { struct sdrc_actim *sdrc_actim_base0, *sdrc_actim_base1; + u32 mcfg, ctrla, ctrlb, rfr_ctrl, mr; + + sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; + sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
if (early) { /* reset sdrc controller */ @@ -127,73 +158,48 @@ void do_sdrc_init(u32 cs, u32 early) /* setup sdrc to ball mux */ writel(SDRC_SHARING, &sdrc_base->sharing);
- /* Disable Power Down of CKE cuz of 1 CKE on combo part */ + /* Disable Power Down of CKE because of 1 CKE on combo part */ writel(WAKEUPPROC | SRFRONRESET | PAGEPOLICY_HIGH, &sdrc_base->power);
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); - } - /* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need * to prevent this to be build in non-SPL build */ #ifdef CONFIG_SPL_BUILD - /* If we use a SPL there is no x-loader nor config header so we have - * to do the job ourselfs - */ - if (cs == CS0) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - - /* General SDRC config */ - writel(V_MCFG, &sdrc_base->cs[cs].mcfg); - writel(V_RFR_CTRL, &sdrc_base->cs[cs].rfr_ctrl); - - /* AC timings */ - writel(V_ACTIMA_165, &sdrc_actim_base0->ctrla); - writel(V_ACTIMB_165, &sdrc_actim_base0->ctrlb); - - /* Initialize */ - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); + /* + * If we use a SPL there is no x-loader nor config header so + * we have to do the job ourselfs + */ + + mcfg = V_MCFG; + ctrla = V_ACTIMA_165; + ctrlb = V_ACTIMB_165; + rfr_ctrl = V_RFR_CTRL; + mr = V_MR; + + write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); +#endif
- writel(V_MR, &sdrc_base->cs[cs].mr); } -#endif
/* - * SDRC timings are set up by x-load or config header - * We don't need to redo them here. - * Older x-loads configure only CS0 - * configure CS1 to handle this ommission + * If we aren't using SPL we have been loaded by some + * other means which may not have correctly initialized + * both CS0 and CS1 (such as some older versions of x-loader) + * so we may be asked now to setup CS1. */ if (cs == CS1) { - sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; - sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE; - writel(readl(&sdrc_base->cs[CS0].mcfg), - &sdrc_base->cs[CS1].mcfg); - writel(readl(&sdrc_base->cs[CS0].rfr_ctrl), - &sdrc_base->cs[CS1].rfr_ctrl); - writel(readl(&sdrc_actim_base0->ctrla), - &sdrc_actim_base1->ctrla); - writel(readl(&sdrc_actim_base0->ctrlb), - &sdrc_actim_base1->ctrlb); - - writel(CMD_NOP, &sdrc_base->cs[cs].manual); - writel(CMD_PRECHARGE, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(CMD_AUTOREFRESH, &sdrc_base->cs[cs].manual); - writel(readl(&sdrc_base->cs[CS0].mr), - &sdrc_base->cs[CS1].mr); - } + mcfg = readl(&sdrc_base->cs[CS0].mcfg), + rfr_ctrl = readl(&sdrc_base->cs[CS0].rfr_ctrl); + ctrla = readl(&sdrc_actim_base0->ctrla), + ctrlb = readl(&sdrc_actim_base0->ctrlb); + mr = readl(&sdrc_base->cs[CS0].mr); + write_sdrc_timings(cs, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr);
- /* - * Test ram in this bank - * Disable if bad or not present - */ - if (!mem_ok(cs)) - writel(0, &sdrc_base->cs[cs].mcfg); + } }
/*
It's possible to need to call this function on the same banks multiple times so we want to be sure that 'pos A' is cleared out again at the end.
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap3/mem.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/mem.c b/arch/arm/cpu/armv7/omap3/mem.c index a01c303..cd5fe5c 100644 --- a/arch/arm/cpu/armv7/omap3/mem.c +++ b/arch/arm/cpu/armv7/omap3/mem.c @@ -86,6 +86,7 @@ u32 mem_ok(u32 cs) writel(0x0, addr + 4); /* remove pattern off the bus */ val1 = readl(addr + 0x400); /* get pos A value */ val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */
if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ return 0;
This function doesn't exist for omap3
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 - 1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 995e7cb..9e64410 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -49,7 +49,6 @@ void set_muxconf_regs(void); u32 get_cpu_family(void); u32 get_cpu_rev(void); u32 get_sku_id(void); -u32 get_mem_type(void); u32 get_sysboot_value(void); u32 is_gpmc_muxed(void); u32 get_gpmc0_type(void);
This adds the optimal SDRC autorefresh control register values for 100Mhz, 133MHz, 165MHz and 200MHz clocks. We switch to using this to provide the default 165MHz value.
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-omap3/mem.h | 12 +++++++----- 1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 8e28f77..61baccb 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -43,6 +43,12 @@ enum { #define SDRC_SHARING 0x00000100 #define SDRC_MR_0_SDR 0x00000031
+/* optimized timings good for current shipping parts */ +#define SDP_3430_SDRC_RFR_CTRL_100MHz 0x0002da01 +#define SDP_3430_SDRC_RFR_CTRL_133MHz 0x0003de01 /* 7.8us/7.5ns - 50=0x3de */ +#define SDP_3430_SDRC_RFR_CTRL_165MHz 0x0004e201 /* 7.8us/6ns - 50=0x4e2 */ +#define SDP_3430_SDRC_RFR_CTRL_200MHz 0x0005e601 /* 7.8us/5ns - 50=0x5e6 */ + #define DLL_OFFSET 0 #define DLL_WRITEDDRCLKX2DIS 1 #define DLL_ENADLL 1 @@ -144,10 +150,6 @@ enum { (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
-#define MICRON_ARCV 2030 -#define MICRON_ARE 0x1 -#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE)) - #define MICRON_BL 0x2 #define MICRON_SIL 0x0 #define MICRON_CASL 0x3 @@ -203,7 +205,7 @@ enum { #define V_ACTIMA_165 MICRON_V_ACTIMA_165 #define V_ACTIMB_165 MICRON_V_ACTIMB_165 #define V_MCFG MICRON_V_MCFG -#define V_RFR_CTRL MICRON_V_RFR_CTRL +#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz #define V_MR MICRON_V_MR #endif
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-omap3/mem.h | 54 +++++++++++++++++---------------- 1 files changed, 28 insertions(+), 26 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 61baccb..a55553c 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -134,28 +134,30 @@ enum { (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \ (MICRON_TWTR_165 << 16))
-#define MICRON_RAMTYPE 0x1 -#define MICRON_DDRTYPE 0x0 -#define MICRON_DEEPPD 0x1 -#define MICRON_B32NOT16 0x1 -#define MICRON_BANKALLOCATION 0x2 -#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) -#define MICRON_ADDRMUXLEGACY 0x1 -#define MICRON_CASWIDTH 0x5 -#define MICRON_RASWIDTH 0x2 -#define MICRON_LOCKSTATUS 0x0 -#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \ - (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \ - (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \ - (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \ - (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE)) - -#define MICRON_BL 0x2 -#define MICRON_SIL 0x0 -#define MICRON_CASL 0x3 -#define MICRON_WBST 0x0 -#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \ - (MICRON_SIL << 3) | (MICRON_BL)) +#define MICRON_RAMTYPE_165 0x1 +#define MICRON_DDRTYPE_165 0x0 +#define MICRON_DEEPPD_165 0x1 +#define MICRON_B32NOT16_165 0x1 +#define MICRON_BANKALLOCATION_165 0x2 +#define MICRON_RAMSIZE_165 ((PHYS_SDRAM_1_SIZE/(1024*1024))/2) +#define MICRON_ADDRMUXLEGACY_165 0x1 +#define MICRON_CASWIDTH_165 0x5 +#define MICRON_RASWIDTH_165 0x2 +#define MICRON_LOCKSTATUS_165 0x0 +#define MICRON_V_MCFG_165 ((MICRON_LOCKSTATUS_165 << 30) | \ + (MICRON_RASWIDTH_165 << 24) | (MICRON_CASWIDTH_165 << 20) | \ + (MICRON_ADDRMUXLEGACY_165 << 19) | (MICRON_RAMSIZE_165 << 8) | \ + (MICRON_BANKALLOCATION_165 << 6) | \ + (MICRON_B32NOT16_165 << 4) | (MICRON_DEEPPD_165 << 3) | \ + (MICRON_DDRTYPE_165 << 2) | (MICRON_RAMTYPE_165)) + +#define MICRON_BL_165 0x2 +#define MICRON_SIL_165 0x0 +#define MICRON_CASL_165 0x3 +#define MICRON_WBST_165 0x0 +#define MICRON_V_MR_165 ((MICRON_WBST_165 << 9) | \ + (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ + (MICRON_BL_165))
/* * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns @@ -202,11 +204,11 @@ enum { #endif
#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG +#define V_ACTIMA_165 MICRON_V_ACTIMA_165 +#define V_ACTIMB_165 MICRON_V_ACTIMB_165 +#define V_MCFG MICRON_V_MCFG_165 #define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR +#define V_MR MICRON_V_MR_165 #endif
#ifdef CONFIG_OMAP3_NUMONYX_DDR
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz frederik@kriewitz.eu Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap3/sdrc.c | 28 ++++++++++++++------------ arch/arm/include/asm/arch-omap3/mem.h | 26 ------------------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + board/timll/devkit8000/devkit8000.c | 21 ++++++++++++++++++++ include/configs/devkit8000.h | 4 --- 5 files changed, 37 insertions(+), 43 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 2756024..a27b4b1 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early) sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
+ /* + * When called in the early context this may be SPL and we will + * need to set all of the timings. This ends up being board + * specific so we call a helper function to take care of this + * for us. Otherwise, to be safe, we need to copy the settings + * from the first bank to the second. We will setup CS0, + * then set cs_cfg to the appropriate value then try and + * setup CS1. + */ +#ifdef CONFIG_SPL_BUILD + get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr); +#endif if (early) { /* reset sdrc controller */ writel(SOFTRESET, &sdrc_base->sysconfig); @@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000); -/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need - * to prevent this to be build in non-SPL build */ #ifdef CONFIG_SPL_BUILD - /* - * If we use a SPL there is no x-loader nor config header so - * we have to do the job ourselfs - */ - - mcfg = V_MCFG; - ctrla = V_ACTIMA_165; - ctrlb = V_ACTIMB_165; - rfr_ctrl = V_RFR_CTRL; - mr = V_MR; - write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr); + make_cs1_contiguous(); + write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb, + rfr_ctrl, mr); #endif
} diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index a55553c..8c6dc3f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -198,32 +198,6 @@ enum { (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ (NUMONYX_TWTR_165 << 16))
-#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif - -#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG_165 -#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR_165 -#endif - -#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif - -#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif - -#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif - /* * GPMC settings - * Definitions is as per the following format diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e64410..a53d205 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,7 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *, u32 *, u32 *, u32 *, u32 *); void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff..a854b57 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif + +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings outself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + /* General SDRC config */ + *mcfg = MICRON_V_MCFG_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + + /* AC timings */ + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + + *mr = MICRON_V_MR_165; +} diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 6c51a27..d29481e 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -68,10 +68,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/* Hardware drivers */ - -/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* DM9000 */ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_DRIVER_DM9000 1
Hi Tom,
On 11/07/11 22:05, Tom Rini wrote:
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz frederik@kriewitz.eu Signed-off-by: Tom Rini trini@ti.com
arch/arm/cpu/armv7/omap3/sdrc.c | 28 ++++++++++++++------------ arch/arm/include/asm/arch-omap3/mem.h | 26 ------------------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + board/timll/devkit8000/devkit8000.c | 21 ++++++++++++++++++++ include/configs/devkit8000.h | 4 --- 5 files changed, 37 insertions(+), 43 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 2756024..a27b4b1 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early) sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- /*
* When called in the early context this may be SPL and we will* need to set all of the timings. This ends up being board* specific so we call a helper function to take care of this* for us. Otherwise, to be safe, we need to copy the settings* from the first bank to the second. We will setup CS0,* then set cs_cfg to the appropriate value then try and* setup CS1.*/+#ifdef CONFIG_SPL_BUILD
- get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+#endif if (early) { /* reset sdrc controller */ writel(SOFTRESET, &sdrc_base->sysconfig); @@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000);-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- to prevent this to be build in non-SPL build */
#ifdef CONFIG_SPL_BUILD
/** If we use a SPL there is no x-loader nor config header so* we have to do the job ourselfs*/mcfg = V_MCFG;ctrla = V_ACTIMA_165;ctrlb = V_ACTIMB_165;rfr_ctrl = V_RFR_CTRL;mr = V_MR;- write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr);
make_cs1_contiguous();write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,rfr_ctrl, mr);#endif
} diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index a55553c..8c6dc3f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -198,32 +198,6 @@ enum { (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ (NUMONYX_TWTR_165 << 16))
-#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif
-#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG_165 -#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR_165 -#endif
-#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif
/*
- GPMC settings -
- Definitions is as per the following format
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e64410..a53d205 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,7 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *, u32 *, u32 *, u32 *, u32 *);
This is kind of API declaration, so it is not obvious what values it takes and what should be the order of values here. Can this declaration also have variable names, so one would not have to look at the function call to understand what values should be supplied and what is the order?
void emif4_init(void); void gpmc_init(void); void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, diff --git a/board/timll/devkit8000/devkit8000.c b/board/timll/devkit8000/devkit8000.c index fee0dff..a854b57 100644 --- a/board/timll/devkit8000/devkit8000.c +++ b/board/timll/devkit8000/devkit8000.c @@ -138,3 +138,24 @@ int board_eth_init(bd_t *bis) return dm9000_initialize(bis); } #endif
+/*
- Routine: get_board_mem_timings
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings outself on the first bank. This
- provides the timing values back to the function that configures
- the memory.
- */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
- /* General SDRC config */
- *mcfg = MICRON_V_MCFG_165;
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- /* AC timings */
- *ctrla = MICRON_V_ACTIMA_165;
- *ctrlb = MICRON_V_ACTIMB_165;
- *mr = MICRON_V_MR_165;
+} diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 6c51a27..d29481e 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -68,10 +68,6 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
/* Hardware drivers */
-/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1
/* DM9000 */ #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_DRIVER_DM9000 1
On 11/08/2011 12:06 AM, Igor Grinberg wrote:
Hi Tom,
On 11/07/11 22:05, Tom Rini wrote:
This changes to making the board be responsible for providing the memory initialization timings in SPL and converts the devkit8000 to this framework. In SPL we try and initialize both CS0 and CS1.
Cc: Frederik Kriewitz frederik@kriewitz.eu Signed-off-by: Tom Rini trini@ti.com
arch/arm/cpu/armv7/omap3/sdrc.c | 28 ++++++++++++++------------ arch/arm/include/asm/arch-omap3/mem.h | 26 ------------------------- arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + board/timll/devkit8000/devkit8000.c | 21 ++++++++++++++++++++ include/configs/devkit8000.h | 4 --- 5 files changed, 37 insertions(+), 43 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 2756024..a27b4b1 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -148,6 +148,18 @@ void do_sdrc_init(u32 cs, u32 early) sdrc_actim_base0 = (struct sdrc_actim *)SDRC_ACTIM_CTRL0_BASE; sdrc_actim_base1 = (struct sdrc_actim *)SDRC_ACTIM_CTRL1_BASE;
- /*
* When called in the early context this may be SPL and we will* need to set all of the timings. This ends up being board* specific so we call a helper function to take care of this* for us. Otherwise, to be safe, we need to copy the settings* from the first bank to the second. We will setup CS0,* then set cs_cfg to the appropriate value then try and* setup CS1.*/+#ifdef CONFIG_SPL_BUILD
- get_board_mem_timings(&mcfg, &ctrla, &ctrlb, &rfr_ctrl, &mr);
+#endif if (early) { /* reset sdrc controller */ writel(SOFTRESET, &sdrc_base->sysconfig); @@ -164,22 +176,12 @@ void do_sdrc_init(u32 cs, u32 early)
writel(ENADLL | DLLPHASE_90, &sdrc_base->dlla_ctrl); sdelay(0x20000);-/* As long as V_MCFG and V_RFR_CTRL is not defined for all OMAP3 boards we need
- to prevent this to be build in non-SPL build */
#ifdef CONFIG_SPL_BUILD
/** If we use a SPL there is no x-loader nor config header so* we have to do the job ourselfs*/mcfg = V_MCFG;ctrla = V_ACTIMA_165;ctrlb = V_ACTIMB_165;rfr_ctrl = V_RFR_CTRL;mr = V_MR;- write_sdrc_timings(CS0, sdrc_actim_base0, mcfg, ctrla, ctrlb, rfr_ctrl, mr);
make_cs1_contiguous();write_sdrc_timings(CS0, sdrc_actim_base1, mcfg, ctrla, ctrlb,rfr_ctrl, mr);#endif
} diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index a55553c..8c6dc3f 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -198,32 +198,6 @@ enum { (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \ (NUMONYX_TWTR_165 << 16))
-#ifdef CONFIG_OMAP3_INFINEON_DDR -#define V_ACTIMA_165 INFINEON_V_ACTIMA_165 -#define V_ACTIMB_165 INFINEON_V_ACTIMB_165 -#endif
-#ifdef CONFIG_OMAP3_MICRON_DDR -#define V_ACTIMA_165 MICRON_V_ACTIMA_165 -#define V_ACTIMB_165 MICRON_V_ACTIMB_165 -#define V_MCFG MICRON_V_MCFG_165 -#define V_RFR_CTRL SDP_3430_SDRC_RFR_CTRL_165MHz -#define V_MR MICRON_V_MR_165 -#endif
-#ifdef CONFIG_OMAP3_NUMONYX_DDR -#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165 -#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165 -#endif
-#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165) -#error "Please choose the right DDR type in config header" -#endif
-#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL)) -#error "Please choose the right DDR type in config header" -#endif
/*
- GPMC settings -
- Definitions is as per the following format
diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index 9e64410..a53d205 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,7 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void get_board_mem_timings(u32 *, u32 *, u32 *, u32 *, u32 *);
This is kind of API declaration, so it is not obvious what values it takes and what should be the order of values here. Can this declaration also have variable names, so one would not have to look at the function call to understand what values should be supplied and what is the order?
Not a problem, just following existing style, but I'll change it (and identify_pop_memory()). for v2
A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE.
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/omap3/Makefile | 3 + arch/arm/cpu/armv7/omap3/spl_pop_probe.c | 84 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 3 files changed, 88 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap3/spl_pop_probe.c
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..772f3d4 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o +endif
COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/spl_pop_probe.c b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c new file mode 100644 index 0000000..ca66dd9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c @@ -0,0 +1,84 @@ +/* + * (C) Copyright 2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Tom Rini trini@ti.com + * + * Initial Code from: + * Richard Woodruff r-woodruff2@ti.com + * Jian Zhang jzhang@ti.com + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/mtd/nand.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h> + +#ifdef CONFIG_SPL_BUILD +static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE; + +/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{ + writeb(command, &gpmc_config->cs[0].nand_cmd); + + if (command == NAND_CMD_RESET) { + unsigned char ret_val; + nand_command(NAND_CMD_STATUS); + do { + /* Wait until ready */ + ret_val = readl(&gpmc_config->cs[0].nand_dat); + } while ((ret_val & 0x40) != 0x40); + } +} + +/* + * Many boards ship with a PoP chip of both NAND and DDR, so we need + * probe the NAND side, very earily, to see what it says and pass this + * along to the board. The board code will then use this information + * to decide what DDR timings to use. + */ +void identify_pop_memory(int *mfr, int *id) +{ + /* Make sure that we have setup GPMC for NAND correctly. */ + writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1); + writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2); + writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3); + writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4); + writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5); + writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6); + + /* Enable the GPMC Mapping */ + writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) | + (1 << 6)), &gpmc_config->cs[0].config7); + + sdelay(2000); + + /* Issue a RESET and then READID */ + nand_command(NAND_CMD_RESET); + nand_command(NAND_CMD_READID); + + writeb(0x0, &gpmc_config->cs[0].nand_adr); + + /* Read off the manufacturer and device id. */ + *mfr = readb(&gpmc_config->cs[0].nand_dat); + *id = readb(&gpmc_config->cs[0].nand_dat); +} +#endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index a53d205..2a8b5c7 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,7 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void identify_pop_memory(int *, int *); void get_board_mem_timings(u32 *, u32 *, u32 *, u32 *, u32 *); void emif4_init(void); void gpmc_init(void);
On 11/07/11 22:05, Tom Rini wrote:
A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE.
I don't see how POP is different from other types of packages in terms of DRAM. The same thing can be true also for non-POP packages. What I'm saying here is, I understand the necessity of that code, but why call it POP specific? If it is not POP specific, then please call it some other way (e.g. ...DRAM_NAND_PROBE). Also, hypothetically, some other means can be used for DRAM type identification, so it will be a good thing to split it, but again it is only hypothetically and it is only my thoughts, so you don't have to...
Signed-off-by: Tom Rini trini@ti.com
arch/arm/cpu/armv7/omap3/Makefile | 3 + arch/arm/cpu/armv7/omap3/spl_pop_probe.c | 84 +++++++++++++++++++++++++++ arch/arm/include/asm/arch-omap3/sys_proto.h | 1 + 3 files changed, 88 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap3/spl_pop_probe.c
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..772f3d4 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o +endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o diff --git a/arch/arm/cpu/armv7/omap3/spl_pop_probe.c b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c new file mode 100644 index 0000000..ca66dd9 --- /dev/null +++ b/arch/arm/cpu/armv7/omap3/spl_pop_probe.c @@ -0,0 +1,84 @@ +/*
- (C) Copyright 2011
- Texas Instruments, <www.ti.com>
- Author :
Tom Rini <trini@ti.com>
- Initial Code from:
Richard Woodruff <r-woodruff2@ti.com>
Jian Zhang <jzhang@ti.com>
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License as
- published by the Free Software Foundation; either version 2 of
- the License, or (at your option) any later version.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
The address is subject to change so probably it will be a good thing to drop the address part (but leave the rest).
- */
+#include <common.h> +#include <linux/mtd/nand.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h>
+#ifdef CONFIG_SPL_BUILD
no need for this #ifdef, the whole file compilation depends on that symbol being defined.
+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{
- writeb(command, &gpmc_config->cs[0].nand_cmd);
- if (command == NAND_CMD_RESET) {
unsigned char ret_val;nand_command(NAND_CMD_STATUS);
This recursion looks redundant. Why not just replace it with: writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
do {/* Wait until ready */ret_val = readl(&gpmc_config->cs[0].nand_dat);} while ((ret_val & 0x40) != 0x40);
Can't 0x40 magic be defined to have some more understandable name? Probably kind of NAND_CMD_READY mask?
- }
+}
+/*
- Many boards ship with a PoP chip of both NAND and DDR, so we need
- probe the NAND side, very earily, to see what it says and pass this
s/earily/early/
- along to the board. The board code will then use this information
- to decide what DDR timings to use.
- */
+void identify_pop_memory(int *mfr, int *id) +{
- /* Make sure that we have setup GPMC for NAND correctly. */
- writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
- writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
- writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
- writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
- writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
- writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
- /* Enable the GPMC Mapping */
- writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) |
(1 << 6)), &gpmc_config->cs[0].config7);- sdelay(2000);
- /* Issue a RESET and then READID */
- nand_command(NAND_CMD_RESET);
- nand_command(NAND_CMD_READID);
- writeb(0x0, &gpmc_config->cs[0].nand_adr);
It would be nice to have a comment, why the above is needed.
- /* Read off the manufacturer and device id. */
- *mfr = readb(&gpmc_config->cs[0].nand_dat);
- *id = readb(&gpmc_config->cs[0].nand_dat);
+} +#endif diff --git a/arch/arm/include/asm/arch-omap3/sys_proto.h b/arch/arm/include/asm/arch-omap3/sys_proto.h index a53d205..2a8b5c7 100644 --- a/arch/arm/include/asm/arch-omap3/sys_proto.h +++ b/arch/arm/include/asm/arch-omap3/sys_proto.h @@ -38,6 +38,7 @@ void per_clocks_enable(void); void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); +void identify_pop_memory(int *, int *);
Same thing, what are the parameters? What is the order?
void get_board_mem_timings(u32 *, u32 *, u32 *, u32 *, u32 *); void emif4_init(void); void gpmc_init(void);
On 11/08/2011 12:45 AM, Igor Grinberg wrote:
On 11/07/11 22:05, Tom Rini wrote:
A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE.
I don't see how POP is different from other types of packages in terms of DRAM. The same thing can be true also for non-POP packages. What I'm saying here is, I understand the necessity of that code, but why call it POP specific? If it is not POP specific, then please call it some other way (e.g. ...DRAM_NAND_PROBE). Also, hypothetically, some other means can be used for DRAM type identification, so it will be a good thing to split it, but again it is only hypothetically and it is only my thoughts, so you don't have to...
Well, that gets at why I called it spl_pop_probe. If you have a POP package, this is how you would do the probe. I can see in theory wanting to probe NAND as a way to see board rev on a non-POP package, but I'd like to see a real example first.
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..772f3d4 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o +endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
But then it would build for both SPL and non-SPL cases.
[snip]
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
The address is subject to change so probably it will be a good thing to drop the address part (but leave the rest).
Just following existing examples.
- */
+#include <common.h> +#include <linux/mtd/nand.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h>
+#ifdef CONFIG_SPL_BUILD
no need for this #ifdef, the whole file compilation depends on that symbol being defined.
True, will fix, thanks.
+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{
- writeb(command, &gpmc_config->cs[0].nand_cmd);
- if (command == NAND_CMD_RESET) {
unsigned char ret_val;nand_command(NAND_CMD_STATUS);This recursion looks redundant. Why not just replace it with: writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
OK, thanks.
do {/* Wait until ready */ret_val = readl(&gpmc_config->cs[0].nand_dat);} while ((ret_val & 0x40) != 0x40);Can't 0x40 magic be defined to have some more understandable name? Probably kind of NAND_CMD_READY mask?
I'll see if the datasheet defines this particular bit of magic.
- }
+}
+/*
- Many boards ship with a PoP chip of both NAND and DDR, so we need
- probe the NAND side, very earily, to see what it says and pass this
s/earily/early/
Thanks.
- along to the board. The board code will then use this information
- to decide what DDR timings to use.
- */
+void identify_pop_memory(int *mfr, int *id) +{
- /* Make sure that we have setup GPMC for NAND correctly. */
- writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
- writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
- writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
- writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
- writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
- writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
- /* Enable the GPMC Mapping */
- writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) |
(1 << 6)), &gpmc_config->cs[0].config7);- sdelay(2000);
- /* Issue a RESET and then READID */
- nand_command(NAND_CMD_RESET);
- nand_command(NAND_CMD_READID);
- writeb(0x0, &gpmc_config->cs[0].nand_adr);
It would be nice to have a comment, why the above is needed.
OK.
-- Tom
Hi Tom,
On 11/08/11 17:21, Tom Rini wrote:
On 11/08/2011 12:45 AM, Igor Grinberg wrote:
On 11/07/11 22:05, Tom Rini wrote:
A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE.
I don't see how POP is different from other types of packages in terms of DRAM. The same thing can be true also for non-POP packages. What I'm saying here is, I understand the necessity of that code, but why call it POP specific? If it is not POP specific, then please call it some other way (e.g. ...DRAM_NAND_PROBE). Also, hypothetically, some other means can be used for DRAM type identification, so it will be a good thing to split it, but again it is only hypothetically and it is only my thoughts, so you don't have to...
Well, that gets at why I called it spl_pop_probe. If you have a POP package, this is how you would do the probe. I can see in theory wanting to probe NAND as a way to see board rev on a non-POP package, but I'd like to see a real example first.
That's the problem we see in Linux OMAP... some guys don't think forward and submit stuff on a per case basis, then when it comes to a bit different case, they are trying to reuse (which is fine) and end up renaming stuff all around - generating huge diff stat. Why not just do the generic stuff from the start of it? Why wait for a new case? It is pretty simple, just don't name it POP, so it can serve w/o any confusion for more cases.
diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 8e85891..772f3d4 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -31,6 +31,9 @@ COBJS += board.o COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +ifdef CONFIG_SPL_BUILD +COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o +endif
Can't CONFIG_SPL_OMAP3_..._PROBE symbol default to "no" and depend on CONFIG_SPL_BUILD, so you don't need to enclose it in #ifdef?
But then it would build for both SPL and non-SPL cases.
No, it should not. What do you think of the following: In the Makefile have only: COBJS-$(CONFIG_SPL_OMAP3_POP_PROBE) += spl_pop_probe.o
Then in the spl_pop_probe.c have this type of check: #ifndef CONFIG_SPL_BUILD # error CONFIG_SPL_OMAP3_POP_PROBE requires CONFIG_SPL_BUILD #endif
This way, you require the CONFIG_SPL_OMAP3_POP_PROBE symbol be a part of the CONFIG_SPL_BUILD symbols group.
[snip]
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- MA 02111-1307 USA
The address is subject to change so probably it will be a good thing to drop the address part (but leave the rest).
Just following existing examples.
Existing examples can be wrong and as Wolfgang said, it is not a good justification, but I don't really mind, just trying to raise people awareness.
- */
+#include <common.h> +#include <linux/mtd/nand.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/mem.h>
+#ifdef CONFIG_SPL_BUILD
no need for this #ifdef, the whole file compilation depends on that symbol being defined.
True, will fix, thanks.
+static struct gpmc *gpmc_config = (struct gpmc *)GPMC_BASE;
+/* nand_command: Send a flash command to the flash chip */ +static void nand_command(u8 command) +{
- writeb(command, &gpmc_config->cs[0].nand_cmd);
- if (command == NAND_CMD_RESET) {
unsigned char ret_val;nand_command(NAND_CMD_STATUS);This recursion looks redundant. Why not just replace it with: writeb(NAND_CMD_STATUS, &gpmc_config->cs[0].nand_cmd);
OK, thanks.
do {/* Wait until ready */ret_val = readl(&gpmc_config->cs[0].nand_dat);} while ((ret_val & 0x40) != 0x40);Can't 0x40 magic be defined to have some more understandable name? Probably kind of NAND_CMD_READY mask?
I'll see if the datasheet defines this particular bit of magic.
- }
+}
+/*
- Many boards ship with a PoP chip of both NAND and DDR, so we need
- probe the NAND side, very earily, to see what it says and pass this
s/earily/early/
Thanks.
- along to the board. The board code will then use this information
- to decide what DDR timings to use.
- */
+void identify_pop_memory(int *mfr, int *id) +{
- /* Make sure that we have setup GPMC for NAND correctly. */
- writel(M_NAND_GPMC_CONFIG1, &gpmc_config->cs[0].config1);
- writel(M_NAND_GPMC_CONFIG2, &gpmc_config->cs[0].config2);
- writel(M_NAND_GPMC_CONFIG3, &gpmc_config->cs[0].config3);
- writel(M_NAND_GPMC_CONFIG4, &gpmc_config->cs[0].config4);
- writel(M_NAND_GPMC_CONFIG5, &gpmc_config->cs[0].config5);
- writel(M_NAND_GPMC_CONFIG6, &gpmc_config->cs[0].config6);
- /* Enable the GPMC Mapping */
- writel((((GPMC_SIZE_128M & 0xF) << 8) | ((NAND_BASE >> 24) & 0x3F) |
(1 << 6)), &gpmc_config->cs[0].config7);- sdelay(2000);
- /* Issue a RESET and then READID */
- nand_command(NAND_CMD_RESET);
- nand_command(NAND_CMD_READID);
- writeb(0x0, &gpmc_config->cs[0].nand_adr);
It would be nice to have a comment, why the above is needed.
OK.
-- Tom
On 11/09/2011 04:04 AM, Igor Grinberg wrote:
Hi Tom,
On 11/08/11 17:21, Tom Rini wrote:
On 11/08/2011 12:45 AM, Igor Grinberg wrote:
On 11/07/11 22:05, Tom Rini wrote:
A number of boards are populated with a PoP chip for both DDR and NAND memory. So to determine DDR timings the NAND chip needs to be probed and mfr/id returned to the board to make decisions with. All of this code is put into spl_pop_probe.c and controlled via CONFIG_SPL_OMAP3_POP_PROBE.
I don't see how POP is different from other types of packages in terms of DRAM. The same thing can be true also for non-POP packages. What I'm saying here is, I understand the necessity of that code, but why call it POP specific? If it is not POP specific, then please call it some other way (e.g. ...DRAM_NAND_PROBE). Also, hypothetically, some other means can be used for DRAM type identification, so it will be a good thing to split it, but again it is only hypothetically and it is only my thoughts, so you don't have to...
Well, that gets at why I called it spl_pop_probe. If you have a POP package, this is how you would do the probe. I can see in theory wanting to probe NAND as a way to see board rev on a non-POP package, but I'd like to see a real example first.
That's the problem we see in Linux OMAP... some guys don't think forward and submit stuff on a per case basis, then when it comes to a bit different case, they are trying to reuse (which is fine) and end up renaming stuff all around - generating huge diff stat. Why not just do the generic stuff from the start of it? Why wait for a new case? It is pretty simple, just don't name it POP, so it can serve w/o any confusion for more cases.
I'll do the rename for a v3. I just don't see renaming once another use comes up as a problem, we aren't using CVS anymore ;)
This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h>. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC.
Cc: Dirk Behme dirk.behme@gmail.com Beagleboard rev C5, xM rev A: Tested-by: Tom Rini trini@ti.com Beagleboard xM rev C: Tested-by: Matt Ranostay mranostay@gmail.com Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter mporter@ti.com Signed-off-by: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-omap3/mem.h | 23 ++++++++++ board/ti/beagle/beagle.c | 72 ++++++++++++++++++++++++++++++++- board/ti/beagle/config.mk | 33 --------------- include/configs/omap3_beagle.h | 55 +++++++++++++++++++++++++ 4 files changed, 148 insertions(+), 35 deletions(-) delete mode 100644 board/ti/beagle/config.mk
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 8c6dc3f..f467ba9 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -159,6 +159,29 @@ enum { (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ (MICRON_BL_165))
+/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | \ + (MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) | \ + (MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) | \ + (MICRON_TRRD_200 << 9) | (MICRON_TDPL_200 << 6) | \ + (MICRON_TDAL_200)) + +#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | \ + (MICRON_XSR_200 << 0) | (MICRON_TXP_200 << 8) | \ + (MICRON_TWTR_200 << 16)) + /* * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns * ACTIMA diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9482c5e..4ab2d8e 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -34,9 +34,11 @@ #include <status_led.h> #endif #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> @@ -135,6 +137,70 @@ int get_board_revision(void) return revision; }
+#ifdef CONFIG_SPL_BUILD +/* + * Routine: board_early_sdrc_init + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings outself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. If we can't identify it then + * we know it's an xM. + */ + identify_pop_memory(&pop_mfr, &pop_id); + + /* + * We cannot use the MICRON_MCFG_165 as it relies on + * PHYS_SDRAM_1_SIZE being defined to the correct value, and we + * don't know that value until runtime. + */ + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_C4: + if ((pop_mfr == NAND_MFR_STMICRO) && (pop_id == 0xba)) { + *mcfg = 0x04590099; + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + } else if ((pop_mfr == NAND_MFR_MICRON) && (pop_id == 0xbc)) { + /* Beagleboard Rev C5 */ + *mcfg = 0x03588099; + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + break; + } + case REVISION_XM_A: + case REVISION_XM_B: + case REVISION_XM_C: + if (pop_mfr == 0) { + *mcfg = 0x03588099; + *ctrla = MICRON_V_ACTIMA_200; + *ctrlb = MICRON_V_ACTIMB_200; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + } else { + *mcfg = 0x04590099; + *ctrla = NUMONYX_V_ACTIMA_165; + *ctrlb = NUMONYX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } + break; + default: + *mcfg = 0x02584099; + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_expansion_id * Description: This function checks for expansion board by checking I2C @@ -367,7 +433,7 @@ void set_muxconf_regs(void) MUX_BEAGLE(); }
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -476,6 +542,7 @@ int ehci_hcd_init(void)
#endif /* CONFIG_USB_EHCI */
+#ifndef CONFIG_SPL_BUILD /* * This command returns the status of the user button on beagle xM * Input - none @@ -528,3 +595,4 @@ U_BOOT_CMD( "Return the status of the BeagleBoard USER button", "" ); +#endif diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk deleted file mode 100644 index cf055db..0000000 --- a/board/ti/beagle/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ebb572e..f444a7c 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -390,4 +390,59 @@
#define CONFIG_OMAP3_SPI
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_POP_PROBE +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */
On 11/07/11 22:05, Tom Rini wrote:
This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h>. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC.
Cc: Dirk Behme dirk.behme@gmail.com Beagleboard rev C5, xM rev A: Tested-by: Tom Rini trini@ti.com Beagleboard xM rev C: Tested-by: Matt Ranostay mranostay@gmail.com Beagleboard rev B7, C2, xM rev B: Tested-by: Matt Porter mporter@ti.com Signed-off-by: Tom Rini trini@ti.com
arch/arm/include/asm/arch-omap3/mem.h | 23 ++++++++++ board/ti/beagle/beagle.c | 72 ++++++++++++++++++++++++++++++++- board/ti/beagle/config.mk | 33 --------------- include/configs/omap3_beagle.h | 55 +++++++++++++++++++++++++ 4 files changed, 148 insertions(+), 35 deletions(-) delete mode 100644 board/ti/beagle/config.mk
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 8c6dc3f..f467ba9 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -159,6 +159,29 @@ enum { (MICRON_CASL_165 << 4) | (MICRON_SIL_165 << 3) | \ (MICRON_BL_165))
+/* Micron part (200MHz optimized) 5 ns */ +#define MICRON_TDAL_200 6 +#define MICRON_TDPL_200 3 +#define MICRON_TRRD_200 2 +#define MICRON_TRCD_200 3 +#define MICRON_TRP_200 3 +#define MICRON_TRAS_200 8 +#define MICRON_TRC_200 11 +#define MICRON_TRFC_200 15 +#define MICRON_V_ACTIMA_200 ((MICRON_TRFC_200 << 27) | \
(MICRON_TRC_200 << 22) | (MICRON_TRAS_200 << 18) | \(MICRON_TRP_200 << 15) | (MICRON_TRCD_200 << 12) | \(MICRON_TRRD_200 << 9) | (MICRON_TDPL_200 << 6) | \(MICRON_TDAL_200))+#define MICRON_TWTR_200 2 +#define MICRON_TCKE_200 4 +#define MICRON_TXP_200 2 +#define MICRON_XSR_200 23 +#define MICRON_V_ACTIMB_200 ((MICRON_TCKE_200 << 12) | \
(MICRON_XSR_200 << 0) | (MICRON_TXP_200 << 8) | \(MICRON_TWTR_200 << 16))/*
- NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
- ACTIMA
diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 9482c5e..4ab2d8e 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -1,5 +1,5 @@ /*
- (C) Copyright 2004-2008
- (C) Copyright 2004-2011
- Texas Instruments, <www.ti.com>
- Author :
@@ -34,9 +34,11 @@ #include <status_led.h> #endif #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> @@ -135,6 +137,70 @@ int get_board_revision(void) return revision; }
+#ifdef CONFIG_SPL_BUILD +/*
- Routine: board_early_sdrc_init
s/board_early_sdrc_init/get_board_mem_timings/
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings outself on both banks.
s/outself/ourself/
- */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
- int pop_mfr, pop_id;
- /*
* We need to identify what PoP memory is on the board so that* we know what timings to use. If we can't identify it then* we know it's an xM.*/- identify_pop_memory(&pop_mfr, &pop_id);
- /*
* We cannot use the MICRON_MCFG_165 as it relies on* PHYS_SDRAM_1_SIZE being defined to the correct value, and we* don't know that value until runtime.*/- *mr = MICRON_V_MR_165;
- switch (get_board_revision()) {
- case REVISION_C4:
if ((pop_mfr == NAND_MFR_STMICRO) && (pop_id == 0xba)) {
No need for extra parenthesis.
*mcfg = 0x04590099;*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
This will look much better if it will be aligned.
break;} else if ((pop_mfr == NAND_MFR_MICRON) && (pop_id == 0xbc)) {
No need for extra parenthesis.
/* Beagleboard Rev C5 */*mcfg = 0x03588099;*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
This will look much better if it will be aligned.
break;}- case REVISION_XM_A:
- case REVISION_XM_B:
- case REVISION_XM_C:
if (pop_mfr == 0) {*mcfg = 0x03588099;*ctrla = MICRON_V_ACTIMA_200;*ctrlb = MICRON_V_ACTIMB_200;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz;
Same here.
} else {*mcfg = 0x04590099;*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
ditto
}break;- default:
*mcfg = 0x02584099;*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
ditto
- }
+} +#endif
/*
- Routine: get_expansion_id
- Description: This function checks for expansion board by checking I2C
@@ -367,7 +433,7 @@ void set_muxconf_regs(void) MUX_BEAGLE(); }
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); @@ -476,6 +542,7 @@ int ehci_hcd_init(void)
#endif /* CONFIG_USB_EHCI */
+#ifndef CONFIG_SPL_BUILD /*
- This command returns the status of the user button on beagle xM
- Input - none
@@ -528,3 +595,4 @@ U_BOOT_CMD( "Return the status of the BeagleBoard USER button", "" ); +#endif diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk deleted file mode 100644 index cf055db..0000000 --- a/board/ti/beagle/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 -# Texas Instruments, <www.ti.com> -# -# Beagle Board uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved)
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000
Removing needless crap is a very good thing, but does not belong to this patch, is it?
diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ebb572e..f444a7c 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -390,4 +390,59 @@
#define CONFIG_OMAP3_SPI
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_OMAP3_POP_PROBE +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}+#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- 64 bytes before this address should be set aside for u-boot.img's
- header. That is 0x800FFFC0--0x80100000 should not be used for any
- other needs.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#endif /* __CONFIG_H */
On 11/08/2011 12:57 AM, Igor Grinberg wrote:
On 11/07/11 22:05, Tom Rini wrote:
This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h>. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC.
[snip]
+#ifdef CONFIG_SPL_BUILD +/*
- Routine: board_early_sdrc_init
s/board_early_sdrc_init/get_board_mem_timings/
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings outself on both banks.
s/outself/ourself/
Thanks.
[snip]
- case REVISION_C4:
if ((pop_mfr == NAND_MFR_STMICRO) && (pop_id == 0xba)) {No need for extra parenthesis.
I'll double check all these cases, thanks.
*mcfg = 0x04590099;*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;This will look much better if it will be aligned.
It's not in CodingStyle tho ;)
[snip]
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000
Removing needless crap is a very good thing, but does not belong to this patch, is it?
I thought I said in this commit message, but I know I did for am3517 evm/crane, we change CONFIG_SYS_TEXT_BASE which is why we remove this file here. It could be done as a two-step if it's a hard objection tho.
On 11/08/11 17:28, Tom Rini wrote:
On 11/08/2011 12:57 AM, Igor Grinberg wrote:
On 11/07/11 22:05, Tom Rini wrote:
This introduces 200MHz Micron parts timing information based on x-loader to <asm/arch-omap3/mem.h>. The memory init logic is also based on what x-loader does in these cases. Note that while previously u-boot would be flashed in with SW ECC in this case it now must be flashed with HW ECC.
[snip]
+#ifdef CONFIG_SPL_BUILD +/*
- Routine: board_early_sdrc_init
s/board_early_sdrc_init/get_board_mem_timings/
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings outself on both banks.
s/outself/ourself/
Thanks.
[snip]
- case REVISION_C4:
if ((pop_mfr == NAND_MFR_STMICRO) && (pop_id == 0xba)) {No need for extra parenthesis.
I'll double check all these cases, thanks.
*mcfg = 0x04590099;*ctrla = NUMONYX_V_ACTIMA_165;*ctrlb = NUMONYX_V_ACTIMB_165;*rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;This will look much better if it will be aligned.
It's not in CodingStyle tho ;)
Right, you don't have to, but it will look better...
[snip]
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000
Removing needless crap is a very good thing, but does not belong to this patch, is it?
I thought I said in this commit message, but I know I did for am3517 evm/crane, we change CONFIG_SYS_TEXT_BASE which is why we remove this file here. It could be done as a two-step if it's a hard objection tho.
Yeah, I've sent this email before I saw the AM3517 changes. Ok.
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. We don't calculate the MCFG value here for the Micron parts as the provided one assumes a memory size which is incorrect.
Signed-off-by: Tom Rini trini@ti.com --- arch/arm/include/asm/arch-omap3/mem.h | 38 +++++++++++++++++++++ board/ti/evm/config.mk | 33 ------------------ board/ti/evm/evm.c | 42 ++++++++++++++++++++++- include/configs/omap3_evm.h | 58 +++++++++++++++++++++++++++++++-- 4 files changed, 133 insertions(+), 38 deletions(-) delete mode 100644 board/ti/evm/config.mk
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index f467ba9..7b0aaa1 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -60,6 +60,44 @@ enum { #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+/* Hynix part of AM/DM37xEVM (200MHz optimized) + * ACTIMA + * TDAL = 6 + * TDPL (Twr) = 3 + * TRRD = 2 + * TRCD = 4 + * TRP = 3 + * TRAS = 8 + * TRC = 11 + * TRFC = 18 + * ACTIMB + * TWTR = 2 + * TCKE = 1 + * TXP = 1 + * TXSR = 28 + */ +#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 ((HYNIX_TRFC_200 << 27) | \ + (HYNIX_TRC_200 << 22) | (HYNIX_TRAS_200 << 18) | \ + (HYNIX_TRP_200 << 15) | (HYNIX_TRCD_200 << 12) | \ + (HYNIX_TRRD_200 << 9) | (HYNIX_TDPL_200 << 6) | \ + (HYNIX_TDAL_200)) + +#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 (((HYNIX_TCKE_200 << 12) | \ + (HYNIX_XSR_200 << 0)) | (HYNIX_TXP_200 << 8) | \ + (HYNIX_TWTR_200 << 16)) + /* Infineon part of 3430SDP (165MHz optimized) 6.06ns * ACTIMA * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6 diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, <www.ti.com> -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index b17c0fb..debf564 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2004-2008 + * (C) Copyright 2004-2011 * Texas Instruments, <www.ti.com> * * Author : @@ -119,6 +119,44 @@ int board_init(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings outself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + int pop_mfr, pop_id; + + /* + * We need to identify what PoP memory is on the board so that + * we know what timings to use. If we can't identify it then + * we know it's an xM. + */ + identify_pop_memory(&pop_mfr, &pop_id); + + if ((pop_mfr == 0xad) && (pop_id == 0xbc)) { + *ctrla = HYNIX_V_ACTIMA_200; + *ctrlb = HYNIX_V_ACTIMB_200; + *mcfg = 0x03588099; + } else { + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + /* + * MICRON_V_MCFG_165 would be correct here except that + * we have 128MB not PHYS_SDRAM_1_SIZE (32MB) + */ + *mcfg = 0x02584099; + } + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + *mr = MICRON_V_MR_165; +} +#endif + /* * Routine: misc_init_r * Description: Init ethernet (done here so udelay works) @@ -223,7 +261,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 7a76288..511b599 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -101,9 +101,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1
-/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1 - /* USB * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard * Enable CONFIG_MUSB_UDD for Device functionalities. @@ -360,4 +357,59 @@ #define CONFIG_BOOTP_HOSTNAME 0x00000004 #define CONFIG_BOOTP_BOOTPATH 0x00000010
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_OMAP3_POP_PROBE +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */
On 11/08/11 00:03, Tom Rini wrote:
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. We don't calculate the MCFG value here for the Micron parts as the provided one assumes a memory size which is incorrect.
Signed-off-by: Tom Rini trini@ti.com
arch/arm/include/asm/arch-omap3/mem.h | 38 +++++++++++++++++++++ board/ti/evm/config.mk | 33 ------------------ board/ti/evm/evm.c | 42 ++++++++++++++++++++++- include/configs/omap3_evm.h | 58 +++++++++++++++++++++++++++++++-- 4 files changed, 133 insertions(+), 38 deletions(-) delete mode 100644 board/ti/evm/config.mk
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index f467ba9..7b0aaa1 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -60,6 +60,44 @@ enum { #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+/* Hynix part of AM/DM37xEVM (200MHz optimized)
- ACTIMA
- TDAL = 6
- TDPL (Twr) = 3
- TRRD = 2
- TRCD = 4
- TRP = 3
- TRAS = 8
- TRC = 11
- TRFC = 18
- ACTIMB
- TWTR = 2
- TCKE = 1
- TXP = 1
- TXSR = 28
- */
+#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 ((HYNIX_TRFC_200 << 27) | \
(HYNIX_TRC_200 << 22) | (HYNIX_TRAS_200 << 18) | \(HYNIX_TRP_200 << 15) | (HYNIX_TRCD_200 << 12) | \(HYNIX_TRRD_200 << 9) | (HYNIX_TDPL_200 << 6) | \(HYNIX_TDAL_200))+#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 (((HYNIX_TCKE_200 << 12) | \
(HYNIX_XSR_200 << 0)) | (HYNIX_TXP_200 << 8) | \(HYNIX_TWTR_200 << 16))/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- ACTIMA
- TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, <www.ti.com> -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved)
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000
Does not belong to this patch, is it?
diff --git a/board/ti/evm/evm.c b/board/ti/evm/evm.c index b17c0fb..debf564 100644 --- a/board/ti/evm/evm.c +++ b/board/ti/evm/evm.c @@ -1,5 +1,5 @@ /*
- (C) Copyright 2004-2008
- (C) Copyright 2004-2011
- Texas Instruments, <www.ti.com>
- Author :
@@ -119,6 +119,44 @@ int board_init(void) return 0; }
+#ifdef CONFIG_SPL_BUILD +/*
- Routine: get_board_mem_timings
- Description: If we use SPL then there is no x-loader nor config header
- so we have to setup the DDR timings outself on the first bank. This
- provides the timing values back to the function that configures
- the memory.
- */
+void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl,
u32 *mr)+{
- int pop_mfr, pop_id;
- /*
* We need to identify what PoP memory is on the board so that* we know what timings to use. If we can't identify it then* we know it's an xM.
This comment should be slightly adjusted, evm is not beagle...
*/- identify_pop_memory(&pop_mfr, &pop_id);
- if ((pop_mfr == 0xad) && (pop_id == 0xbc)) {
No need for extra parenthesis.
*ctrla = HYNIX_V_ACTIMA_200;*ctrlb = HYNIX_V_ACTIMB_200;*mcfg = 0x03588099;- } else {
*ctrla = MICRON_V_ACTIMA_165;*ctrlb = MICRON_V_ACTIMB_165;/** MICRON_V_MCFG_165 would be correct here except that* we have 128MB not PHYS_SDRAM_1_SIZE (32MB)*/*mcfg = 0x02584099;- }
- *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
- *mr = MICRON_V_MR_165;
+} +#endif
/*
- Routine: misc_init_r
- Description: Init ethernet (done here so udelay works)
@@ -223,7 +261,7 @@ int board_eth_init(bd_t *bis) } #endif /* CONFIG_CMD_NET */
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 7a76288..511b599 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -101,9 +101,6 @@ #define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1
-/* DDR - I use Micron DDR */ -#define CONFIG_OMAP3_MICRON_DDR 1
/* USB
- Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- Enable CONFIG_MUSB_UDD for Device functionalities.
@@ -360,4 +357,59 @@ #define CONFIG_BOOTP_HOSTNAME 0x00000004 #define CONFIG_BOOTP_BOOTPATH 0x00000010
+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) /* 45 KB */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
+#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_OMAP3_POP_PROBE +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
+/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
10, 11, 12, 13}+#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
CONFIG_SYS_NAND_ECCSIZE)+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
CONFIG_SYS_NAND_ECCSTEPS)+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
+/*
- 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- 64 bytes before this address should be set aside for u-boot.img's
- header. That is 0x800FFFC0--0x80100000 should not be used for any
- other needs.
- */
+#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
#endif /* __CONFIG_H */
On 11/08/2011 01:02 AM, Igor Grinberg wrote:
On 11/08/11 00:03, Tom Rini wrote:
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. We don't calculate the MCFG value here for the Micron parts as the provided one assumes a memory size which is incorrect.
Signed-off-by: Tom Rini trini@ti.com
arch/arm/include/asm/arch-omap3/mem.h | 38 +++++++++++++++++++++ board/ti/evm/config.mk | 33 ------------------ board/ti/evm/evm.c | 42 ++++++++++++++++++++++- include/configs/omap3_evm.h | 58 +++++++++++++++++++++++++++++++-- 4 files changed, 133 insertions(+), 38 deletions(-) delete mode 100644 board/ti/evm/config.mk
diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index f467ba9..7b0aaa1 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -60,6 +60,44 @@ enum { #define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \ (DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
+/* Hynix part of AM/DM37xEVM (200MHz optimized)
- ACTIMA
- TDAL = 6
- TDPL (Twr) = 3
- TRRD = 2
- TRCD = 4
- TRP = 3
- TRAS = 8
- TRC = 11
- TRFC = 18
- ACTIMB
- TWTR = 2
- TCKE = 1
- TXP = 1
- TXSR = 28
- */
+#define HYNIX_TDAL_200 6 +#define HYNIX_TDPL_200 3 +#define HYNIX_TRRD_200 2 +#define HYNIX_TRCD_200 4 +#define HYNIX_TRP_200 3 +#define HYNIX_TRAS_200 8 +#define HYNIX_TRC_200 11 +#define HYNIX_TRFC_200 18 +#define HYNIX_V_ACTIMA_200 ((HYNIX_TRFC_200 << 27) | \
(HYNIX_TRC_200 << 22) | (HYNIX_TRAS_200 << 18) | \(HYNIX_TRP_200 << 15) | (HYNIX_TRCD_200 << 12) | \(HYNIX_TRRD_200 << 9) | (HYNIX_TDPL_200 << 6) | \(HYNIX_TDAL_200))+#define HYNIX_TWTR_200 2 +#define HYNIX_TCKE_200 1 +#define HYNIX_TXP_200 1 +#define HYNIX_XSR_200 28 +#define HYNIX_V_ACTIMB_200 (((HYNIX_TCKE_200 << 12) | \
(HYNIX_XSR_200 << 0)) | (HYNIX_TXP_200 << 8) | \(HYNIX_TWTR_200 << 16))/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- ACTIMA
- TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
diff --git a/board/ti/evm/config.mk b/board/ti/evm/config.mk deleted file mode 100644 index d173eef..0000000 --- a/board/ti/evm/config.mk +++ /dev/null @@ -1,33 +0,0 @@ -# -# (C) Copyright 2006 - 2008 -# Texas Instruments, <www.ti.com> -# -# EVM uses OMAP3 (ARM-CortexA8) cpu -# see http://www.ti.com/ for more information on Texas Instruments -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved)
-# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000
Does not belong to this patch, is it?
Same rational as beagle, we change CONFIG_SYS_TEXT_BASE, which I guess I should note more obviously in the commit message.
- /*
* We need to identify what PoP memory is on the board so that* we know what timings to use. If we can't identify it then* we know it's an xM.This comment should be slightly adjusted, evm is not beagle...
Ha, oops, thanks.
*/- identify_pop_memory(&pop_mfr, &pop_id);
- if ((pop_mfr == 0xad) && (pop_id == 0xbc)) {
No need for extra parenthesis.
I'll go double check, thanks.
On Tue, Nov 8, 2011 at 8:29 AM, Tom Rini trini@ti.com wrote:
On 11/08/2011 01:02 AM, Igor Grinberg wrote:
On 11/08/11 00:03, Tom Rini wrote:
Add Hynix 200MHz timing information to <asm/arch-omap3/mem.h>. We don't calculate the MCFG value here for the Micron parts as the provided one assumes a memory size which is incorrect.
Signed-off-by: Tom Rini trini@ti.com
arch/arm/include/asm/arch-omap3/mem.h | 38 +++++++++++++++++++++ board/ti/evm/config.mk | 33 ------------------ board/ti/evm/evm.c | 42 ++++++++++++++++++++++- include/configs/omap3_evm.h | 58 +++++++++++++++++++++++++++++++-- 4 files changed, 133 insertions(+), 38 deletions(-) delete mode 100644 board/ti/evm/config.mk
[snip]
- */
- identify_pop_memory(&pop_mfr, &pop_id);
- if ((pop_mfr == 0xad) && (pop_id == 0xbc)) {
No need for extra parenthesis.
I'll go double check, thanks.
And 0xad should be NAND_MFR_HYNIX, I'll fix that.
The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE
Cc: Vaibhav Hiremath hvaibhav@ti.com Signed-off-by: Tom Rini trini@ti.com --- board/logicpd/am3517evm/am3517evm.c | 2 +- board/logicpd/am3517evm/config.mk | 30 ------------------- include/configs/am3517_evm.h | 55 +++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 31 deletions(-) delete mode 100644 board/logicpd/am3517evm/config.mk
diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index c0a006a..0a105bf 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -76,7 +76,7 @@ void set_muxconf_regs(void) MUX_AM3517EVM(); }
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/logicpd/am3517evm/config.mk b/board/logicpd/am3517evm/config.mk deleted file mode 100644 index 71ec5d0..0000000 --- a/board/logicpd/am3517evm/config.mk +++ /dev/null @@ -1,30 +0,0 @@ -# -# Author: Vaibhav Hiremath hvaibhav@ti.com -# -# Based on ti/evm/config.mk -# -# Copyright (C) 2010 -# Texas Instruments Incorporated - http://www.ti.com/ -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 1c70b9d..9cc7fa1 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -331,4 +331,59 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */
The only change of note is that we move from 0x80008000 to 0x80100000 for CONFIG_SYS_TEXT_BASE
Cc: Nagendra T S nagendra@mistralsolutions.com Tested-by: Koen Kooi k-kooi@ti.com Signed-off-by: Tom Rini trini@ti.com --- board/ti/am3517crane/am3517crane.c | 2 +- board/ti/am3517crane/config.mk | 29 ------------------- include/configs/am3517_crane.h | 55 ++++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 30 deletions(-) delete mode 100644 board/ti/am3517crane/config.mk
diff --git a/board/ti/am3517crane/am3517crane.c b/board/ti/am3517crane/am3517crane.c index cd5683d..436645a 100644 --- a/board/ti/am3517crane/am3517crane.c +++ b/board/ti/am3517crane/am3517crane.c @@ -75,7 +75,7 @@ void set_muxconf_regs(void) MUX_AM3517CRANE(); }
-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/ti/am3517crane/config.mk b/board/ti/am3517crane/config.mk deleted file mode 100644 index c6a18b5..0000000 --- a/board/ti/am3517crane/config.mk +++ /dev/null @@ -1,29 +0,0 @@ -# -# Author: Srinath R srinath@mistralsolutions.com -# -# Based on logicpd/am3517evm/config.mk -# -# Copyright (C) 2011 Mistral Solutions Pvt Ltd -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; either version 2 of the License, or -# (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -# For use with external or internal boots. -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/include/configs/am3517_crane.h b/include/configs/am3517_crane.h index 8842a18..80c7176 100644 --- a/include/configs/am3517_crane.h +++ b/include/configs/am3517_crane.h @@ -330,4 +330,59 @@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ CONFIG_SYS_INIT_RAM_SIZE - \ GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + +/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + #endif /* __CONFIG_H */
participants (3)
-
Igor Grinberg -
Tom Rini -
Tom Rini