[U-Boot] [PATCH v7 0/7] add support for atheros ath79 based SOCs
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_io...
Changes in v7: - Use setbits_32 - Fix include path for SoC specific headers - Use CKSEGxADDR instead of KSEGxADDR for ar933x - Use CKSEGxADDR instead of KSEGxADDR for qca953x - remove map_physmem for debug port - Define spi_cs_activate/spi_cs_deactivate - Rename MHZ to ATH79_SPI_MHZ - Use clrsetbits_32 - Use KSEG1 address for debug port in ap121 - Use KSEG1 address for debug port in ap143
Changes in v6: - Move ar933x as separate patch - Add get_bootstrap in reset.c - Use map_physmem instead of KSEG1ADDR - Add arch_cpu_init for detect SOC type for early - Remove board.c - Define magic value in ddr.c - Remove wait loop in putc and getc - Use map_physmem instead of KSEG1ADDR - Add rrw_delay in ath79_spi_priv for more accurate timing - Remove ath79_spi_delay - Calculate delay in ath79_spi_set_speed - Convert SZ_XXX into hex in ap121.h - Remove useless CONFIG_SYS_INIT_SP_OFFSET in ap121.h - Add board_early_init_f for DDR and pin initialization - Select UART and SPI in ap121_defconfig
Changes in v5: - Add independent Kconfig - Use SRAM for initial stack - Move DDR initialization into board_early_init_f - Convert DDR tap tunning code to C - Save SOC's version into arch_global_data - remove ar933x_serial_platdata - Import document "qca,ar9330-uart.txt" from kernel - Add support for debug UART - remove ar933x_spi_platdata - Import document "spi-ath79.txt" from kernel - Add delay for bitbang operation - Move CONFIG_SYS_TEXT_BASE into ap121.h, and remove config.mk - Remove useless README file - Remove useless checkboard function
Changes in v4: - Use global_data to save CPU/DDR/AHB clock - Use arch_global_data to save SOC's type, revison and id - Auto calculate baudrate for serial driver - Move pinctrl code in serial driver into arch/mips/mach-ath79 - Use get_serial_clock to serial clock source - Use get_bus_freq instead of hardcode in SPI driver
Changes in v3: - Move SoC specific header files into arch/mips/mach-ath79/include/mach - Optimize assembly code - Same code style convertion - Convert serial driver to driver model - Convert spi driver to driver model - Add support for device tree
Changes in v2: - Move all SoC specific header files into arch/mips/include/asm/arch-ath79 - Check SOC type and extract common code into arch/mips/mach-ath79 - Move serial driver code into drivers/serial - Add a compatible spi driver - Add a reference board implemention
Wills Wang (7): mips: add base support for QCA/Atheros ath79 SOCs mips: ath79: add support for AR933x SOCs mips: ath79: add support for QCA953x SOCs mips: ath79: add serial driver for ar933x SOC mips: ath79: add spi driver mips: ath79: add AP121 reference board mips: ath79: add AP143 reference board
arch/mips/Kconfig | 6 + arch/mips/Makefile | 1 + arch/mips/dts/Makefile | 3 +- arch/mips/dts/ap121.dts | 43 + arch/mips/dts/ap143.dts | 43 + arch/mips/dts/ar933x.dtsi | 70 ++ arch/mips/dts/qca953x.dtsi | 72 ++ arch/mips/include/asm/global_data.h | 6 + arch/mips/mach-ath79/Kconfig | 46 + arch/mips/mach-ath79/Makefile | 10 + arch/mips/mach-ath79/ar933x/Makefile | 7 + arch/mips/mach-ath79/ar933x/clk.c | 89 ++ arch/mips/mach-ath79/ar933x/ddr.c | 316 ++++++ arch/mips/mach-ath79/ar933x/lowlevel_init.S | 279 +++++ arch/mips/mach-ath79/cpu.c | 203 ++++ arch/mips/mach-ath79/dram.c | 16 + arch/mips/mach-ath79/include/mach/ar71xx_regs.h | 1187 ++++++++++++++++++++ arch/mips/mach-ath79/include/mach/ath79.h | 143 +++ arch/mips/mach-ath79/include/mach/ddr.h | 13 + arch/mips/mach-ath79/include/mach/reset.h | 14 + arch/mips/mach-ath79/qca953x/Makefile | 7 + arch/mips/mach-ath79/qca953x/clk.c | 111 ++ arch/mips/mach-ath79/qca953x/ddr.c | 462 ++++++++ arch/mips/mach-ath79/qca953x/lowlevel_init.S | 185 +++ arch/mips/mach-ath79/reset.c | 71 ++ board/ath79/ap121/Kconfig | 9 + board/ath79/ap121/MAINTAINERS | 6 + board/ath79/ap121/Makefile | 5 + board/ath79/ap121/ap121.c | 47 + board/ath79/ap143/Kconfig | 9 + board/ath79/ap143/MAINTAINERS | 6 + board/ath79/ap143/Makefile | 5 + board/ath79/ap143/ap143.c | 63 ++ configs/ap121_defconfig | 42 + configs/ap143_defconfig | 43 + .../serial/qca,ar9330-uart.txt | 24 + doc/device-tree-bindings/spi/spi-ath79.txt | 19 + drivers/serial/Kconfig | 17 + drivers/serial/Makefile | 1 + drivers/serial/serial_ar933x.c | 254 +++++ drivers/spi/Kconfig | 8 + drivers/spi/Makefile | 1 + drivers/spi/ath79_spi.c | 237 ++++ include/configs/ap121.h | 87 ++ include/configs/ap143.h | 91 ++ 45 files changed, 4376 insertions(+), 1 deletion(-) create mode 100644 arch/mips/dts/ap121.dts create mode 100644 arch/mips/dts/ap143.dts create mode 100644 arch/mips/dts/ar933x.dtsi create mode 100644 arch/mips/dts/qca953x.dtsi create mode 100644 arch/mips/mach-ath79/Kconfig create mode 100644 arch/mips/mach-ath79/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/Makefile create mode 100644 arch/mips/mach-ath79/ar933x/clk.c create mode 100644 arch/mips/mach-ath79/ar933x/ddr.c create mode 100644 arch/mips/mach-ath79/ar933x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/cpu.c create mode 100644 arch/mips/mach-ath79/dram.c create mode 100644 arch/mips/mach-ath79/include/mach/ar71xx_regs.h create mode 100644 arch/mips/mach-ath79/include/mach/ath79.h create mode 100644 arch/mips/mach-ath79/include/mach/ddr.h create mode 100644 arch/mips/mach-ath79/include/mach/reset.h create mode 100644 arch/mips/mach-ath79/qca953x/Makefile create mode 100644 arch/mips/mach-ath79/qca953x/clk.c create mode 100644 arch/mips/mach-ath79/qca953x/ddr.c create mode 100644 arch/mips/mach-ath79/qca953x/lowlevel_init.S create mode 100644 arch/mips/mach-ath79/reset.c create mode 100644 board/ath79/ap121/Kconfig create mode 100644 board/ath79/ap121/MAINTAINERS create mode 100644 board/ath79/ap121/Makefile create mode 100644 board/ath79/ap121/ap121.c create mode 100644 board/ath79/ap143/Kconfig create mode 100644 board/ath79/ap143/MAINTAINERS create mode 100644 board/ath79/ap143/Makefile create mode 100644 board/ath79/ap143/ap143.c create mode 100644 configs/ap121_defconfig create mode 100644 configs/ap143_defconfig create mode 100644 doc/device-tree-bindings/serial/qca,ar9330-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-ath79.txt create mode 100644 drivers/serial/serial_ar933x.c create mode 100644 drivers/spi/ath79_spi.c create mode 100644 include/configs/ap121.h create mode 100644 include/configs/ap143.h
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
Best regards, Marek Vasut
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
Best regards, Marek Vasut
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/m ips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
Best regards, Marek Vasut
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/m ips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
My board is also ar9330 rev 1, but i can boot well without any change for start.s and cache, is it possible about hardware? My board work fine when i use DDR or SRAM for stack.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. I doubt whether there are same exceptions for your memory subsystem, or some DDR parameters are not for your DDR chip.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Did your board use DDR1? I check the original u-boot code again, this value 0xa33 is for DDR2, 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
At present, i have no plan to involve ethernet and USB, i want to work done first for this patch.
Best regards, Marek Vasut
On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote:
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: > These series of patch add support for atheros ath79 based SOCs in > u-boot, at the present moment it's just available for ar933x and > qca953x chip. > > This patch serises is based on mips_io_v4 branch on u-boot-mips > repository > [1] and tested on ar933x and qca953x board. > > [1] > > http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads > /m ips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
My board is also ar9330 rev 1, but i can boot well without any change for start.s and cache, is it possible about hardware?
No clue.
My board work fine when i use DDR or SRAM for stack.
I remember you weren't able to boot if you used SRAM for stack. Did something change ?
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. I doubt whether there are same exceptions for your memory subsystem, or some DDR parameters are not for your DDR chip.
DDR is not started at the point where INIT_RAM_LOAD comes into play, so it has nothing to do with it. Instead, refilling the cache from DDR makes no sense if DDR is not running, therefore this should be disabled to make sure we don't run into problems.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Did your board use DDR1?
DDR2
I check the original u-boot code again, this value 0xa33 is for DDR2, 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved.
That's correct, so I suspect there's something swapped somewhere, since my register ends up configured with 0x33 and not 0xa33 . That's why I hacked this change for now.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
At present, i have no plan to involve ethernet and USB, i want to work done first for this patch.
OK, I am looking into the ethernet part now, no luck so far. I cannot even read the PHY ID yet, probably missing some register bit somewhere.
On Thursday, January 21, 2016 01:35 PM, Marek Vasut wrote:
On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote:
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote: > On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: >> These series of patch add support for atheros ath79 based SOCs in >> u-boot, at the present moment it's just available for ar933x and >> qca953x chip. >> >> This patch serises is based on mips_io_v4 branch on u-boot-mips >> repository >> [1] and tested on ar933x and qca953x board. >> >> [1] >> >> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads >> /m ips_ io_v4 > So if I didn't complain about this being sent as separate emails this > morning. > Please, do send your patches as a series, not as separate emails. How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
My board is also ar9330 rev 1, but i can boot well without any change for start.s and cache, is it possible about hardware?
No clue.
My board work fine when i use DDR or SRAM for stack.
I remember you weren't able to boot if you used SRAM for stack. Did something change ?
What i mean is that my board can't boot if drop the whole lowlevel_init.S when use SRAM for stack. we need lowlevel_init.S to handle RTC, PLL and some chip issues.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. I doubt whether there are same exceptions for your memory subsystem, or some DDR parameters are not for your DDR chip.
DDR is not started at the point where INIT_RAM_LOAD comes into play, so it has nothing to do with it. Instead, refilling the cache from DDR makes no sense if DDR is not running, therefore this should be disabled to make sure we don't run into problems.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Did your board use DDR1?
DDR2
I check the original u-boot code again, this value 0xa33 is for DDR2, 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved.
That's correct, so I suspect there's something swapped somewhere, since my register ends up configured with 0x33 and not 0xa33 . That's why I hacked this change for now.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
At present, i have no plan to involve ethernet and USB, i want to work done first for this patch.
OK, I am looking into the ethernet part now, no luck so far. I cannot even read the PHY ID yet, probably missing some register bit somewhere.
On Thursday, January 21, 2016 at 10:31:50 AM, Wills Wang wrote:
On Thursday, January 21, 2016 01:35 PM, Marek Vasut wrote:
On Thursday, January 21, 2016 at 03:58:44 AM, Wills Wang wrote:
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com: > On 01/17/2016 03:05 AM, Marek Vasut wrote: >> On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: >>> These series of patch add support for atheros ath79 based SOCs in >>> u-boot, at the present moment it's just available for ar933x and >>> qca953x chip. >>> >>> This patch serises is based on mips_io_v4 branch on u-boot-mips >>> repository >>> [1] and tested on ar933x and qca953x board. >>> >>> [1] >>> >>> http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/hea >>> ds /m ips_ io_v4 >> >> So if I didn't complain about this being sent as separate emails >> this morning. >> Please, do send your patches as a series, not as separate emails. > > How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
My board is also ar9330 rev 1, but i can boot well without any change for start.s and cache, is it possible about hardware?
No clue.
My board work fine when i use DDR or SRAM for stack.
I remember you weren't able to boot if you used SRAM for stack. Did something change ?
What i mean is that my board can't boot if drop the whole lowlevel_init.S when use SRAM for stack. we need lowlevel_init.S to handle RTC, PLL and some chip issues.
Aha , okay. That's unfortunate indeed.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
My hardware can work no matter if i select SYS_MIPS_CACHE_INIT_RAM_LOAD. I doubt whether there are same exceptions for your memory subsystem, or some DDR parameters are not for your DDR chip.
DDR is not started at the point where INIT_RAM_LOAD comes into play, so it has nothing to do with it. Instead, refilling the cache from DDR makes no sense if DDR is not running, therefore this should be disabled to make sure we don't run into problems.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Did your board use DDR1?
DDR2
I check the original u-boot code again, this value 0xa33 is for DDR2, 0x33 for DDR1. The 0 value for WR filed in DDR2 MRS is reserved.
That's correct, so I suspect there's something swapped somewhere, since my register ends up configured with 0x33 and not 0xa33 . That's why I hacked this change for now.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
At present, i have no plan to involve ethernet and USB, i want to work done first for this patch.
OK, I am looking into the ethernet part now, no luck so far. I cannot even read the PHY ID yet, probably missing some register bit somewhere.
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1]
http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/m ips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
-#define CONFIG_SYS_TEXT_BASE 0x9f000000 +#define CONFIG_SYS_TEXT_BASE 0xbf000000
Why need this change?
Best regards, Marek Vasut
On Thursday, January 21, 2016 at 04:02:05 AM, Wills Wang wrote:
On Thursday, January 21, 2016 09:32 AM, Marek Vasut wrote:
On Sunday, January 17, 2016 at 01:21:29 PM, Wills Wang wrote:
On 01/17/2016 06:24 PM, Daniel Schwierzeck wrote:
2016-01-17 6:49 GMT+01:00 Wills Wang wills.wang@live.com:
On 01/17/2016 03:05 AM, Marek Vasut wrote:
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote: > These series of patch add support for atheros ath79 based SOCs in > u-boot, at the present moment it's just available for ar933x and > qca953x chip. > > This patch serises is based on mips_io_v4 branch on u-boot-mips > repository > [1] and tested on ar933x and qca953x board. > > [1] > > http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads > /m ips_ io_v4
So if I didn't complain about this being sent as separate emails this morning. Please, do send your patches as a series, not as separate emails.
How to send a patch series by patman?
If your git-sendmail config is correctly set up, patman automatically sends the cover letter and then all patches as response to that cover letter.
You have to enable mail threading in git-sendmail. Check that with:
$ git config --get sendemail.thread
To enable it globally:
$ git config --global sendemail.thread true
Thanks, i will try it for the coming v8.
I got as far as booting my ar9330 rev 1 machine, though it did take considerably amount of hackery. I also had to use locked cachelines for stack, because it is far faster than using the SRAM on ar9331 . You can find my hacks in the attachment, most of the stuff there is because arduino yun is repugnant crappy piece of hardware and needs some extra treatment.
You should mostly care about the hacks in start.S , in particular the one setting bit 3 in CP0 in setup_c0_status seems important on mips 24kc core. Daniel seems to have some ideas on this too I think, he helped me finding out there's a problem.
Also, mips_cache_lock_24k does the job for locking the cachelines, but (!) it is clearly a dirty hack. The start.S needs to be modularized in some way for this to be properly integrat(ed|able).
In case I select SYS_MIPS_CACHE_INIT_RAM_LOAD , the machine hangs. No idea why, but I suspect it makes no sense on a machine which has no running DRAM anyway, so I removed this option.
Change to ddr.c seems correct, the values for DDR1 and DDR2 were swapped, but I suggest you double-check it.
Ignore my AHB hack in lowlevel_init.S , it's necessary to keep my SPI NOR running at low speed, since I am using an FPGA instead of real SPI NOR and the FPGA implementation of the SPI NOR emulator cannot run at tens of MHz.
I am now looking into implementing ethernet and USB support for ar9331, did you look into it at all or not ? I'd like to avoid duplicating efforts.
-#define CONFIG_SYS_TEXT_BASE 0x9f000000 +#define CONFIG_SYS_TEXT_BASE 0xbf000000
Why need this change?
I believe this has no impact, it just prevents code from being cachable which is convenient for me. You can ignore it.
On Saturday, January 16, 2016 at 07:13:46 PM, Wills Wang wrote:
These series of patch add support for atheros ath79 based SOCs in u-boot, at the present moment it's just available for ar933x and qca953x chip.
This patch serises is based on mips_io_v4 branch on u-boot-mips repository [1] and tested on ar933x and qca953x board.
[1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=shortlog;h=refs/heads/mips_ io_v4
Brief update, I got EHCI operational on the AR9331.
The controller is almost standard chipidea HDRC, but it is broken in a few nasty ways. I will submit patches later...ish, once I am comfortable with them.
Best regards, Marek Vasut
participants (3)
-
Daniel Schwierzeck -
Marek Vasut -
Wills Wang