[U-Boot] [PATCH 0/2] powerpc/p2041: u-boot.pbl build for P2041RDB
This series enables the build of a u-boot.pbl for the P2041RDB dev board.
Valentin Longchamp (2): powerpc/p2041: add RCW file for P2041RDB powerpc/p2041: set RCW and PBI files for .pbl build or P2041RDB
board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 +++++++++++ include/configs/P2041RDB.h | 2 ++ 2 files changed, 13 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg
All the dev boards of Freescale's QorIQ family have a RCW that is supported by the u-boot.pbl build target. This patch adds one for the P2041 dev board.
This RCW is suitable for the RAMBOOT_PBL scenarios and was tested on the P2041RDB booting from the eSPI NOR Flash (P2041RDB_SPIFLASH config).
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- board/freescale/corenet_ds/rcw_p2041rdb.cfg | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) create mode 100644 board/freescale/corenet_ds/rcw_p2041rdb.cfg
diff --git a/board/freescale/corenet_ds/rcw_p2041rdb.cfg b/board/freescale/corenet_ds/rcw_p2041rdb.cfg new file mode 100644 index 0000000..8df19dd --- /dev/null +++ b/board/freescale/corenet_ds/rcw_p2041rdb.cfg @@ -0,0 +1,11 @@ +# +# Default RCW for P2041RDB. +# + +#PBL preamble and RCW header +aa55aa55 010e0100 +#64 bytes RCW data +12600000 00000000 241C0000 00000000 +649FA0C1 C3C02000 58000000 40000000 +00000000 00000000 00000000 D0030F07 +00000000 00000000 00000000 00000000
In order to be able to build a u-boot.pbl image, both the CONFIG_PBLPBI_CONFIG and CONFIG_PBLRCW_CONFIG variables have to be defined.
This patch sets these two files for the P2041RDB board.
Signed-off-by: Valentin Longchamp valentin.longchamp@keymile.com --- include/configs/P2041RDB.h | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 8b9b0db..bbc53ce 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -34,6 +34,8 @@ #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg +#define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p2041rdb.cfg #endif
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
participants (1)
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Valentin Longchamp