On Fri, Jan 03, 2025 at 04:17:14PM +0100, neil.armstrong@linaro.org wrote:

On 03/01/2025 06:14, Varadarajan Narayanan wrote:

...

Add initial support for the QCS9100 (derived from SA8775p) Ride platforms. Define memory layout statically.

Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com

arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi | 22 ++++++++++++++++++++++ arch/arm/dts/sa8775p-ride-u-boot.dtsi | 11 +++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi create mode 100644 arch/arm/dts/sa8775p-ride-u-boot.dtsi

diff --git a/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi new file mode 100644 index 0000000000..7d01d5f6a1 --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/ {

• model = "Qualcomm QCS9100 Ride Rev3";
• compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";

Why do you redefine those ? they are already defined in the upstream sa8775p-ride-r3.dts

To include QCS9100 info to the model and compatible strings, so that users might not get confused if a wrong U-Boot has booted on the platform.

Please let me know if this should still be removed.

Thanks Varada

...

• /* Will be removed when bootloader updates later */
• memory@80000000 {

• device_type = "memory";
  

• reg = <0x0 0x80000000 0x0 0x3ee00000>,
  

•       <0x0 0xc0000000 0x0 0x04d00000>,
  

•       <0xD 0x00000000 0x2 0x54100000>,
  

•       <0xA 0x80000000 0x1 0x52d00000>,
  

•       <0x9 0x00000000 0x1 0x80000000>,
  

•       <0x1 0x00000000 0x2 0xf7500000>,
  

•       <0x0 0xd0000000 0x0 0x00100000>,
  

•       <0x0 0xd3500000 0x0 0x07c00000>;
  

• };

Ack, this should be removed once the SMEM code is merged.

...

+}; diff --git a/arch/arm/dts/sa8775p-ride-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-u-boot.dtsi new file mode 100644 index 0000000000..979462dfec --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/dts-v1/;

+#include "sa8775p-ride.dts"

Why ? this file will be automatically appended to sa8775p-ride.dts, no need to import is before.

...

+/ {

• model = "Qualcomm QCS9100 Ride";
• compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";

Same, unneeded.

In fact, this file is completely unneeded.

...

+};

Neil

On Tue, Jan 07, 2025 at 12:36:23PM +0100, Caleb Connolly wrote:

On 07/01/2025 10:24, Varadarajan Narayanan wrote:

...

On Fri, Jan 03, 2025 at 04:17:14PM +0100, neil.armstrong@linaro.org wrote:

...

On 03/01/2025 06:14, Varadarajan Narayanan wrote:

...

Add initial support for the QCS9100 (derived from SA8775p) Ride platforms. Define memory layout statically.

Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com

arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi | 22 ++++++++++++++++++++++ arch/arm/dts/sa8775p-ride-u-boot.dtsi | 11 +++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi create mode 100644 arch/arm/dts/sa8775p-ride-u-boot.dtsi

diff --git a/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi new file mode 100644 index 0000000000..7d01d5f6a1 --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/ {

• model = "Qualcomm QCS9100 Ride Rev3";
• compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";

Why do you redefine those ? they are already defined in the upstream sa8775p-ride-r3.dts

To include QCS9100 info to the model and compatible strings, so that users might not get confused if a wrong U-Boot has booted on the platform.

They are already defined in dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts

That file is patched at build time to include this dtsi file at the end.

[1] defines it as "Qualcomm SA8775P Ride Rev3". We want to define as "Qualcomm QCS9100 Ride Rev3", i.e. s/SA8775P/QCS9100/. That is why having it here. This would not be needed once [2] gets into U-Boot.

1. https://source.denx.de/u-boot/u-boot/-/blob/master/dts/upstream/src/arm64/qc... 2. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch...

Thanks Varada

...

Please let me know if this should still be removed.

Thanks Varada

...

...

• /* Will be removed when bootloader updates later */
• memory@80000000 {

• device_type = "memory";
  

• reg = <0x0 0x80000000 0x0 0x3ee00000>,
  

•       <0x0 0xc0000000 0x0 0x04d00000>,
  

•       <0xD 0x00000000 0x2 0x54100000>,
  

•       <0xA 0x80000000 0x1 0x52d00000>,
  

•       <0x9 0x00000000 0x1 0x80000000>,
  

•       <0x1 0x00000000 0x2 0xf7500000>,
  

•       <0x0 0xd0000000 0x0 0x00100000>,
  

•       <0x0 0xd3500000 0x0 0x07c00000>;
  

• };

Ack, this should be removed once the SMEM code is merged.

...

+}; diff --git a/arch/arm/dts/sa8775p-ride-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-u-boot.dtsi new file mode 100644 index 0000000000..979462dfec --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/dts-v1/;

+#include "sa8775p-ride.dts"

Why ? this file will be automatically appended to sa8775p-ride.dts, no need to import is before.

...

+/ {

• model = "Qualcomm QCS9100 Ride";
• compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";

Same, unneeded.

In fact, this file is completely unneeded.

...

+};

Neil

-- // Caleb (they/them)

On Wed, 8 Jan 2025 at 19:36, Caleb Connolly caleb.connolly@linaro.org wrote:

On 08/01/2025 06:46, Varadarajan Narayanan wrote:

...

On Tue, Jan 07, 2025 at 12:36:23PM +0100, Caleb Connolly wrote:

...

On 07/01/2025 10:24, Varadarajan Narayanan wrote:

...

On Fri, Jan 03, 2025 at 04:17:14PM +0100, neil.armstrong@linaro.org wrote:

...

On 03/01/2025 06:14, Varadarajan Narayanan wrote:

...

Add initial support for the QCS9100 (derived from SA8775p) Ride platforms. Define memory layout statically.

Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com

arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi | 22 ++++++++++++++++++++++ arch/arm/dts/sa8775p-ride-u-boot.dtsi | 11 +++++++++++ 2 files changed, 33 insertions(+) create mode 100644 arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi create mode 100644 arch/arm/dts/sa8775p-ride-u-boot.dtsi

diff --git a/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi new file mode 100644 index 0000000000..7d01d5f6a1 --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/ {

• model = "Qualcomm QCS9100 Ride Rev3";
• compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p";

Why do you redefine those ? they are already defined in the upstream sa8775p-ride-r3.dts

To include QCS9100 info to the model and compatible strings, so that users might not get confused if a wrong U-Boot has booted on the platform.

They are already defined in dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts

That file is patched at build time to include this dtsi file at the end.

[1] defines it as "Qualcomm SA8775P Ride Rev3". We want to define as "Qualcomm QCS9100 Ride Rev3", i.e. s/SA8775P/QCS9100/. That is why having it here. This would not be needed once [2] gets into U-Boot.

hmm I see, well that's a pickle. I don't think we have a process yet for handling these cases where we're blocked on a DTS sync.

I would rather avoid creating this weird situation where we use the sa8775p dts and pretend it's a different board especially if it's only temporary until the proper dts lands.

Some proposals:

1. remove the model/compatible properties assuming the sa8775p-ride-r3

board using the same memory map, add another u-boot dtsi for qcs9100-ride-r3 once it's merged in 2. import qcs9100-ride-r3.dts into arch/arm/dts in u-boot as part of this series (but need to remember to remove it later!)

3. somehow cherry-pick the relevant patch into the subtree early

This is the preferred approach, following should create a cherry-pick patch for this platform on top of next branch:

$ ./tools/update-subtree.sh pick dts db6231faa8ef46e5ff5d5ece0c930a07c6358562

Then you should rather include that cherry picked patch in this patch-set instead. The next DT sync will take care of it automatically.

-Sumit

or ask Tom to sync the DT subtree 4. wait for the next sync which hopefully won't be too long(?)

I'd be ok with 1 or maybe 2 for this specific case, I'll see if 3/4 are viable for the future.

Feel free to pick one of those approaches and respin if that works for you.

Kind regards,

...

1. https://source.denx.de/u-boot/u-boot/-/blob/master/dts/upstream/src/arm64/qc...
2. https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch...

Thanks Varada

...

...

Please let me know if this should still be removed.

Thanks Varada

...

...

• /* Will be removed when bootloader updates later */
• memory@80000000 {

•     device_type = "memory";
  

•     reg = <0x0 0x80000000 0x0 0x3ee00000>,
  

•           <0x0 0xc0000000 0x0 0x04d00000>,
  

•           <0xD 0x00000000 0x2 0x54100000>,
  

•           <0xA 0x80000000 0x1 0x52d00000>,
  

•           <0x9 0x00000000 0x1 0x80000000>,
  

•           <0x1 0x00000000 0x2 0xf7500000>,
  

•           <0x0 0xd0000000 0x0 0x00100000>,
  

•           <0x0 0xd3500000 0x0 0x07c00000>;
  

• };

Ack, this should be removed once the SMEM code is merged.

...

+}; diff --git a/arch/arm/dts/sa8775p-ride-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-u-boot.dtsi new file mode 100644 index 0000000000..979462dfec --- /dev/null +++ b/arch/arm/dts/sa8775p-ride-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: BSD-3-Clause +/*

• • Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
• */

+/dts-v1/;

+#include "sa8775p-ride.dts"

Why ? this file will be automatically appended to sa8775p-ride.dts, no need to import is before.

...

+/ {

• model = "Qualcomm QCS9100 Ride";
• compatible = "qcom,qcs9100-ride", "qcom,qcs9100", "qcom,sa8775p";

Same, unneeded.

In fact, this file is completely unneeded.

...

+};

Neil

-- // Caleb (they/them)

-- // Caleb (they/them)

On Wed, Jan 08, 2025 at 03:29:42PM +0100, Caleb Connolly wrote:

On 08/01/2025 15:20, Sumit Garg via groups.io wrote:

...

On Wed, 8 Jan 2025 at 19:36, Caleb Connolly caleb.connolly@linaro.org wrote:

...

On 08/01/2025 06:46, Varadarajan Narayanan wrote:

...

On Tue, Jan 07, 2025 at 12:36:23PM +0100, Caleb Connolly wrote:

...

On 07/01/2025 10:24, Varadarajan Narayanan wrote:

...

On Fri, Jan 03, 2025 at 04:17:14PM +0100, neil.armstrong@linaro.org wrote: > On 03/01/2025 06:14, Varadarajan Narayanan wrote: >> Add initial support for the QCS9100 (derived from SA8775p) Ride platforms. >> Define memory layout statically. >> >> Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com >> --- >> arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi | 22 ++++++++++++++++++++++ >> arch/arm/dts/sa8775p-ride-u-boot.dtsi | 11 +++++++++++ >> 2 files changed, 33 insertions(+) >> create mode 100644 arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi >> create mode 100644 arch/arm/dts/sa8775p-ride-u-boot.dtsi >> >> diff --git a/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi >> new file mode 100644 >> index 0000000000..7d01d5f6a1 >> --- /dev/null >> +++ b/arch/arm/dts/sa8775p-ride-r3-u-boot.dtsi >> @@ -0,0 +1,22 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved. >> + */ >> + >> +/ { >> + model = "Qualcomm QCS9100 Ride Rev3"; >> + compatible = "qcom,qcs9100-ride-r3", "qcom,qcs9100", "qcom,sa8775p"; > > Why do you redefine those ? they are already defined in the upstream sa8775p-ride-r3.dts

To include QCS9100 info to the model and compatible strings, so that users might not get confused if a wrong U-Boot has booted on the platform.

They are already defined in dts/upstream/src/arm64/qcom/sa8775p-ride-r3.dts

That file is patched at build time to include this dtsi file at the end.

[1] defines it as "Qualcomm SA8775P Ride Rev3". We want to define as "Qualcomm QCS9100 Ride Rev3", i.e. s/SA8775P/QCS9100/. That is why having it here. This would not be needed once [2] gets into U-Boot.

hmm I see, well that's a pickle. I don't think we have a process yet for handling these cases where we're blocked on a DTS sync.

I would rather avoid creating this weird situation where we use the sa8775p dts and pretend it's a different board especially if it's only temporary until the proper dts lands.

Some proposals:

1. remove the model/compatible properties assuming the sa8775p-ride-r3

board using the same memory map, add another u-boot dtsi for qcs9100-ride-r3 once it's merged in 2. import qcs9100-ride-r3.dts into arch/arm/dts in u-boot as part of this series (but need to remember to remove it later!)

...

3. somehow cherry-pick the relevant patch into the subtree early

This is the preferred approach, following should create a cherry-pick patch for this platform on top of next branch:

$ ./tools/update-subtree.sh pick dts db6231faa8ef46e5ff5d5ece0c930a07c6358562

Then you should rather include that cherry picked patch in this patch-set instead. The next DT sync will take care of it automatically.

ah that's perfect, thanks Sumit. Then this is the right way to go.

Thanks Caleb and Sumit. Will post a new spin.

-Varada

[ . . . ]

On 03/01/2025 06:14, Varadarajan Narayanan wrote:

Add initial set of clocks and resets for enabling U-Boot on QCS9100 based Ride platforms.

Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com

drivers/clk/qcom/Kconfig | 8 ++ drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clock-sa8775p.c | 142 +++++++++++++++++++++++++++++++ 3 files changed, 151 insertions(+) create mode 100644 drivers/clk/qcom/clock-sa8775p.c

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index d76fca5dba..ad5797ab85 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -103,6 +103,14 @@ config CLK_QCOM_SC7280 on the Snapdragon SC7280 SoC. This driver supports the clocks and resets exposed by the GCC hardware block.

+config CLK_QCOM_SA8775P

•    bool "Qualcomm SA8775 GCC"
  

•    select CLK_QCOM
  

•    help
  

•      Say Y here to enable support for the Global Clock Controller
  

•      on the Snapdragon SA8775 SoC. This driver supports the clocks
  

•      and resets exposed by the GCC hardware block.
  

• endmenu

  endif

diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index ab33f1c5fa..01b541af32 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_CLK_QCOM_SM8150) += clock-sm8150.o obj-$(CONFIG_CLK_QCOM_SM8250) += clock-sm8250.o obj-$(CONFIG_CLK_QCOM_SM8550) += clock-sm8550.o obj-$(CONFIG_CLK_QCOM_SM8650) += clock-sm8650.o +obj-$(CONFIG_CLK_QCOM_SA8775P) += clock-sa8775p.o diff --git a/drivers/clk/qcom/clock-sa8775p.c b/drivers/clk/qcom/clock-sa8775p.c new file mode 100644 index 0000000000..e31f24ed4f --- /dev/null +++ b/drivers/clk/qcom/clock-sa8775p.c @@ -0,0 +1,142 @@ +// SPDX-License-Identifier: GPL-2.0 +/*

• • Clock drivers for Qualcomm sa8775p
• • (C) Copyright 2024 Linaro Ltd.
• */

+#include <linux/types.h> +#include <clk-uclass.h> +#include <dm.h> +#include <linux/delay.h> +#include <asm/io.h> +#include <linux/bug.h> +#include <linux/bitops.h> +#include <dt-bindings/clock/qcom,sa8775p-gcc.h> +#include "clock-qcom.h"

+#define USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR 0xf038 +#define USB30_PRIM_MASTER_CLK_CMD_RCGR 0xf020

+static ulong sa8775p_set_rate(struct clk *clk, ulong rate) +{

• struct msm_clk_priv *priv = dev_get_priv(clk->dev);
• if (clk->id < priv->data->num_clks)

• debug("%s: %s, requested rate=%ld\n", __func__,
  

•       priv->data->clks[clk->id].name, rate);
  

• switch (clk->id) {
• case GCC_USB30_PRIM_MOCK_UTMI_CLK:

• WARN(rate != 19200000, "Unexpected rate for USB30_PRIM_MOCK_UTMI_CLK: %lu\n", rate);
  

• clk_rcg_set_rate(priv->base, USB30_PRIM_MOCK_UTMI_CLK_CMD_RCGR, 0, CFG_CLK_SRC_CXO);
  

• return rate;
  

• case GCC_USB30_PRIM_MASTER_CLK:

• WARN(rate != 200000000, "Unexpected rate for USB30_PRIM_MASTER_CLK: %lu\n", rate);
  

• clk_rcg_set_rate_mnd(priv->base, USB30_PRIM_MASTER_CLK_CMD_RCGR,
  

• 		     1, 0, 0, CFG_CLK_SRC_GPLL0_ODD, 8);
  

• clk_rcg_set_rate(priv->base, 0xf064, 0, 0);
  

• return rate;
  

• default:

• return 0;
  

• }

+}

+static const struct gate_clk sa8775p_clks[] = {

• GATE_CLK(GCC_CFG_NOC_USB3_PRIM_AXI_CLK, 0x1b088, 1),
• GATE_CLK(GCC_USB30_PRIM_MASTER_CLK, 0x1b018, 1),
• GATE_CLK(GCC_AGGRE_USB3_PRIM_AXI_CLK, 0x1b084, 1),
• GATE_CLK(GCC_USB30_PRIM_SLEEP_CLK, 0x1b020, 1),
• GATE_CLK(GCC_USB30_PRIM_MOCK_UTMI_CLK, 0x1b024, 1),
• GATE_CLK(GCC_USB3_PRIM_PHY_AUX_CLK, 0x1b05c, 1),
• GATE_CLK(GCC_USB3_PRIM_PHY_COM_AUX_CLK, 0x1b060, 1),

+};

+static int sa8775p_enable(struct clk *clk) +{

• struct msm_clk_priv *priv = dev_get_priv(clk->dev);
• if (priv->data->num_clks < clk->id) {

• debug("%s: unknown clk id %lu\n", __func__, clk->id);
  

• return 0;
  

• }
• debug("%s: clk %ld: %s\n", __func__, clk->id, sa8775p_clks[clk->id].name);
• switch (clk->id) {
• case GCC_AGGRE_USB3_PRIM_AXI_CLK:

• qcom_gate_clk_en(priv, GCC_USB30_PRIM_MASTER_CLK);
  

• fallthrough;
  

• case GCC_USB30_PRIM_MASTER_CLK:

• qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_AUX_CLK);
  

• qcom_gate_clk_en(priv, GCC_USB3_PRIM_PHY_COM_AUX_CLK);
  

• break;
  

• }
• qcom_gate_clk_en(priv, clk->id);
• return 0;

+}

+static const struct qcom_reset_map sa8775p_gcc_resets[] = {

• [GCC_CAMERA_BCR] = { 0x32000 },
• [GCC_DISPLAY1_BCR] = { 0xC7000 },
• [GCC_DISPLAY_BCR] = { 0x33000 },
• [GCC_EMAC0_BCR] = { 0xB6000 },
• [GCC_EMAC1_BCR] = { 0xB4000 },
• [GCC_GPU_BCR] = { 0x7D000 },
• [GCC_MMSS_BCR] = { 0x17000 },
• [GCC_PCIE_0_BCR] = { 0xa9000 },
• [GCC_PCIE_0_LINK_DOWN_BCR] = { 0xBF000 },
• [GCC_PCIE_0_NOCSR_COM_PHY_BCR] = { 0xBF008 },
• [GCC_PCIE_0_PHY_BCR] = { 0xAD144 },
• [GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR] = { 0xBF00C },
• [GCC_PCIE_1_BCR] = { 0x77000 },
• [GCC_PCIE_1_LINK_DOWN_BCR] = { 0xAE084 },
• [GCC_PCIE_1_NOCSR_COM_PHY_BCR] = { 0xAE090 },
• [GCC_PCIE_1_PHY_BCR] = { 0xAE08C },
• [GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR] = { 0xAE094 },
• [GCC_PDM_BCR] = { 0x3F000 },
• [GCC_QUPV3_WRAPPER_0_BCR] = { 0x23000 },
• [GCC_QUPV3_WRAPPER_1_BCR] = { 0x24000 },
• [GCC_QUPV3_WRAPPER_2_BCR] = { 0x2A000 },
• [GCC_QUPV3_WRAPPER_3_BCR] = { 0xC4000 },
• [GCC_SDCC1_BCR] = { 0x20000 },
• [GCC_TSCSS_BCR] = { 0x21000 },
• [GCC_UFS_CARD_BCR] = { 0x81000 },
• [GCC_UFS_PHY_BCR] = { 0x83000 },

+};

+static const struct qcom_power_map sa8775p_gdscs[] = {

• [UFS_PHY_GDSC] = { 0x83004 },
• [USB30_PRIM_GDSC] = { 0x1B004 },

+};

+static struct msm_clk_data sa8775_gcc_data = {

• .resets = sa8775p_gcc_resets,
• .num_resets = ARRAY_SIZE(sa8775p_gcc_resets),
• .clks = sa8775p_clks,
• .num_clks = ARRAY_SIZE(sa8775p_clks),
• .power_domains = sa8775p_gdscs,
• .num_power_domains = ARRAY_SIZE(sa8775p_gdscs),
• .enable = sa8775p_enable,
• .set_rate = sa8775p_set_rate,

+};

+static const struct udevice_id gcc_sa8775p_of_match[] = {

• {

• .compatible = "qcom,sa8775p-gcc",
  

• .data = (ulong)&sa8775_gcc_data,
  

• },
• { }

+};

+U_BOOT_DRIVER(gcc_sa8775p) = {

• .name = "gcc_sa8775p",
• .id = UCLASS_NOP,
• .of_match = gcc_sa8775p_of_match,
• .bind = qcom_cc_bind,
• .flags = DM_FLAG_PRE_RELOC | DM_FLAG_DEFAULT_PD_CTRL_OFF,

+};

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org

On 03/01/2025 06:14, Varadarajan Narayanan wrote:

Copy PHY tables over from Linux to support SA8775

Signed-off-by: Varadarajan Narayanan quic_varada@quicinc.com

.../phy/qcom/phy-qcom-qmp-qserdes-com-v5.h | 124 ++++++++++ .../phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h | 231 ++++++++++++++++++ drivers/phy/qcom/phy-qcom-qmp-ufs.c | 170 +++++++++++++ 3 files changed, 525 insertions(+) create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h

diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h new file mode 100644 index 0000000000..f264ea3672 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v5.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • • Copyright (c) 2017, The Linux Foundation. All rights reserved.
• • */

+#ifndef QCOM_PHY_QMP_QSERDES_COM_V5_H_ +#define QCOM_PHY_QMP_QSERDES_COM_V5_H_

+/* Only for QMP V5 PHY - QSERDES COM registers */ +#define QSERDES_V5_COM_ATB_SEL1 0x000 +#define QSERDES_V5_COM_ATB_SEL2 0x004 +#define QSERDES_V5_COM_FREQ_UPDATE 0x008 +#define QSERDES_V5_COM_BG_TIMER 0x00c +#define QSERDES_V5_COM_SSC_EN_CENTER 0x010 +#define QSERDES_V5_COM_SSC_ADJ_PER1 0x014 +#define QSERDES_V5_COM_SSC_ADJ_PER2 0x018 +#define QSERDES_V5_COM_SSC_PER1 0x01c +#define QSERDES_V5_COM_SSC_PER2 0x020 +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE0 0x02c +#define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 +#define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 +#define QSERDES_V5_COM_SSC_STEP_SIZE3_MODE1 0x038 +#define QSERDES_V5_COM_POST_DIV 0x03c +#define QSERDES_V5_COM_POST_DIV_MUX 0x040 +#define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 +#define QSERDES_V5_COM_CLK_ENABLE1 0x048 +#define QSERDES_V5_COM_SYS_CLK_CTRL 0x04c +#define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 +#define QSERDES_V5_COM_PLL_EN 0x054 +#define QSERDES_V5_COM_PLL_IVCO 0x058 +#define QSERDES_V5_COM_CMN_IETRIM 0x05c +#define QSERDES_V5_COM_CMN_IPTRIM 0x060 +#define QSERDES_V5_COM_EP_CLOCK_DETECT_CTRL 0x064 +#define QSERDES_V5_COM_SYSCLK_DET_COMP_STATUS 0x068 +#define QSERDES_V5_COM_CLK_EP_DIV_MODE0 0x06c +#define QSERDES_V5_COM_CLK_EP_DIV_MODE1 0x070 +#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 +#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 +#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c +#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 +#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 +#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 +#define QSERDES_V5_COM_PLL_CNTRL 0x08c +#define QSERDES_V5_COM_BIAS_EN_CTRL_BY_PSM 0x090 +#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 +#define QSERDES_V5_COM_CML_SYSCLK_SEL 0x098 +#define QSERDES_V5_COM_RESETSM_CNTRL 0x09c +#define QSERDES_V5_COM_RESETSM_CNTRL2 0x0a0 +#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 +#define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 +#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac +#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 +#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 +#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 +#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc +#define QSERDES_V5_COM_DEC_START_MSB_MODE0 0x0c0 +#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 +#define QSERDES_V5_COM_DEC_START_MSB_MODE1 0x0c8 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 +#define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 +#define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc +#define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 +#define QSERDES_V5_COM_INTEGLOOP_INITVAL 0x0e4 +#define QSERDES_V5_COM_INTEGLOOP_EN 0x0e8 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0 0x0ec +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 +#define QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 +#define QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN0 0x0fc +#define QSERDES_V5_COM_INTEGLOOP_P_PATH_GAIN1 0x100 +#define QSERDES_V5_COM_VCOCAL_DEADMAN_CTRL 0x104 +#define QSERDES_V5_COM_VCO_TUNE_CTRL 0x108 +#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c +#define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 +#define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 +#define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 +#define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c +#define QSERDES_V5_COM_VCO_TUNE_INITVAL1 0x120 +#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL1 0x128 +#define QSERDES_V5_COM_VCO_TUNE_MINVAL2 0x12c +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL1 0x130 +#define QSERDES_V5_COM_VCO_TUNE_MAXVAL2 0x134 +#define QSERDES_V5_COM_VCO_TUNE_TIMER1 0x138 +#define QSERDES_V5_COM_VCO_TUNE_TIMER2 0x13c +#define QSERDES_V5_COM_CMN_STATUS 0x140 +#define QSERDES_V5_COM_RESET_SM_STATUS 0x144 +#define QSERDES_V5_COM_RESTRIM_CODE_STATUS 0x148 +#define QSERDES_V5_COM_PLLCAL_CODE1_STATUS 0x14c +#define QSERDES_V5_COM_PLLCAL_CODE2_STATUS 0x150 +#define QSERDES_V5_COM_CLK_SELECT 0x154 +#define QSERDES_V5_COM_HSCLK_SEL 0x158 +#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c +#define QSERDES_V5_COM_INTEGLOOP_BINCODE_STATUS 0x160 +#define QSERDES_V5_COM_PLL_ANALOG 0x164 +#define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 +#define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c +#define QSERDES_V5_COM_SW_RESET 0x170 +#define QSERDES_V5_COM_CORE_CLK_EN 0x174 +#define QSERDES_V5_COM_C_READY_STATUS 0x178 +#define QSERDES_V5_COM_CMN_CONFIG 0x17c +#define QSERDES_V5_COM_CMN_RATE_OVERRIDE 0x180 +#define QSERDES_V5_COM_SVS_MODE_CLK_SEL 0x184 +#define QSERDES_V5_COM_DEBUG_BUS0 0x188 +#define QSERDES_V5_COM_DEBUG_BUS1 0x18c +#define QSERDES_V5_COM_DEBUG_BUS2 0x190 +#define QSERDES_V5_COM_DEBUG_BUS3 0x194 +#define QSERDES_V5_COM_DEBUG_BUS_SEL 0x198 +#define QSERDES_V5_COM_CMN_MISC1 0x19c +#define QSERDES_V5_COM_CMN_MODE 0x1a0 +#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 +#define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 +#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 +#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc +#define QSERDES_V5_COM_RESERVED_1 0x1c0

+#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h new file mode 100644 index 0000000000..c16b010c45 --- /dev/null +++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v5.h @@ -0,0 +1,231 @@

+/* SPDX-License-Identifier: GPL-2.0 */ +/*

• • • Copyright (c) 2017, The Linux Foundation. All rights reserved.
• • */

+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ +#define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_

+/* Only for QMP V5 PHY - TX registers */ +#define QSERDES_V5_TX_BIST_MODE_LANENO 0x000 +#define QSERDES_V5_TX_BIST_INVERT 0x004 +#define QSERDES_V5_TX_CLKBUF_ENABLE 0x008 +#define QSERDES_V5_TX_TX_EMP_POST1_LVL 0x00c +#define QSERDES_V5_TX_TX_IDLE_LVL_LARGE_AMP 0x010 +#define QSERDES_V5_TX_TX_DRV_LVL 0x014 +#define QSERDES_V5_TX_TX_DRV_LVL_OFFSET 0x018 +#define QSERDES_V5_TX_RESET_TSYNC_EN 0x01c +#define QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN 0x020 +#define QSERDES_V5_TX_TX_BAND 0x024 +#define QSERDES_V5_TX_SLEW_CNTL 0x028 +#define QSERDES_V5_TX_INTERFACE_SELECT 0x02c +#define QSERDES_V5_TX_LPB_EN 0x030 +#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 +#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c +#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 +#define QSERDES_V5_TX_PERL_LENGTH1 0x044 +#define QSERDES_V5_TX_PERL_LENGTH2 0x048 +#define QSERDES_V5_TX_SERDES_BYP_EN_OUT 0x04c +#define QSERDES_V5_TX_DEBUG_BUS_SEL 0x050 +#define QSERDES_V5_TX_TRANSCEIVER_BIAS_EN 0x054 +#define QSERDES_V5_TX_HIGHZ_DRVR_EN 0x058 +#define QSERDES_V5_TX_TX_POL_INV 0x05c +#define QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN 0x060 +#define QSERDES_V5_TX_BIST_PATTERN1 0x064 +#define QSERDES_V5_TX_BIST_PATTERN2 0x068 +#define QSERDES_V5_TX_BIST_PATTERN3 0x06c +#define QSERDES_V5_TX_BIST_PATTERN4 0x070 +#define QSERDES_V5_TX_BIST_PATTERN5 0x074 +#define QSERDES_V5_TX_BIST_PATTERN6 0x078 +#define QSERDES_V5_TX_BIST_PATTERN7 0x07c +#define QSERDES_V5_TX_BIST_PATTERN8 0x080 +#define QSERDES_V5_TX_LANE_MODE_1 0x084 +#define QSERDES_V5_TX_LANE_MODE_2 0x088 +#define QSERDES_V5_TX_LANE_MODE_3 0x08c +#define QSERDES_V5_TX_LANE_MODE_4 0x090 +#define QSERDES_V5_TX_LANE_MODE_5 0x094 +#define QSERDES_V5_TX_ATB_SEL1 0x098 +#define QSERDES_V5_TX_ATB_SEL2 0x09c +#define QSERDES_V5_TX_RCV_DETECT_LVL 0x0a0 +#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 +#define QSERDES_V5_TX_PRBS_SEED1 0x0a8 +#define QSERDES_V5_TX_PRBS_SEED2 0x0ac +#define QSERDES_V5_TX_PRBS_SEED3 0x0b0 +#define QSERDES_V5_TX_PRBS_SEED4 0x0b4 +#define QSERDES_V5_TX_RESET_GEN 0x0b8 +#define QSERDES_V5_TX_RESET_GEN_MUXES 0x0bc +#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 +#define QSERDES_V5_TX_TX_INTERFACE_MODE 0x0c4 +#define QSERDES_V5_TX_VMODE_CTRL1 0x0c8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_CTRL_1 0x0cc +#define QSERDES_V5_TX_BIST_STATUS 0x0d0 +#define QSERDES_V5_TX_BIST_ERROR_COUNT1 0x0d4 +#define QSERDES_V5_TX_BIST_ERROR_COUNT2 0x0d8 +#define QSERDES_V5_TX_ALOG_OBSV_BUS_STATUS_1 0x0dc +#define QSERDES_V5_TX_LANE_DIG_CONFIG 0x0e0 +#define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 +#define QSERDES_V5_TX_PRE_EMPH 0x0e8 +#define QSERDES_V5_TX_SW_RESET 0x0ec +#define QSERDES_V5_TX_DCC_OFFSET 0x0f0 +#define QSERDES_V5_TX_DCC_CMUX_POSTCAL_OFFSET 0x0f4 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL1 0x0f8 +#define QSERDES_V5_TX_DCC_CMUX_CAL_CTRL2 0x0fc +#define QSERDES_V5_TX_DIG_BKUP_CTRL 0x100 +#define QSERDES_V5_TX_DEBUG_BUS0 0x104 +#define QSERDES_V5_TX_DEBUG_BUS1 0x108 +#define QSERDES_V5_TX_DEBUG_BUS2 0x10c +#define QSERDES_V5_TX_DEBUG_BUS3 0x110 +#define QSERDES_V5_TX_READ_EQCODE 0x114 +#define QSERDES_V5_TX_READ_OFFSETCODE 0x118 +#define QSERDES_V5_TX_IA_ERROR_COUNTER_LOW 0x11c +#define QSERDES_V5_TX_IA_ERROR_COUNTER_HIGH 0x120 +#define QSERDES_V5_TX_VGA_READ_CODE 0x124 +#define QSERDES_V5_TX_VTH_READ_CODE 0x128 +#define QSERDES_V5_TX_DFE_TAP1_READ_CODE 0x12c +#define QSERDES_V5_TX_DFE_TAP2_READ_CODE 0x130 +#define QSERDES_V5_TX_IDAC_STATUS_I 0x134 +#define QSERDES_V5_TX_IDAC_STATUS_IBAR 0x138 +#define QSERDES_V5_TX_IDAC_STATUS_Q 0x13c +#define QSERDES_V5_TX_IDAC_STATUS_QBAR 0x140 +#define QSERDES_V5_TX_IDAC_STATUS_A 0x144 +#define QSERDES_V5_TX_IDAC_STATUS_ABAR 0x148 +#define QSERDES_V5_TX_IDAC_STATUS_SM_ON 0x14c +#define QSERDES_V5_TX_IDAC_STATUS_CAL_DONE 0x150 +#define QSERDES_V5_TX_IDAC_STATUS_SIGNERROR 0x154 +#define QSERDES_V5_TX_DCC_CAL_STATUS 0x158 +#define QSERDES_V5_TX_DCC_READ_CODE_STATUS 0x15c

+/* Only for QMP V5 PHY - RX registers */ +#define QSERDES_V5_RX_UCDR_FO_GAIN_HALF 0x000 +#define QSERDES_V5_RX_UCDR_FO_GAIN_QUARTER 0x004 +#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 +#define QSERDES_V5_RX_UCDR_SO_GAIN_HALF 0x00c +#define QSERDES_V5_RX_UCDR_SO_GAIN_QUARTER 0x010 +#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_HALF 0x018 +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN_QUARTER 0x01c +#define QSERDES_V5_RX_UCDR_SVS_FO_GAIN 0x020 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_HALF 0x024 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 +#define QSERDES_V5_RX_UCDR_SVS_SO_GAIN 0x02c +#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 +#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 +#define QSERDES_V5_RX_UCDR_FO_TO_SO_DELAY 0x038 +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c +#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 +#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 +#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 +#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c +#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 +#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 +#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 +#define QSERDES_V5_RX_AUX_CONTROL 0x05c +#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 +#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 +#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 +#define QSERDES_V5_RX_AC_JTAG_INITP 0x06c +#define QSERDES_V5_RX_AC_JTAG_INITN 0x070 +#define QSERDES_V5_RX_AC_JTAG_LVL 0x074 +#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 +#define QSERDES_V5_RX_AC_JTAG_RESET 0x07c +#define QSERDES_V5_RX_RX_TERM_BW 0x080 +#define QSERDES_V5_RX_RX_RCVR_IQ_EN 0x084 +#define QSERDES_V5_RX_RX_IDAC_I_DC_OFFSETS 0x088 +#define QSERDES_V5_RX_RX_IDAC_IBAR_DC_OFFSETS 0x08c +#define QSERDES_V5_RX_RX_IDAC_Q_DC_OFFSETS 0x090 +#define QSERDES_V5_RX_RX_IDAC_QBAR_DC_OFFSETS 0x094 +#define QSERDES_V5_RX_RX_IDAC_A_DC_OFFSETS 0x098 +#define QSERDES_V5_RX_RX_IDAC_ABAR_DC_OFFSETS 0x09c +#define QSERDES_V5_RX_RX_IDAC_EN 0x0a0 +#define QSERDES_V5_RX_RX_IDAC_ENABLES 0x0a4 +#define QSERDES_V5_RX_RX_IDAC_SIGN 0x0a8 +#define QSERDES_V5_RX_RX_HIGHZ_HIGHRATE 0x0ac +#define QSERDES_V5_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0 +#define QSERDES_V5_RX_DFE_1 0x0b4 +#define QSERDES_V5_RX_DFE_2 0x0b8 +#define QSERDES_V5_RX_DFE_3 0x0bc +#define QSERDES_V5_RX_DFE_4 0x0c0 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH1 0x0c4 +#define QSERDES_V5_RX_TX_ADAPT_PRE_THRESH2 0x0c8 +#define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc +#define QSERDES_V5_RX_TX_ADAPT_MAIN_THRESH 0x0d0 +#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 +#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 +#define QSERDES_V5_RX_GM_CAL 0x0dc +#define QSERDES_V5_RX_RX_VGA_GAIN2_LSB 0x0e0 +#define QSERDES_V5_RX_RX_VGA_GAIN2_MSB 0x0e4 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 +#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 +#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc +#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 +#define QSERDES_V5_RX_RX_IDAC_ACCUMULATOR 0x104 +#define QSERDES_V5_RX_RX_EQ_OFFSET_LSB 0x108 +#define QSERDES_V5_RX_RX_EQ_OFFSET_MSB 0x10c +#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 +#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 +#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 +#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c +#define QSERDES_V5_RX_SIGDET_LVL 0x120 +#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 +#define QSERDES_V5_RX_RX_BAND 0x128 +#define QSERDES_V5_RX_CDR_FREEZE_UP_DN 0x12c +#define QSERDES_V5_RX_CDR_RESET_OVERRIDE 0x130 +#define QSERDES_V5_RX_RX_INTERFACE_MODE 0x134 +#define QSERDES_V5_RX_JITTER_GEN_MODE 0x138 +#define QSERDES_V5_RX_SJ_AMP1 0x13c +#define QSERDES_V5_RX_SJ_AMP2 0x140 +#define QSERDES_V5_RX_SJ_PER1 0x144 +#define QSERDES_V5_RX_SJ_PER2 0x148 +#define QSERDES_V5_RX_PPM_OFFSET1 0x14c +#define QSERDES_V5_RX_PPM_OFFSET2 0x150 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD1 0x154 +#define QSERDES_V5_RX_SIGN_PPM_PERIOD2 0x158 +#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c +#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 +#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 +#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 +#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c +#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 +#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 +#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 +#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c +#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 +#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 +#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 +#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c +#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 +#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 +#define QSERDES_V5_RX_PHPRE_CTRL 0x198 +#define QSERDES_V5_RX_PHPRE_INITVAL 0x19c +#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 +#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 +#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 +#define QSERDES_V5_RX_DCC_CTRL2 0x1ac +#define QSERDES_V5_RX_VTH_CODE 0x1b0 +#define QSERDES_V5_RX_VTH_MIN_THRESH 0x1b4 +#define QSERDES_V5_RX_VTH_MAX_THRESH 0x1b8 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_CTRL_1 0x1bc +#define QSERDES_V5_RX_PI_CTRL1 0x1c0 +#define QSERDES_V5_RX_PI_CTRL2 0x1c4 +#define QSERDES_V5_RX_PI_QUAD 0x1c8 +#define QSERDES_V5_RX_IDATA1 0x1cc +#define QSERDES_V5_RX_IDATA2 0x1d0 +#define QSERDES_V5_RX_AUX_DATA1 0x1d4 +#define QSERDES_V5_RX_AUX_DATA2 0x1d8 +#define QSERDES_V5_RX_AC_JTAG_OUTP 0x1dc +#define QSERDES_V5_RX_AC_JTAG_OUTN 0x1e0 +#define QSERDES_V5_RX_RX_SIGDET 0x1e4 +#define QSERDES_V5_RX_ALOG_OBSV_BUS_STATUS_1 0x1e8

+/* Only for QMP V5 UFS ? */ +#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 +#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c +#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 +#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184

+#endif diff --git a/drivers/phy/qcom/phy-qcom-qmp-ufs.c b/drivers/phy/qcom/phy-qcom-qmp-ufs.c index 5c90d60e7d..7eba50f2d7 100644 --- a/drivers/phy/qcom/phy-qcom-qmp-ufs.c +++ b/drivers/phy/qcom/phy-qcom-qmp-ufs.c @@ -33,8 +33,10 @@ #include "phy-qcom-qmp-pcs-ufs-v6.h"

#include "phy-qcom-qmp-qserdes-com-v4.h" +#include "phy-qcom-qmp-qserdes-com-v5.h" #include "phy-qcom-qmp-qserdes-com-v6.h" #include "phy-qcom-qmp-qserdes-txrx-v4.h" +#include "phy-qcom-qmp-qserdes-txrx-v5.h" #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"

/* QPHY_SW_RESET bit */ @@ -97,6 +99,13 @@ static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, };

+static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {

• [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START,
• [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS,
• [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET,
• [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,

+};

• static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS,

@@ -457,6 +466,127 @@ static const struct qmp_ufs_init_tbl sm8650_ufsphy_rx[] = { QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), }; +static const struct qmp_ufs_init_tbl sm8350_ufsphy_serdes[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd),
• QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_hs_b_serdes[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_tx[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
• QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_rx[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_pcs[] = {

• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e),
• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_tx[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_rx[] = {

• QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed),
• QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c),

+};

+static const struct qmp_ufs_init_tbl sm8350_ufsphy_g4_pcs[] = {

• QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a),

+};

static const struct qmp_ufs_init_tbl sm8650_ufsphy_pcs[] = { QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), @@ -690,6 +820,11 @@ static const char * const sdm845_ufs_phy_clk_l[] = { "ref", "ref_aux", };

+/* the primary usb3 phy on sm8250 doesn't have a ref clock */ +static const char * const sm8450_ufs_phy_clk_l[] = {

• "qref", "ref", "ref_aux",

+};

• /* list of regulators */ static const char * const qmp_ufs_vreg_l[] = { "vdda-phy", "vdda-pll",

@@ -909,6 +1044,40 @@ static const struct qmp_ufs_cfg sc7280_ufsphy_cfg = { .regs = ufsphy_v4_regs_layout, };

+static const struct qmp_ufs_cfg sa8775p_ufsphy_cfg = {

• .lanes = 2,
• .offsets = &qmp_ufs_offsets,
• .tbls = {

• .serdes		= sm8350_ufsphy_serdes,
  

• .serdes_num	= ARRAY_SIZE(sm8350_ufsphy_serdes),
  

• .tx		= sm8350_ufsphy_tx,
  

• .tx_num		= ARRAY_SIZE(sm8350_ufsphy_tx),
  

• .rx		= sm8350_ufsphy_rx,
  

• .rx_num		= ARRAY_SIZE(sm8350_ufsphy_rx),
  

• .pcs		= sm8350_ufsphy_pcs,
  

• .pcs_num	= ARRAY_SIZE(sm8350_ufsphy_pcs),
  

• },
• .tbls_hs_b = {

• .serdes		= sm8350_ufsphy_hs_b_serdes,
  

• .serdes_num	= ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes),
  

• },
• .tbls_hs_g4 = {

• .tx		= sm8350_ufsphy_g4_tx,
  

• .tx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_tx),
  

• .rx		= sm8350_ufsphy_g4_rx,
  

• .rx_num		= ARRAY_SIZE(sm8350_ufsphy_g4_rx),
  

• .pcs		= sm8350_ufsphy_g4_pcs,
  

• .pcs_num	= ARRAY_SIZE(sm8350_ufsphy_g4_pcs),
  

• },
• .clk_list = sm8450_ufs_phy_clk_l,
• .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
• .vreg_list = qmp_ufs_vreg_l,
• .num_vregs = ARRAY_SIZE(qmp_ufs_vreg_l),
• .regs = ufsphy_v5_regs_layout,

+};

• static void qmp_ufs_configure_lane(void __iomem *base, const struct qmp_ufs_init_tbl tbl[], int num,

@@ -1295,6 +1464,7 @@ static struct phy_ops qmp_ufs_ops = { };

static const struct udevice_id qmp_ufs_ids[] = {

• { .compatible = "qcom,sa8775p-qmp-ufs-phy", .data = (ulong)&sa8775p_ufsphy_cfg, }, { .compatible = "qcom,sdm845-qmp-ufs-phy", .data = (ulong)&sdm845_ufsphy_cfg }, { .compatible = "qcom,sm8150-qmp-ufs-phy", .data = (ulong)&sm8150_ufsphy_cfg }, { .compatible = "qcom,sm8250-qmp-ufs-phy", .data = (ulong)&sm8250_ufsphy_cfg },

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org