[U-Boot] [PATCH v4 0/4] x86: Support pci based uart as the U-Boot serial console

This series add support to the ns16550 compatible pci devices.
Newer x86 Platform Controller Hub chipset (like Topcliff, BayTrail) starts to integrate ns16550 compatible pci uart devices. In order to use them, we have to scan the pci bus and allocate memory/io address in the early phase. A gd->hose is added to save the pci bus controller hose in the early phase so that pci apis can be used.
On Intel Crown Bay board, there are 4 DB9 connectors, one of which is from the superio legacy serial port and the other 3 are connected to the Topcliff PCH UART devices. In order to use them as the U-Boot serial console, we need describe those devices in the board's dts file per Open Firmware PCI bus bindings and specify it as the console via the 'stdout-path' in the chosen node. Several APIs are added in fdtdec.c to provide help for decoding the pci device nodes.
Changes in v4: - Check compatible string 12th byte against '\0' - Add , after pciclass in the pci compatible string per spec - Drop the first 3 patches which are already applied
Changes in v3: - Fixed a typo: parant -> parent - Return better error code in fdtdec_get_pci_addr() - Add some debug output in fdtdec_get_pci_addr() - Reuse variable 'len' instead of creating a new one 'l' - Check compatible string length and existence of '.' - Using simple_strtol() directly on the compatible sub-string - Change variable 'bn' to 'barnum' which is self-documenting - Update to use 'memory-mapped' and 'i/o-mapped' in several places - Use 'Processor Local Bus' instead of 'plb' - Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto
Changes in v2: - New patch to add several apis to decode pci device node - New patch to support ns16550 compatible pci uart devices - New patch to use ePAPR defined properties for x86-uart - New patch to add pci devices in crownbay.dts - Drop v1 patch: Add an API for finding pci devices in the early phase - Drop v1 patch: Support PCI UART in the x86_serial driver - Drop v1 patch: Add PCI UART related defines in crownbay.h
Bin Meng (4): fdt: Add several apis to decode pci device node serial: ns16550: Support ns16550 compatible pci uart devices x86: Use ePAPR defined properties for x86-uart x86: crownbay: Add pci devices in the dts file
arch/x86/dts/crownbay.dts | 81 +++++++++++++++++++++ arch/x86/dts/serial.dtsi | 5 +- drivers/serial/ns16550.c | 31 ++++++++ drivers/serial/serial_x86.c | 8 ++- include/fdtdec.h | 108 +++++++++++++++++++++++++--- lib/fdtdec.c | 171 ++++++++++++++++++++++++++++++++++++++++---- 6 files changed, 375 insertions(+), 29 deletions(-)

This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including: - fdtdec_get_pci_addr() for encoded pci address - fdtdec_get_pci_vendev() for vendor id and device id - fdtdec_get_pci_bdf() for pci device bdf triplet - fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v4: - Check compatible string 12th byte against '\0'
Changes in v3: - Fixed a typo: parant -> parent - Return better error code in fdtdec_get_pci_addr() - Add some debug output in fdtdec_get_pci_addr() - Reuse variable 'len' instead of creating a new one 'l' - Check compatible string length and existence of '.' - Using simple_strtol() directly on the compatible sub-string - Change variable 'bn' to 'barnum' which is self-documenting
Changes in v2: - New patch to add several apis to decode pci device node
include/fdtdec.h | 108 +++++++++++++++++++++++++++++++---- lib/fdtdec.c | 171 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 254 insertions(+), 25 deletions(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h index d2b665c..2b2652f 100644 --- a/include/fdtdec.h +++ b/include/fdtdec.h @@ -50,6 +50,49 @@ struct fdt_resource { fdt_addr_t end; };
+enum fdt_pci_space { + FDT_PCI_SPACE_CONFIG = 0, + FDT_PCI_SPACE_IO = 0x01000000, + FDT_PCI_SPACE_MEM32 = 0x02000000, + FDT_PCI_SPACE_MEM64 = 0x03000000, + FDT_PCI_SPACE_MEM32_PREF = 0x42000000, + FDT_PCI_SPACE_MEM64_PREF = 0x43000000, +}; + +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_SIZE_CELLS 2 +#define FDT_PCI_REG_SIZE \ + ((FDT_PCI_ADDR_CELLS + FDT_PCI_SIZE_CELLS) * sizeof(u32)) + +/* + * The Open Firmware spec defines PCI physical address as follows: + * + * bits# 31 .... 24 23 .... 16 15 .... 08 07 .... 00 + * + * phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr + * phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh + * phys.lo cell: llllllll llllllll llllllll llllllll + * + * where: + * + * n: is 0 if the address is relocatable, 1 otherwise + * p: is 1 if addressable region is prefetchable, 0 otherwise + * t: is 1 if the address is aliased (for non-relocatable I/O) below 1MB + * (for Memory), or below 64KB (for relocatable I/O) + * ss: is the space code, denoting the address space + * bbbbbbbb: is the 8-bit Bus Number + * ddddd: is the 5-bit Device Number + * fff: is the 3-bit Function Number + * rrrrrrrr: is the 8-bit Register Number + * hhhhhhhh: is a 32-bit unsigned number + * llllllll: is a 32-bit unsigned number + */ +struct fdt_pci_addr { + u32 phys_hi; + u32 phys_mid; + u32 phys_lo; +}; + /** * Compute the size of a resource. * @@ -252,6 +295,60 @@ fdt_addr_t fdtdec_get_addr_size(const void *blob, int node, const char *prop_name, fdt_size_t *sizep);
/** + * Look at an address property in a node and return the pci address which + * corresponds to the given type in the form of fdt_pci_addr. + * The property must hold one fdt_pci_addr with a lengh. + * + * @param blob FDT blob + * @param node node to examine + * @param type pci address type (FDT_PCI_SPACE_xxx) + * @param prop_name name of property to find + * @param addr returns pci address in the form of fdt_pci_addr + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, + const char *prop_name, struct fdt_pci_addr *addr); + +/** + * Look at the compatible property of a device node that represents a PCI + * device and extract pci vendor id and device id from it. + * + * @param blob FDT blob + * @param node node to examine + * @param vendor vendor id of the pci device + * @param device device id of the pci device + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_vendev(const void *blob, int node, + u16 *vendor, u16 *device); + +/** + * Look at the pci address of a device node that represents a PCI device + * and parse the bus, device and function number from it. + * + * @param blob FDT blob + * @param node node to examine + * @param addr pci address in the form of fdt_pci_addr + * @param bdf returns bus, device, function triplet + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_bdf(const void *blob, int node, + struct fdt_pci_addr *addr, pci_dev_t *bdf); + +/** + * Look at the pci address of a device node that represents a PCI device + * and return base address of the pci device's registers. + * + * @param blob FDT blob + * @param node node to examine + * @param addr pci address in the form of fdt_pci_addr + * @param bar returns base address of the pci device's registers + * @return 0 if ok, negative on error + */ +int fdtdec_get_pci_bar32(const void *blob, int node, + struct fdt_pci_addr *addr, u32 *bar); + +/** * Look up a 32-bit integer property in a node and return it. The property * must have at least 4 bytes of data. The value of the first cell is * returned. @@ -677,17 +774,6 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property, struct fdt_resource *res);
/** - * Look at the reg property of a device node that represents a PCI device - * and parse the bus, device and function number from it. - * - * @param fdt FDT blob - * @param node node to examine - * @param bdf returns bus, device, function triplet - * @return 0 if ok, negative on error - */ -int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf); - -/** * Decode a named region within a memory bank of a given type. * * This function handles selection of a memory region. The region is diff --git a/lib/fdtdec.c b/lib/fdtdec.c index 9d86dba..ddfceca 100644 --- a/lib/fdtdec.c +++ b/lib/fdtdec.c @@ -121,6 +121,163 @@ fdt_addr_t fdtdec_get_addr(const void *blob, int node, return fdtdec_get_addr_size(blob, node, prop_name, NULL); }
+#ifdef CONFIG_PCI +int fdtdec_get_pci_addr(const void *blob, int node, enum fdt_pci_space type, + const char *prop_name, struct fdt_pci_addr *addr) +{ + const u32 *cell; + int len; + int ret = -ENOENT; + + debug("%s: %s: ", __func__, prop_name); + + /* + * If we follow the pci bus bindings strictly, we should check + * the value of the node's parent node's #address-cells and + * #size-cells. They need to be 3 and 2 accordingly. However, + * for simplicity we skip the check here. + */ + cell = fdt_getprop(blob, node, prop_name, &len); + if (!cell) + goto fail; + + if ((len % FDT_PCI_REG_SIZE) == 0) { + int num = len / FDT_PCI_REG_SIZE; + int i; + + for (i = 0; i < num; i++) { + debug("pci address #%d: %08lx %08lx %08lx\n", i, + (ulong)fdt_addr_to_cpu(cell[0]), + (ulong)fdt_addr_to_cpu(cell[1]), + (ulong)fdt_addr_to_cpu(cell[2])); + if ((fdt_addr_to_cpu(*cell) & type) == type) { + addr->phys_hi = fdt_addr_to_cpu(cell[0]); + addr->phys_mid = fdt_addr_to_cpu(cell[1]); + addr->phys_lo = fdt_addr_to_cpu(cell[2]); + break; + } else { + cell += (FDT_PCI_ADDR_CELLS + + FDT_PCI_SIZE_CELLS); + } + } + + if (i == num) + goto fail; + + return 0; + } else { + ret = -EINVAL; + } + +fail: + debug("(not found)\n"); + return ret; +} + +int fdtdec_get_pci_vendev(const void *blob, int node, u16 *vendor, u16 *device) +{ + const char *list, *end; + int len; + + list = fdt_getprop(blob, node, "compatible", &len); + if (!list) + return -ENOENT; + + end = list + len; + while (list < end) { + char *s; + + len = strlen(list); + if (len >= strlen("pciVVVV,DDDD")) { + s = strstr(list, "pci"); + + /* + * check if the string is something like pciVVVV,DDDD.RR + * or just pciVVVV,DDDD + */ + if (s && s[7] == ',' && + (s[12] == '.' || s[12] == 0)) { + s += 3; + *vendor = simple_strtol(s, NULL, 16); + + s += 5; + *device = simple_strtol(s, NULL, 16); + + return 0; + } + } else { + list += (len + 1); + } + } + + return -ENOENT; +} + +int fdtdec_get_pci_bdf(const void *blob, int node, + struct fdt_pci_addr *addr, pci_dev_t *bdf) +{ + u16 dt_vendor, dt_device, vendor, device; + int ret; + + /* get vendor id & device id from the compatible string */ + ret = fdtdec_get_pci_vendev(blob, node, &dt_vendor, &dt_device); + if (ret) + return ret; + + /* extract the bdf from fdt_pci_addr */ + *bdf = addr->phys_hi & 0xffff00; + + /* read vendor id & device id based on bdf */ + pci_read_config_word(*bdf, PCI_VENDOR_ID, &vendor); + pci_read_config_word(*bdf, PCI_DEVICE_ID, &device); + + /* + * Note there are two places in the device tree to fully describe + * a pci device: one is via compatible string with a format of + * "pciVVVV,DDDD" and the other one is the bdf numbers encoded in + * the device node's reg address property. We read the vendor id + * and device id based on bdf and compare the values with the + * "VVVV,DDDD". If they are the same, then we are good to use bdf + * to read device's bar. But if they are different, we have to rely + * on the vendor id and device id extracted from the compatible + * string and locate the real bdf by pci_find_device(). This is + * because normally we may only know device's device number and + * function number when writing device tree. The bus number is + * dynamically assigned during the pci enumeration process. + */ + if ((dt_vendor != vendor) || (dt_device != device)) { + *bdf = pci_find_device(dt_vendor, dt_device, 0); + if (*bdf == -1) + return -ENODEV; + } + + return 0; +} + +int fdtdec_get_pci_bar32(const void *blob, int node, + struct fdt_pci_addr *addr, u32 *bar) +{ + pci_dev_t bdf; + int barnum; + int ret; + + /* get pci devices's bdf */ + ret = fdtdec_get_pci_bdf(blob, node, addr, &bdf); + if (ret) + return ret; + + /* extract the bar number from fdt_pci_addr */ + barnum = addr->phys_hi & 0xff; + if ((barnum < PCI_BASE_ADDRESS_0) || (barnum > PCI_CARDBUS_CIS)) + return -EINVAL; + + barnum = (barnum - PCI_BASE_ADDRESS_0) / 4; + *bar = pci_read_bar32(pci_bus_to_hose(PCI_BUS(bdf)), bdf, barnum); + + return 0; +} +#endif + uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name, uint64_t default_val) { @@ -790,20 +947,6 @@ int fdt_get_named_resource(const void *fdt, int node, const char *property, return fdt_get_resource(fdt, node, property, index, res); }
-int fdtdec_pci_get_bdf(const void *fdt, int node, int *bdf) -{ - const fdt32_t *prop; - int len; - - prop = fdt_getprop(fdt, node, "reg", &len); - if (!prop) - return len; - - *bdf = fdt32_to_cpu(*prop) & 0xffffff; - - return 0; -} - int fdtdec_decode_memory_region(const void *blob, int config_node, const char *mem_type, const char *suffix, fdt_addr_t *basep, fdt_size_t *sizep)

On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v4:
- Check compatible string 12th byte against '\0'
Acked-by: Simon Glass sjg@chromium.org
Changes in v3:
- Fixed a typo: parant -> parent
- Return better error code in fdtdec_get_pci_addr()
- Add some debug output in fdtdec_get_pci_addr()
- Reuse variable 'len' instead of creating a new one 'l'
- Check compatible string length and existence of '.'
- Using simple_strtol() directly on the compatible sub-string
- Change variable 'bn' to 'barnum' which is self-documenting
Changes in v2:
- New patch to add several apis to decode pci device node
include/fdtdec.h | 108 +++++++++++++++++++++++++++++++---- lib/fdtdec.c | 171 ++++++++++++++++++++++++++++++++++++++++++++++++++----- 2 files changed, 254 insertions(+), 25 deletions(-)

On 31 December 2014 at 11:17, Simon Glass sjg@chromium.org wrote:
On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
This commit adds several APIs to decode PCI device node according to the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Changes in v4:
- Check compatible string 12th byte against '\0'
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86/next, thanks!

There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
---
Changes in v4: None Changes in v3: - Update to use 'memory-mapped' and 'i/o-mapped' in several places - Use 'Processor Local Bus' instead of 'plb' - Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto
Changes in v2: - New patch to support ns16550 compatible pci uart devices
drivers/serial/ns16550.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index af5beba..70c9462 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -289,7 +289,38 @@ int ns16550_serial_ofdata_to_platdata(struct udevice *dev) struct ns16550_platdata *plat = dev->platdata; fdt_addr_t addr;
+ /* try Processor Local Bus device first */ addr = fdtdec_get_addr(gd->fdt_blob, dev->of_offset, "reg"); +#ifdef CONFIG_PCI + if (addr == FDT_ADDR_T_NONE) { + /* then try pci device */ + struct fdt_pci_addr pci_addr; + u32 bar; + int ret; + + /* we prefer to use a memory-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, dev->of_offset, + FDT_PCI_SPACE_MEM32, "reg", + &pci_addr); + if (ret) { + /* try if there is any i/o-mapped register */ + ret = fdtdec_get_pci_addr(gd->fdt_blob, + dev->of_offset, + FDT_PCI_SPACE_IO, + "reg", &pci_addr); + if (ret) + return ret; + } + + ret = fdtdec_get_pci_bar32(gd->fdt_blob, dev->of_offset, + &pci_addr, &bar); + if (ret) + return ret; + + addr = bar; + } +#endif + if (addr == FDT_ADDR_T_NONE) return -EINVAL;

On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
There are many pci uart devices which are ns16550 compatible. We can describe them in the board dts file and use it as the U-Boot serial console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or i/o-mapped. The driver will try to use the memory-mapped register if the reg property in the node has an entry to describe the memory-mapped register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86/next, thanks!
Changes in v4: None Changes in v3:
- Update to use 'memory-mapped' and 'i/o-mapped' in several places
- Use 'Processor Local Bus' instead of 'plb'
- Change the logic in ns16550_serial_ofdata_to_platdata() to avoid goto
Changes in v2:
- New patch to support ns16550 compatible pci uart devices
drivers/serial/ns16550.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)

Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
---
Changes in v4: None Changes in v3: None Changes in v2: - New patch to use ePAPR defined properties for x86-uart
arch/x86/dts/serial.dtsi | 5 ++--- drivers/serial/serial_x86.c | 8 +++++++- 2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index ebdda76..9b097f4 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -3,8 +3,7 @@ compatible = "x86-uart"; reg = <0x3f8 8>; reg-shift = <0>; - io-mapped = <1>; - multiplier = <1>; - baudrate = <115200>; + clock-frequency = <1843200>; + current-speed = <115200>; }; }; diff --git a/drivers/serial/serial_x86.c b/drivers/serial/serial_x86.c index e81e035..4bf6062 100644 --- a/drivers/serial/serial_x86.c +++ b/drivers/serial/serial_x86.c @@ -6,9 +6,12 @@
#include <common.h> #include <dm.h> +#include <fdtdec.h> #include <ns16550.h> #include <serial.h>
+DECLARE_GLOBAL_DATA_PTR; + static const struct udevice_id x86_serial_ids[] = { { .compatible = "x86-uart" }, { } @@ -22,10 +25,13 @@ static int x86_serial_ofdata_to_platdata(struct udevice *dev) ret = ns16550_serial_ofdata_to_platdata(dev); if (ret) return ret; - plat->clock = 1843200; + + plat->clock = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "clock-frequency", 1843200);
return 0; } + U_BOOT_DRIVER(serial_ns16550) = { .name = "serial_x86", .id = UCLASS_SERIAL,

On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
Use ePAPR defined properties for x86-uart: clock-frequency and current-speed. Assign the value of clock-frequency in device tree to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng bmeng.cn@gmail.com Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86/next, thanks!
Changes in v4: None Changes in v3: None Changes in v2:
- New patch to use ePAPR defined properties for x86-uart
arch/x86/dts/serial.dtsi | 5 ++--- drivers/serial/serial_x86.c | 8 +++++++- 2 files changed, 9 insertions(+), 4 deletions(-)

The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
---
Changes in v4: - Add , after pciclass in the pci compatible string per spec - Drop the first 3 patches which are already applied
Changes in v3: None Changes in v2: - New patch to add pci devices in crownbay.dts - Drop v1 patch: Add an API for finding pci devices in the early phase - Drop v1 patch: Support PCI UART in the x86_serial driver - Drop v1 patch: Add PCI UART related defines in crownbay.h
arch/x86/dts/crownbay.dts | 81 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)
diff --git a/arch/x86/dts/crownbay.dts b/arch/x86/dts/crownbay.dts index 97f7a52..e81054e 100644 --- a/arch/x86/dts/crownbay.dts +++ b/arch/x86/dts/crownbay.dts @@ -32,6 +32,14 @@ };
chosen { + /* + * By default the legacy superio serial port is used as the + * U-Boot serial console. If we want to use UART from Topcliff + * PCH as the console, change this property to &pciuart#. + * + * For example, stdout-path = &pciuart0 will use the first + * UART on Topcliff PCH. + */ stdout-path = "/serial"; };
@@ -52,4 +60,77 @@ }; };
+ pci { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + pcie@17,0 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + topcliff@0,0 { + #address-cells = <3>; + #size-cells = <2>; + compatible = "intel,pci"; + device_type = "pci"; + + pciuart0: uart@a,1 { + compatible = "pci8086,8811.00", + "pci8086,8811", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025100 0x0 0x0 0x0 0x0 + 0x01025110 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart1: uart@a,2 { + compatible = "pci8086,8812.00", + "pci8086,8812", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025200 0x0 0x0 0x0 0x0 + 0x01025210 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart2: uart@a,3 { + compatible = "pci8086,8813.00", + "pci8086,8813", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025300 0x0 0x0 0x0 0x0 + 0x01025310 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + + pciuart3: uart@a,4 { + compatible = "pci8086,8814.00", + "pci8086,8814", + "pciclass,070002", + "pciclass,0700", + "x86-uart"; + reg = <0x00025400 0x0 0x0 0x0 0x0 + 0x01025410 0x0 0x0 0x0 0x0>; + reg-shift = <0>; + clock-frequency = <1843200>; + current-speed = <115200>; + }; + }; + }; + }; + };

On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Acked-by: Simon Glass sjg@chromium.org
Changes in v4:
- Add , after pciclass in the pci compatible string per spec
- Drop the first 3 patches which are already applied
Changes in v3: None Changes in v2:
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h
arch/x86/dts/crownbay.dts | 81 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)

On 31 December 2014 at 11:20, Simon Glass sjg@chromium.org wrote:
On 31 December 2014 at 01:05, Bin Meng bmeng.cn@gmail.com wrote:
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the chosen node, mentioning that by default the legacy superio serial port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
Acked-by: Simon Glass sjg@chromium.org
Applied to u-boot-x86/next, thanks!
Changes in v4:
- Add , after pciclass in the pci compatible string per spec
- Drop the first 3 patches which are already applied
Changes in v3: None Changes in v2:
- New patch to add pci devices in crownbay.dts
- Drop v1 patch: Add an API for finding pci devices in the early phase
- Drop v1 patch: Support PCI UART in the x86_serial driver
- Drop v1 patch: Add PCI UART related defines in crownbay.h
arch/x86/dts/crownbay.dts | 81 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+)
participants (2)
-
Bin Meng
-
Simon Glass