[U-Boot] [PATCH 1/2] ARM: dts: rmobile: Import DTS from Linux 4.12
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6, commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3 and H3 ULCB and Salvator-X boards.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/dts/Makefile | 6 + arch/arm/dts/r8a7795-h3ulcb.dts | 376 ++++++ arch/arm/dts/r8a7795-salvator-x.dts | 584 ++++++++ arch/arm/dts/r8a7795.dtsi | 1866 ++++++++++++++++++++++++++ arch/arm/dts/r8a7796-m3ulcb.dts | 188 +++ arch/arm/dts/r8a7796-salvator-x.dts | 269 ++++ arch/arm/dts/r8a7796.dtsi | 1037 ++++++++++++++ include/dt-bindings/clock/r8a7795-cpg-mssr.h | 70 + include/dt-bindings/clock/r8a7796-cpg-mssr.h | 69 + include/dt-bindings/clock/renesas-cpg-mssr.h | 15 + include/dt-bindings/power/r8a7795-sysc.h | 42 + include/dt-bindings/power/r8a7796-sysc.h | 36 + 12 files changed, 4558 insertions(+) create mode 100644 arch/arm/dts/r8a7795-h3ulcb.dts create mode 100644 arch/arm/dts/r8a7795-salvator-x.dts create mode 100644 arch/arm/dts/r8a7795.dtsi create mode 100644 arch/arm/dts/r8a7796-m3ulcb.dts create mode 100644 arch/arm/dts/r8a7796-salvator-x.dts create mode 100644 arch/arm/dts/r8a7796.dtsi create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h create mode 100644 include/dt-bindings/clock/r8a7796-cpg-mssr.h create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a7795-sysc.h create mode 100644 include/dt-bindings/power/r8a7796-sysc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 132fa69fe5..422b88bc9a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -370,6 +370,12 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_RCAR_GEN3) += \ + r8a7795-h3ulcb.dtb \ + r8a7795-salvator-x.dtb \ + r8a7796-m3ulcb.dtb \ + r8a7796-salvator-x.dtb + dtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ diff --git a/arch/arm/dts/r8a7795-h3ulcb.dts b/arch/arm/dts/r8a7795-h3ulcb.dts new file mode 100644 index 0000000000..ab352159de --- /dev/null +++ b/arch/arm/dts/r8a7795-h3ulcb.dts @@ -0,0 +1,376 @@ +/* + * Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Renesas H3ULCB board based on r8a7795"; + compatible = "renesas,h3ulcb", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + ethernet0 = &avb; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x40000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x40000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x40000000>; + }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + audio_clkout: audio-clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound-clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk-multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a7795-salvator-x.dts new file mode 100644 index 0000000000..639aa085d9 --- /dev/null +++ b/arch/arm/dts/r8a7795-salvator-x.dts @@ -0,0 +1,584 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/* + * SSI-AK4613 + * + * This command is required when Playback/Capture + * + * amixer set "DVC Out" 100% + * amixer set "DVC In" 100% + * + * You can use Mute + * + * amixer set "DVC Out Mute" on + * amixer set "DVC In Mute" on + * + * You can use Volume Ramp + * + * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps" + * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps" + * amixer set "DVC Out Ramp" on + * aplay xxx.wav & + * amixer set "DVC Out" 80% // Volume Down + * amixer set "DVC Out" 100% // Volume Up + */ + +/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas Salvator-X board based on r8a7795"; + compatible = "renesas,salvator-x", "renesas,r8a7795"; + + aliases { + serial0 = &scif2; + serial1 = &scif1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + x12_clk: x12 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vbus0_usb2: regulator-vbus0-usb2 { + compatible = "regulator-fixed"; + + regulator-name = "USB20_VBUS0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + + gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + audio_clkout: audio_clkout { + /* + * This is same as <&rcar_sound 0> + * but needed to avoid cs2000/rcar_sound probe dead-lock + */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <11289600>; + }; + + rsnd_ak4613: sound { + compatible = "simple-audio-card"; + + simple-audio-card,format = "left_j"; + simple-audio-card,bitclock-master = <&sndcpu>; + simple-audio-card,frame-master = <&sndcpu>; + + sndcpu: simple-audio-card,cpu { + sound-dai = <&rcar_sound>; + }; + + sndcodec: simple-audio-card,codec { + sound-dai = <&ak4613>; + }; + }; + + vga-encoder { + compatible = "adi,adv7123"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7123_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + port@1 { + reg = <1>; + adv7123_out: endpoint { + remote-endpoint = <&vga_in>; + }; + }; + }; + }; + + vga { + compatible = "vga-connector"; + + port { + vga_in: endpoint { + remote-endpoint = <&adv7123_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + status = "okay"; + + ports { + port@0 { + endpoint { + remote-endpoint = <&adv7123_in>; + }; + }; + port@3 { + lvds_connector: endpoint { + }; + }; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_phy_int", "avb_mdc", + "avb_mii"; + function = "avb"; + }; + + pins_mdc { + groups = "avb_mdc"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + du_pins: du { + groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0"; + function = "du"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; + + sound_pins: sound { + groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a"; + function = "ssi"; + }; + + sound_clk_pins: sound_clk { + groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a", + "audio_clkout_a", "audio_clkout3_a"; + function = "audio_clk"; + }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + mux { + groups = "usb1"; + function = "usb1"; + }; + + ovc { + pins = "GP_6_27"; + bias-pull-up; + }; + + pwen { + pins = "GP_6_26"; + bias-pull-down; + }; + }; + + usb2_pins: usb2 { + groups = "usb2"; + function = "usb2"; + }; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + + clock-frequency = <100000>; + + ak4613: codec@10 { + compatible = "asahi-kasei,ak4613"; + #sound-dai-cells = <0>; + reg = <0x10>; + clocks = <&rcar_sound 3>; + + asahi-kasei,in1-single-end; + asahi-kasei,in2-single-end; + asahi-kasei,out1-single-end; + asahi-kasei,out2-single-end; + asahi-kasei,out3-single-end; + asahi-kasei,out4-single-end; + asahi-kasei,out5-single-end; + asahi-kasei,out6-single-end; + }; + + cs2000: clk_multiplier@4f { + #clock-cells = <0>; + compatible = "cirrus,cs2000-cp"; + reg = <0x4f>; + clocks = <&audio_clkout>, <&x12_clk>; + clock-names = "clk_in", "ref_clk"; + + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24576000>; /* 1/1 divide */ + }; +}; + +&rcar_sound { + pinctrl-0 = <&sound_pins &sound_clk_pins>; + pinctrl-names = "default"; + + /* Single DAI */ + #sound-dai-cells = <0>; + + /* audio_clkout0/1/2/3 */ + #clock-cells = <1>; + clock-frequency = <11289600>; + + status = "okay"; + + /* update <audio_clk_b> to <cs2000> */ + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&cs2000>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + + rcar_sound,dai { + dai0 { + playback = <&ssi0 &src0 &dvc0>; + capture = <&ssi1 &src1 &dvc1>; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&ssi1 { + shared-pin; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&audio_clk_a { + clock-frequency = <22579200>; +}; + +&i2c_dvfs { + status = "okay"; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&xhci0 { + status = "okay"; +}; + +&usb2_phy0 { + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; + + vbus-supply = <&vbus0_usb2>; + status = "okay"; +}; + +&usb2_phy1 { + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&usb2_phy2 { + pinctrl-0 = <&usb2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&ehci2 { + status = "okay"; +}; + +&ohci0 { + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&ohci2 { + status = "okay"; +}; + +&hsusb { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pciec0 { + status = "okay"; +}; + +&pciec1 { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi new file mode 100644 index 0000000000..e99d6443b3 --- /dev/null +++ b/arch/arm/dts/r8a7795.dtsi @@ -0,0 +1,1866 @@ +/* + * Device Tree Source for the r8a7795 SoC + * + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7795-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7795-sysc.h> + +/ { + compatible = "renesas,r8a7795"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_2: cpu@2 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x2>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU2>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_3: cpu@3 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x3>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA57_CPU3>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7795_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7795", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>, + <&a57_2>, + <&a57_3>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7795-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7795-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7795-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + pfc: pfc@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0 0xe6060000 0 0x50c>; + }; + + intc_ex: interrupt-controller@e61c0000 { + compatible = "renesas,intc-ex-r8a7795", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 407>; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma0: dma-controller@ec700000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec700000 0 0x10000>; + interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 502>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 502>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + audma1: dma-controller@ec720000 { + compatible = "renesas,dmac-r8a7795", + "renesas,rcar-dmac"; + reg = <0 0xec720000 0 0x10000>; + interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 501>; + clock-names = "fck"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 501>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7795", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7795", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7795-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 96>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 96>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 96>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 96>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7795", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 96>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x13>, <&dmac1 0x12>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7795", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7795_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7795", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&cpg CPG_MOD 523>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 523>; + #pwm-cells = <2>; + status = "disabled"; + }; + + rcar_sound: sound@ec500000 { + /* + * #sound-dai-cells is required + * + * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; + * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; + */ + /* + * #clock-cells is required for audio_clkout0/1/2/3 + * + * clkout : #clock-cells = <0>; <&rcar_sound>; + * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; + */ + compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3"; + reg = <0 0xec500000 0 0x1000>, /* SCU */ + <0 0xec5a0000 0 0x100>, /* ADG */ + <0 0xec540000 0 0x1000>, /* SSIU */ + <0 0xec541000 0 0x280>, /* SSI */ + <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ + reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; + + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, + <&audio_clk_c>, + <&cpg CPG_CORE R8A7795_CLK_S0D4>; + clock-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", + "ssi.5", "ssi.4", "ssi.3", "ssi.2", + "ssi.1", "ssi.0", + "src.9", "src.8", "src.7", "src.6", + "src.5", "src.4", "src.3", "src.2", + "src.1", "src.0", + "mix.1", "mix.0", + "ctu.1", "ctu.0", + "dvc.0", "dvc.1", + "clk_a", "clk_b", "clk_c", "clk_i"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + + rcar_sound,dvc { + dvc0: dvc-0 { + dmas = <&audma1 0xbc>; + dma-names = "tx"; + }; + dvc1: dvc-1 { + dmas = <&audma1 0xbe>; + dma-names = "tx"; + }; + }; + + rcar_sound,mix { + mix0: mix-0 { }; + mix1: mix-1 { }; + }; + + rcar_sound,ctu { + ctu00: ctu-0 { }; + ctu01: ctu-1 { }; + ctu02: ctu-2 { }; + ctu03: ctu-3 { }; + ctu10: ctu-4 { }; + ctu11: ctu-5 { }; + ctu12: ctu-6 { }; + ctu13: ctu-7 { }; + }; + + rcar_sound,src { + src0: src-0 { + interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x85>, <&audma1 0x9a>; + dma-names = "rx", "tx"; + }; + src1: src-1 { + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x87>, <&audma1 0x9c>; + dma-names = "rx", "tx"; + }; + src2: src-2 { + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x89>, <&audma1 0x9e>; + dma-names = "rx", "tx"; + }; + src3: src-3 { + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8b>, <&audma1 0xa0>; + dma-names = "rx", "tx"; + }; + src4: src-4 { + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8d>, <&audma1 0xb0>; + dma-names = "rx", "tx"; + }; + src5: src-5 { + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x8f>, <&audma1 0xb2>; + dma-names = "rx", "tx"; + }; + src6: src-6 { + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x91>, <&audma1 0xb4>; + dma-names = "rx", "tx"; + }; + src7: src-7 { + interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x93>, <&audma1 0xb6>; + dma-names = "rx", "tx"; + }; + src8: src-8 { + interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x95>, <&audma1 0xb8>; + dma-names = "rx", "tx"; + }; + src9: src-9 { + interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x97>, <&audma1 0xba>; + dma-names = "rx", "tx"; + }; + }; + + rcar_sound,ssi { + ssi0: ssi-0 { + interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi1: ssi-1 { + interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi2: ssi-2 { + interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi3: ssi-3 { + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi4: ssi-4 { + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi5: ssi-5 { + interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi6: ssi-6 { + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi7: ssi-7 { + interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi8: ssi-8 { + interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + ssi9: ssi-9 { + interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; + dma-names = "rx", "tx", "rxu", "txu"; + }; + }; + }; + + sata: sata@ee300000 { + compatible = "renesas,sata-r8a7795"; + reg = <0 0xee300000 0 0x200000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 815>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 815>; + status = "disabled"; + }; + + xhci0: usb@ee000000 { + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; + reg = <0 0xee000000 0 0xc00>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 328>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 328>; + status = "disabled"; + }; + + xhci1: usb@ee0400000 { + compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci"; + reg = <0 0xee040000 0 0xc00>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 327>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 327>; + status = "disabled"; + }; + + usb_dmac0: dma-controller@e65a0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65a0000 0 0x100>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 330>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 330>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + usb_dmac1: dma-controller@e65b0000 { + compatible = "renesas,r8a7795-usb-dmac", + "renesas,usb-dmac"; + reg = <0 0xe65b0000 0 0x100>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1"; + clocks = <&cpg CPG_MOD 331>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 331>; + #dma-cells = <1>; + dma-channels = <2>; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7795"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + usb2_phy0: usb-phy@ee080200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee080200 0 0x700>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy1: usb-phy@ee0a0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0a0200 0 0x700>; + clocks = <&cpg CPG_MOD 702>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2_phy2: usb-phy@ee0c0200 { + compatible = "renesas,usb2-phy-r8a7795", + "renesas,rcar-gen3-usb2-phy"; + reg = <0 0xee0c0200 0 0x700>; + clocks = <&cpg CPG_MOD 701>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + #phy-cells = <0>; + status = "disabled"; + }; + + ehci0: usb@ee080100 { + compatible = "generic-ehci"; + reg = <0 0xee080100 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ehci1: usb@ee0a0100 { + compatible = "generic-ehci"; + reg = <0 0xee0a0100 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ehci2: usb@ee0c0100 { + compatible = "generic-ehci"; + reg = <0 0xee0c0100 0 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + status = "disabled"; + }; + + ohci0: usb@ee080000 { + compatible = "generic-ohci"; + reg = <0 0xee080000 0 0x100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + }; + + ohci1: usb@ee0a0000 { + compatible = "generic-ohci"; + reg = <0 0xee0a0000 0 0x100>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 702>; + phys = <&usb2_phy1>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 702>; + status = "disabled"; + }; + + ohci2: usb@ee0c0000 { + compatible = "generic-ohci"; + reg = <0 0xee0c0000 0 0x100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 701>; + phys = <&usb2_phy2>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 701>; + status = "disabled"; + }; + + hsusb: usb@e6590000 { + compatible = "renesas,usbhs-r8a7795", + "renesas,rcar-gen3-usbhs"; + reg = <0 0xe6590000 0 0x100>; + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 704>; + dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, + <&usb_dmac1 0>, <&usb_dmac1 1>; + dma-names = "ch0", "ch1", "ch2", "ch3"; + renesas,buswait = <11>; + phys = <&usb2_phy0>; + phy-names = "usb"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + }; + + pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a7795", + "renesas,pcie-rcar-gen3"; + reg = <0 0xfe000000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 + 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 + 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 + 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 319>; + status = "disabled"; + }; + + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a7795", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000 + 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000 + 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000 + 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + vspbc: vsp@fe920000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe920000 0 0x8000>; + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 624>; + + renesas,fcp = <&fcpvb1>; + }; + + fcpvb1: fcp@fe92f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe92f000 0 0x200>; + clocks = <&cpg CPG_MOD 606>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 606>; + }; + + fcpf0: fcp@fe950000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe950000 0 0x200>; + clocks = <&cpg CPG_MOD 615>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 615>; + }; + + fcpf1: fcp@fe951000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe951000 0 0x200>; + clocks = <&cpg CPG_MOD 614>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 614>; + }; + + fcpf2: fcp@fe952000 { + compatible = "renesas,fcpf"; + reg = <0 0xfe952000 0 0x200>; + clocks = <&cpg CPG_MOD 613>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 613>; + }; + + vspbd: vsp@fe960000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe960000 0 0x8000>; + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 626>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 626>; + + renesas,fcp = <&fcpvb0>; + }; + + fcpvb0: fcp@fe96f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe96f000 0 0x200>; + clocks = <&cpg CPG_MOD 607>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 607>; + }; + + vspi0: vsp@fe9a0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9a0000 0 0x8000>; + interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 631>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 631>; + + renesas,fcp = <&fcpvi0>; + }; + + fcpvi0: fcp@fe9af000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9af000 0 0x200>; + clocks = <&cpg CPG_MOD 611>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 611>; + }; + + vspi1: vsp@fe9b0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9b0000 0 0x8000>; + interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 630>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 630>; + + renesas,fcp = <&fcpvi1>; + }; + + fcpvi1: fcp@fe9bf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9bf000 0 0x200>; + clocks = <&cpg CPG_MOD 610>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 610>; + }; + + vspi2: vsp@fe9c0000 { + compatible = "renesas,vsp2"; + reg = <0 0xfe9c0000 0 0x8000>; + interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 629>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 629>; + + renesas,fcp = <&fcpvi2>; + }; + + fcpvi2: fcp@fe9cf000 { + compatible = "renesas,fcpv"; + reg = <0 0xfe9cf000 0 0x200>; + clocks = <&cpg CPG_MOD 609>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 609>; + }; + + vspd0: vsp@fea20000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea20000 0 0x4000>; + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 623>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 623>; + + renesas,fcp = <&fcpvd0>; + }; + + fcpvd0: fcp@fea27000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea27000 0 0x200>; + clocks = <&cpg CPG_MOD 603>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 603>; + }; + + vspd1: vsp@fea28000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea28000 0 0x4000>; + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 622>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 622>; + + renesas,fcp = <&fcpvd1>; + }; + + fcpvd1: fcp@fea2f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea2f000 0 0x200>; + clocks = <&cpg CPG_MOD 602>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 602>; + }; + + vspd2: vsp@fea30000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea30000 0 0x4000>; + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 621>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 621>; + + renesas,fcp = <&fcpvd2>; + }; + + fcpvd2: fcp@fea37000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea37000 0 0x200>; + clocks = <&cpg CPG_MOD 601>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 601>; + }; + + vspd3: vsp@fea38000 { + compatible = "renesas,vsp2"; + reg = <0 0xfea38000 0 0x4000>; + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 620>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 620>; + + renesas,fcp = <&fcpvd3>; + }; + + fcpvd3: fcp@fea3f000 { + compatible = "renesas,fcpv"; + reg = <0 0xfea3f000 0 0x200>; + clocks = <&cpg CPG_MOD 600>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 600>; + }; + + fdp1@fe940000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe940000 0 0x2400>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 119>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 119>; + renesas,fcp = <&fcpf0>; + }; + + fdp1@fe944000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe944000 0 0x2400>; + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 118>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 118>; + renesas,fcp = <&fcpf1>; + }; + + fdp1@fe948000 { + compatible = "renesas,fdp1"; + reg = <0 0xfe948000 0 0x2400>; + interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 117>; + power-domains = <&sysc R8A7795_PD_A3VP>; + resets = <&cpg 117>; + renesas,fcp = <&fcpf2>; + }; + + du: display@feb00000 { + compatible = "renesas,du-r8a7795"; + reg = <0 0xfeb00000 0 0x80000>, + <0 0xfeb90000 0 0x14>; + reg-names = "du", "lvds.0"; + interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 721>, + <&cpg CPG_MOD 727>; + clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0"; + status = "disabled"; + + vsps = <&vspd0 &vspd1 &vspd2 &vspd3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + port@1 { + reg = <1>; + du_out_hdmi0: endpoint { + }; + }; + port@2 { + reg = <2>; + du_out_hdmi1: endpoint { + }; + }; + port@3 { + reg = <3>; + du_out_lvds0: endpoint { + }; + }; + }; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7795-thermal"; + reg = <0 0xe6198000 0 0x68>, + <0 0xe61a0000 0 0x5c>, + <0 0xe61a8000 0 0x5c>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/r8a7796-m3ulcb.dts b/arch/arm/dts/r8a7796-m3ulcb.dts new file mode 100644 index 0000000000..372b2a9447 --- /dev/null +++ b/arch/arm/dts/r8a7796-m3ulcb.dts @@ -0,0 +1,188 @@ +/* + * Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * Copyright (C) 2016 Cogent Embedded, Inc. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +/ { + model = "Renesas M3ULCB board based on r8a7796"; + compatible = "renesas,m3ulcb", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x38000000>; + }; + + leds { + compatible = "gpio-leds"; + + led5 { + gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>; + }; + led6 { + gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>; + }; + }; + + keyboard { + compatible = "gpio-keys"; + + key-1 { + linux,code = <KEY_1>; + label = "SW3"; + wakeup-source; + debounce-interval = <20>; + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>; + }; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts new file mode 100644 index 0000000000..c9f59b6ce3 --- /dev/null +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -0,0 +1,269 @@ +/* + * Device Tree Source for the Salvator-X board + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas Salvator-X board based on r8a7796"; + compatible = "renesas,salvator-x", "renesas,r8a7796"; + + aliases { + serial0 = &scif2; + serial1 = &scif1; + ethernet0 = &avb; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x80000000>; + }; + + reg_1p8v: regulator0 { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_sdhi0: regulator-vcc-sdhi0 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI0 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; + + vcc_sdhi3: regulator-vcc-sdhi3 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI3 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + vccq_sdhi3: regulator-vccq-sdhi3 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI3 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; +}; + +&pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + + avb_pins: avb { + groups = "avb_mdc"; + function = "avb"; + }; + + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + + scif2_pins: scif2 { + groups = "scif2_data_a"; + function = "scif2"; + }; + scif_clk_pins: scif_clk { + groups = "scif_clk_a"; + function = "scif_clk"; + }; + + i2c2_pins: i2c2 { + groups = "i2c2_a"; + function = "i2c2"; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + + sdhi0_pins_uhs: sd0_uhs { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <1800>; + }; + + sdhi2_pins: sd2 { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <3300>; + }; + + sdhi2_pins_uhs: sd2_uhs { + groups = "sdhi2_data8", "sdhi2_ctrl"; + function = "sdhi2"; + power-source = <1800>; + }; + + sdhi3_pins: sd3 { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <3300>; + }; + + sdhi3_pins_uhs: sd3_uhs { + groups = "sdhi3_data4", "sdhi3_ctrl"; + function = "sdhi3"; + power-source = <1800>; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + renesas,no-ether-link; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio2>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-1 = <&sdhi0_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi0>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&sdhi2 { + /* used for on-board 8bit eMMC */ + pinctrl-0 = <&sdhi2_pins>; + pinctrl-1 = <&sdhi2_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&sdhi3 { + pinctrl-0 = <&sdhi3_pins>; + pinctrl-1 = <&sdhi3_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi3>; + vqmmc-supply = <&vccq_sdhi3>; + cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + sd-uhs-sdr50; + status = "okay"; +}; + +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + +&scif2 { + pinctrl-0 = <&scif2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&wdt0 { + timeout-sec = <60>; + status = "okay"; +}; + +&i2c_dvfs { + status = "okay"; +}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi new file mode 100644 index 0000000000..2ec1ed5f49 --- /dev/null +++ b/arch/arm/dts/r8a7796.dtsi @@ -0,0 +1,1037 @@ +/* + * Device Tree Source for the r8a7796 SoC + * + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include <dt-bindings/clock/r8a7796-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7796-sysc.h> + +/ { + compatible = "renesas,r8a7796"; + #address-cells = <2>; + #size-cells = <2>; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + a57_0: cpu@0 { + compatible = "arm,cortex-a57", "arm,armv8"; + reg = <0x0>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU0>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + L2_CA57: cache-controller-0 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA57_SCU>; + cache-unified; + cache-level = <2>; + }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; + }; + + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + extalr_clk: extalr { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + /* External CAN clock - to be overridden by boards that provide it */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + /* External SCIF clock - to be overridden by boards that provide it */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@f1010000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + reg = <0x0 0xf1010000 0 0x1000>, + <0x0 0xf1020000 0 0x20000>, + <0x0 0xf1040000 0 0x20000>, + <0x0 0xf1060000 0 0x20000>; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; + clocks = <&cpg CPG_MOD 408>; + clock-names = "clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 408>; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; + }; + + wdt0: watchdog@e6020000 { + compatible = "renesas,r8a7796-wdt", + "renesas,rcar-gen3-wdt"; + reg = <0 0xe6020000 0 0x0c>; + clocks = <&cpg CPG_MOD 402>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 402>; + status = "disabled"; + }; + + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6050000 0 0x50>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6051000 0 0x50>; + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 29>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6052000 0 0x50>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 15>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6053000 0 0x50>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 16>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6054000 0 0x50>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 18>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055000 0 0x50>; + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055400 0 0x50>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 906>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 906>; + }; + + gpio7: gpio@e6055800 { + compatible = "renesas,gpio-r8a7796", + "renesas,gpio-rcar"; + reg = <0 0xe6055800 0 0x50>; + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 224 4>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + + pfc: pin-controller@e6060000 { + compatible = "renesas,pfc-r8a7796"; + reg = <0 0xe6060000 0 0x50c>; + }; + + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a57_0>, + <&a57_1>; + }; + + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7796-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&extalr_clk>; + clock-names = "extal", "extalr"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; + + rst: reset-controller@e6160000 { + compatible = "renesas,r8a7796-rst"; + reg = <0 0xe6160000 0 0x0200>; + }; + + prr: chipid@fff00044 { + compatible = "renesas,prr"; + reg = <0 0xfff00044 0 4>; + }; + + sysc: system-controller@e6180000 { + compatible = "renesas,r8a7796-sysc"; + reg = <0 0xe6180000 0 0x0400>; + #power-domain-cells = <1>; + }; + + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + + i2c0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6500000 0 0x40>; + interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 931>; + dmas = <&dmac1 0x91>, <&dmac1 0x90>, + <&dmac2 0x91>, <&dmac2 0x90>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c1: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 930>; + dmas = <&dmac1 0x93>, <&dmac1 0x92>, + <&dmac2 0x93>, <&dmac2 0x92>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe6510000 0 0x40>; + interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 929>; + dmas = <&dmac1 0x95>, <&dmac1 0x94>, + <&dmac2 0x95>, <&dmac2 0x94>; + dma-names = "tx", "rx", "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e66d0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d0000 0 0x40>; + interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 928>; + dmas = <&dmac0 0x97>, <&dmac0 0x96>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c4: i2c@e66d8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66d8000 0 0x40>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 927>; + dmas = <&dmac0 0x99>, <&dmac0 0x98>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c5: i2c@e66e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e0000 0 0x40>; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 919>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 919>; + dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <110>; + status = "disabled"; + }; + + i2c6: i2c@e66e8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7796", + "renesas,rcar-gen3-i2c"; + reg = <0 0xe66e8000 0 0x40>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 918>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 918>; + dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; + dma-names = "tx", "rx"; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + can0: can@e6c30000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c30000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 916>; + status = "disabled"; + }; + + can1: can@e6c38000 { + compatible = "renesas,can-r8a7796", + "renesas,rcar-gen3-can"; + reg = <0 0xe6c38000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 915>; + status = "disabled"; + }; + + canfd: can@e66c0000 { + compatible = "renesas,r8a7796-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0 0xe66c0000 0 0x8000>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7796_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 914>; + status = "disabled"; + + channel0 { + status = "disabled"; + }; + + channel1 { + status = "disabled"; + }; + }; + + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7796", + "renesas,etheravb-rcar-gen3"; + reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15", + "ch16", "ch17", "ch18", "ch19", + "ch20", "ch21", "ch22", "ch23", + "ch24"; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 812>; + phy-mode = "rgmii-txid"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 520>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 519>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 518>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 517>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 516>; + status = "disabled"; + }; + + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 207>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 206>; + status = "disabled"; + }; + + scif2: serial@e6e88000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e88000 0 64>; + interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 310>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 310>; + status = "disabled"; + }; + + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 204>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 203>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 202>; + status = "disabled"; + }; + + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 211>; + dmas = <&dmac1 0x41>, <&dmac1 0x40>, + <&dmac2 0x41>, <&dmac2 0x40>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 211>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 210>; + dmas = <&dmac1 0x43>, <&dmac1 0x42>, + <&dmac2 0x43>, <&dmac2 0x42>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 210>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 209>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 209>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a7796", + "renesas,rcar-gen3-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>; + dma-names = "tx", "rx"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 208>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac0: dma-controller@e6700000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe6700000 0 0x10000>; + interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 219>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 219>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac1: dma-controller@e7300000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7300000 0 0x10000>; + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 218>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 218>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + dmac2: dma-controller@e7310000 { + compatible = "renesas,dmac-r8a7796", + "renesas,rcar-dmac"; + reg = <0 0xe7310000 0 0x10000>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH + GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "error", + "ch0", "ch1", "ch2", "ch3", + "ch4", "ch5", "ch6", "ch7", + "ch8", "ch9", "ch10", "ch11", + "ch12", "ch13", "ch14", "ch15"; + clocks = <&cpg CPG_MOD 217>; + clock-names = "fck"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 217>; + #dma-cells = <1>; + dma-channels = <16>; + }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee100000 0 0x2000>; + interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 314>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee120000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee120000 0 0x2000>; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 313>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 313>; + status = "disabled"; + }; + + sdhi2: sd@ee140000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee140000 0 0x2000>; + interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 312>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi3: sd@ee160000 { + compatible = "renesas,sdhi-r8a7796"; + reg = <0 0xee160000 0 0x2000>; + interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 311>; + max-frequency = <200000000>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; + + tsc: thermal@e6198000 { + compatible = "renesas,r8a7796-thermal"; + reg = <0 0xe6198000 0 0x68>, + <0 0xe61a0000 0 0x5c>, + <0 0xe61a8000 0 0x5c>; + interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 522>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + resets = <&cpg 522>; + #thermal-sensor-cells = <1>; + status = "okay"; + }; + + thermal-zones { + sensor_thermal1: sensor-thermal1 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 0>; + + trips { + sensor1_crit: sensor1-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal2: sensor-thermal2 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 1>; + + trips { + sensor2_crit: sensor2-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + sensor_thermal3: sensor-thermal3 { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsc 2>; + + trips { + sensor3_crit: sensor3-crit { + temperature = <120000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; + }; +}; diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644 index 0000000000..f047eaf261 --- /dev/null +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7795 CPG Core Clocks */ +#define R8A7795_CLK_Z 0 +#define R8A7795_CLK_Z2 1 +#define R8A7795_CLK_ZR 2 +#define R8A7795_CLK_ZG 3 +#define R8A7795_CLK_ZTR 4 +#define R8A7795_CLK_ZTRD2 5 +#define R8A7795_CLK_ZT 6 +#define R8A7795_CLK_ZX 7 +#define R8A7795_CLK_S0D1 8 +#define R8A7795_CLK_S0D4 9 +#define R8A7795_CLK_S1D1 10 +#define R8A7795_CLK_S1D2 11 +#define R8A7795_CLK_S1D4 12 +#define R8A7795_CLK_S2D1 13 +#define R8A7795_CLK_S2D2 14 +#define R8A7795_CLK_S2D4 15 +#define R8A7795_CLK_S3D1 16 +#define R8A7795_CLK_S3D2 17 +#define R8A7795_CLK_S3D4 18 +#define R8A7795_CLK_LB 19 +#define R8A7795_CLK_CL 20 +#define R8A7795_CLK_ZB3 21 +#define R8A7795_CLK_ZB3D2 22 +#define R8A7795_CLK_CR 23 +#define R8A7795_CLK_CRD2 24 +#define R8A7795_CLK_SD0H 25 +#define R8A7795_CLK_SD0 26 +#define R8A7795_CLK_SD1H 27 +#define R8A7795_CLK_SD1 28 +#define R8A7795_CLK_SD2H 29 +#define R8A7795_CLK_SD2 30 +#define R8A7795_CLK_SD3H 31 +#define R8A7795_CLK_SD3 32 +#define R8A7795_CLK_SSP2 33 +#define R8A7795_CLK_SSP1 34 +#define R8A7795_CLK_SSPRS 35 +#define R8A7795_CLK_RPC 36 +#define R8A7795_CLK_RPCD2 37 +#define R8A7795_CLK_MSO 38 +#define R8A7795_CLK_CANFD 39 +#define R8A7795_CLK_HDMI 40 +#define R8A7795_CLK_CSI0 41 +#define R8A7795_CLK_CSIREF 42 +#define R8A7795_CLK_CP 43 +#define R8A7795_CLK_CPEX 44 +#define R8A7795_CLK_R 45 +#define R8A7795_CLK_OSC 46 + +/* r8a7795 ES2.0 CPG Core Clocks */ +#define R8A7795_CLK_S0D2 47 +#define R8A7795_CLK_S0D3 48 +#define R8A7795_CLK_S0D6 49 +#define R8A7795_CLK_S0D8 50 +#define R8A7795_CLK_S0D12 51 + +#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h new file mode 100644 index 0000000000..1e5942695f --- /dev/null +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2016 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ + +#include <dt-bindings/clock/renesas-cpg-mssr.h> + +/* r8a7796 CPG Core Clocks */ +#define R8A7796_CLK_Z 0 +#define R8A7796_CLK_Z2 1 +#define R8A7796_CLK_ZR 2 +#define R8A7796_CLK_ZG 3 +#define R8A7796_CLK_ZTR 4 +#define R8A7796_CLK_ZTRD2 5 +#define R8A7796_CLK_ZT 6 +#define R8A7796_CLK_ZX 7 +#define R8A7796_CLK_S0D1 8 +#define R8A7796_CLK_S0D2 9 +#define R8A7796_CLK_S0D3 10 +#define R8A7796_CLK_S0D4 11 +#define R8A7796_CLK_S0D6 12 +#define R8A7796_CLK_S0D8 13 +#define R8A7796_CLK_S0D12 14 +#define R8A7796_CLK_S1D1 15 +#define R8A7796_CLK_S1D2 16 +#define R8A7796_CLK_S1D4 17 +#define R8A7796_CLK_S2D1 18 +#define R8A7796_CLK_S2D2 19 +#define R8A7796_CLK_S2D4 20 +#define R8A7796_CLK_S3D1 21 +#define R8A7796_CLK_S3D2 22 +#define R8A7796_CLK_S3D4 23 +#define R8A7796_CLK_LB 24 +#define R8A7796_CLK_CL 25 +#define R8A7796_CLK_ZB3 26 +#define R8A7796_CLK_ZB3D2 27 +#define R8A7796_CLK_ZB3D4 28 +#define R8A7796_CLK_CR 29 +#define R8A7796_CLK_CRD2 30 +#define R8A7796_CLK_SD0H 31 +#define R8A7796_CLK_SD0 32 +#define R8A7796_CLK_SD1H 33 +#define R8A7796_CLK_SD1 34 +#define R8A7796_CLK_SD2H 35 +#define R8A7796_CLK_SD2 36 +#define R8A7796_CLK_SD3H 37 +#define R8A7796_CLK_SD3 38 +#define R8A7796_CLK_SSP2 39 +#define R8A7796_CLK_SSP1 40 +#define R8A7796_CLK_SSPRS 41 +#define R8A7796_CLK_RPC 42 +#define R8A7796_CLK_RPCD2 43 +#define R8A7796_CLK_MSO 44 +#define R8A7796_CLK_CANFD 45 +#define R8A7796_CLK_HDMI 46 +#define R8A7796_CLK_CSI0 47 +#define R8A7796_CLK_CSIREF 48 +#define R8A7796_CLK_CP 49 +#define R8A7796_CLK_CPEX 50 +#define R8A7796_CLK_R 51 +#define R8A7796_CLK_OSC 52 + +#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h new file mode 100644 index 0000000000..569a3cc33f --- /dev/null +++ b/include/dt-bindings/clock/renesas-cpg-mssr.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ + +#define CPG_CORE 0 /* Core Clock */ +#define CPG_MOD 1 /* Module Clock */ + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h new file mode 100644 index 0000000000..ad679eeda1 --- /dev/null +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7795_PD_CA57_CPU0 0 +#define R8A7795_PD_CA57_CPU1 1 +#define R8A7795_PD_CA57_CPU2 2 +#define R8A7795_PD_CA57_CPU3 3 +#define R8A7795_PD_CA53_CPU0 5 +#define R8A7795_PD_CA53_CPU1 6 +#define R8A7795_PD_CA53_CPU2 7 +#define R8A7795_PD_CA53_CPU3 8 +#define R8A7795_PD_A3VP 9 +#define R8A7795_PD_CA57_SCU 12 +#define R8A7795_PD_CR7 13 +#define R8A7795_PD_A3VC 14 +#define R8A7795_PD_3DG_A 17 +#define R8A7795_PD_3DG_B 18 +#define R8A7795_PD_3DG_C 19 +#define R8A7795_PD_3DG_D 20 +#define R8A7795_PD_CA53_SCU 21 +#define R8A7795_PD_3DG_E 22 +#define R8A7795_PD_A3IR 24 +#define R8A7795_PD_A2VC0 25 /* ES1.x only */ +#define R8A7795_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7795_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h new file mode 100644 index 0000000000..5b4daab44d --- /dev/null +++ b/include/dt-bindings/power/r8a7796-sysc.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2016 Glider bvba + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ +#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A7796_PD_CA57_CPU0 0 +#define R8A7796_PD_CA57_CPU1 1 +#define R8A7796_PD_CA53_CPU0 5 +#define R8A7796_PD_CA53_CPU1 6 +#define R8A7796_PD_CA53_CPU2 7 +#define R8A7796_PD_CA53_CPU3 8 +#define R8A7796_PD_CA57_SCU 12 +#define R8A7796_PD_CR7 13 +#define R8A7796_PD_A3VC 14 +#define R8A7796_PD_3DG_A 17 +#define R8A7796_PD_3DG_B 18 +#define R8A7796_PD_CA53_SCU 21 +#define R8A7796_PD_A3IR 24 +#define R8A7796_PD_A2VC0 25 +#define R8A7796_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A7796_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
Since the DTs are now in place, enable OF control so that they get bundled into the U-Boot.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org --- arch/arm/mach-rmobile/Kconfig | 1 + configs/r8a7795_salvator-x_defconfig | 2 +- configs/r8a7795_ulcb_defconfig | 2 +- configs/r8a7796_salvator-x_defconfig | 2 +- configs/r8a7796_ulcb_defconfig | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 4b05d78839..8922554d59 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -11,6 +11,7 @@ config RCAR_32 config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select ARM64 + select OF_CONTROL
endchoice
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index c0e3999f96..a562431208 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x" CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -19,4 +20,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index fd5fd55b80..46715f952b 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb" CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -18,4 +19,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index d57305112b..4927e45588 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x" CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -20,4 +21,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 96f903bb52..0bec182577 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A7796=y CONFIG_TARGET_ULCB=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb" CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -19,4 +20,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y
Applied to rmobile branch, thanks!
2017-07-22 6:17 GMT+09:00 Marek Vasut marek.vasut@gmail.com:
Since the DTs are now in place, enable OF control so that they get bundled into the U-Boot.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org
arch/arm/mach-rmobile/Kconfig | 1 + configs/r8a7795_salvator-x_defconfig | 2 +- configs/r8a7795_ulcb_defconfig | 2 +- configs/r8a7796_salvator-x_defconfig | 2 +- configs/r8a7796_ulcb_defconfig | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 4b05d78839..8922554d59 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -11,6 +11,7 @@ config RCAR_32 config RCAR_GEN3 bool "Renesas ARM SoCs R-Car Gen3 (64bit)" select ARM64
select OF_CONTROLendchoice
diff --git a/configs/r8a7795_salvator-x_defconfig b/configs/r8a7795_salvator-x_defconfig index c0e3999f96..a562431208 100644 --- a/configs/r8a7795_salvator-x_defconfig +++ b/configs/r8a7795_salvator-x_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7795-salvator-x" CONFIG_DEFAULT_FDT_FILE="r8a7795-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -19,4 +20,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7795_ulcb_defconfig b/configs/r8a7795_ulcb_defconfig index fd5fd55b80..46715f952b 100644 --- a/configs/r8a7795_ulcb_defconfig +++ b/configs/r8a7795_ulcb_defconfig @@ -3,6 +3,7 @@ CONFIG_ARCH_RMOBILE=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7795-h3ulcb" CONFIG_DEFAULT_FDT_FILE="r8a7795-h3ulcb.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -18,4 +19,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7796_salvator-x_defconfig b/configs/r8a7796_salvator-x_defconfig index d57305112b..4927e45588 100644 --- a/configs/r8a7796_salvator-x_defconfig +++ b/configs/r8a7796_salvator-x_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A7796=y CONFIG_TARGET_SALVATOR_X=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7796-salvator-x" CONFIG_DEFAULT_FDT_FILE="r8a7796-salvator-x.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -20,4 +21,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y -CONFIG_OF_LIBFDT=y diff --git a/configs/r8a7796_ulcb_defconfig b/configs/r8a7796_ulcb_defconfig index 96f903bb52..0bec182577 100644 --- a/configs/r8a7796_ulcb_defconfig +++ b/configs/r8a7796_ulcb_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_RCAR_GEN3=y CONFIG_R8A7796=y CONFIG_TARGET_ULCB=y +CONFIG_DEFAULT_DEVICE_TREE="r8a7796-m3ulcb" CONFIG_DEFAULT_FDT_FILE="r8a7796-m3ulcb.dtb" CONFIG_VERSION_VARIABLE=y CONFIG_CMD_BOOTZ=y @@ -19,4 +20,3 @@ CONFIG_RENESAS_RAVB=y CONFIG_USB=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_STORAGE=y
-CONFIG_OF_LIBFDT=y
2.11.0
Applied to rmobile branch, thanks!
2017-07-22 6:16 GMT+09:00 Marek Vasut marek.vasut@gmail.com:
Import the RCar Gen3 DTS and headers from upstream Linux kernel v4.12-rc6, commit 6f7da290413ba713f0cdd9ff1a2a9bb129ef4f6c . This includes both M3 and H3 ULCB and Salvator-X boards.
Signed-off-by: Marek Vasut marek.vasut+renesas@gmail.com Cc: Nobuhiro Iwamatsu iwamatsu@nigauri.org
arch/arm/dts/Makefile | 6 + arch/arm/dts/r8a7795-h3ulcb.dts | 376 ++++++ arch/arm/dts/r8a7795-salvator-x.dts | 584 ++++++++ arch/arm/dts/r8a7795.dtsi | 1866 ++++++++++++++++++++++++++ arch/arm/dts/r8a7796-m3ulcb.dts | 188 +++ arch/arm/dts/r8a7796-salvator-x.dts | 269 ++++ arch/arm/dts/r8a7796.dtsi | 1037 ++++++++++++++ include/dt-bindings/clock/r8a7795-cpg-mssr.h | 70 + include/dt-bindings/clock/r8a7796-cpg-mssr.h | 69 + include/dt-bindings/clock/renesas-cpg-mssr.h | 15 + include/dt-bindings/power/r8a7795-sysc.h | 42 + include/dt-bindings/power/r8a7796-sysc.h | 36 + 12 files changed, 4558 insertions(+) create mode 100644 arch/arm/dts/r8a7795-h3ulcb.dts create mode 100644 arch/arm/dts/r8a7795-salvator-x.dts create mode 100644 arch/arm/dts/r8a7795.dtsi create mode 100644 arch/arm/dts/r8a7796-m3ulcb.dts create mode 100644 arch/arm/dts/r8a7796-salvator-x.dts create mode 100644 arch/arm/dts/r8a7796.dtsi create mode 100644 include/dt-bindings/clock/r8a7795-cpg-mssr.h create mode 100644 include/dt-bindings/clock/r8a7796-cpg-mssr.h create mode 100644 include/dt-bindings/clock/renesas-cpg-mssr.h create mode 100644 include/dt-bindings/power/r8a7795-sysc.h create mode 100644 include/dt-bindings/power/r8a7796-sysc.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 132fa69fe5..422b88bc9a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -370,6 +370,12 @@ dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
+dtb-$(CONFIG_RCAR_GEN3) += \
r8a7795-h3ulcb.dtb \r8a7795-salvator-x.dtb \r8a7796-m3ulcb.dtb \r8a7796-salvator-x.dtbdtb-$(CONFIG_SOC_KEYSTONE) += keystone-k2hk-evm.dtb \ keystone-k2l-evm.dtb \ keystone-k2e-evm.dtb \ diff --git a/arch/arm/dts/r8a7795-h3ulcb.dts b/arch/arm/dts/r8a7795-h3ulcb.dts new file mode 100644 index 0000000000..ab352159de --- /dev/null +++ b/arch/arm/dts/r8a7795-h3ulcb.dts @@ -0,0 +1,376 @@ +/*
- Device Tree Source for the H3ULCB (R-Car Starter Kit Premier) board
- Copyright (C) 2016 Renesas Electronics Corp.
- Copyright (C) 2016 Cogent Embedded, Inc.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h>
+/ {
model = "Renesas H3ULCB board based on r8a7795";compatible = "renesas,h3ulcb", "renesas,r8a7795";aliases {serial0 = &scif2;ethernet0 = &avb;};chosen {stdout-path = "serial0:115200n8";};memory@48000000 {device_type = "memory";/* first 128MB is reserved for secure area. */reg = <0x0 0x48000000 0x0 0x38000000>;};memory@500000000 {device_type = "memory";reg = <0x5 0x00000000 0x0 0x40000000>;};memory@600000000 {device_type = "memory";reg = <0x6 0x00000000 0x0 0x40000000>;};memory@700000000 {device_type = "memory";reg = <0x7 0x00000000 0x0 0x40000000>;};leds {compatible = "gpio-leds";led5 {gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;};led6 {gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;};};keyboard {compatible = "gpio-keys";key-1 {linux,code = <KEY_1>;label = "SW3";wakeup-source;debounce-interval = <20>;gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;};};x12_clk: x12 {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <24576000>;};reg_1p8v: regulator0 {compatible = "regulator-fixed";regulator-name = "fixed-1.8V";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-boot-on;regulator-always-on;};reg_3p3v: regulator1 {compatible = "regulator-fixed";regulator-name = "fixed-3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-boot-on;regulator-always-on;};vcc_sdhi0: regulator-vcc-sdhi0 {compatible = "regulator-fixed";regulator-name = "SDHI0 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi0: regulator-vccq-sdhi0 {compatible = "regulator-gpio";regulator-name = "SDHI0 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};audio_clkout: audio-clkout {/** This is same as <&rcar_sound 0>* but needed to avoid cs2000/rcar_sound probe dead-lock*/compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <11289600>;};rsnd_ak4613: sound {compatible = "simple-audio-card";simple-audio-card,format = "left_j";simple-audio-card,bitclock-master = <&sndcpu>;simple-audio-card,frame-master = <&sndcpu>;sndcpu: simple-audio-card,cpu {sound-dai = <&rcar_sound>;};sndcodec: simple-audio-card,codec {sound-dai = <&ak4613>;};};+};
+&extal_clk {
clock-frequency = <16666666>;+};
+&extalr_clk {
clock-frequency = <32768>;+};
+&pfc {
pinctrl-0 = <&scif_clk_pins>;pinctrl-names = "default";scif2_pins: scif2 {groups = "scif2_data_a";function = "scif2";};scif_clk_pins: scif_clk {groups = "scif_clk_a";function = "scif_clk";};i2c2_pins: i2c2 {groups = "i2c2_a";function = "i2c2";};avb_pins: avb {groups = "avb_mdc";function = "avb";};sdhi0_pins: sd0 {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <3300>;};sdhi0_pins_uhs: sd0_uhs {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <1800>;};sdhi2_pins: sd2 {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <3300>;};sdhi2_pins_uhs: sd2_uhs {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <1800>;};sound_pins: sound {groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";function = "ssi";};sound_clk_pins: sound-clk {groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a","audio_clkout_a", "audio_clkout3_a";function = "audio_clk";};usb1_pins: usb1 {groups = "usb1";function = "usb1";};+};
+&scif2 {
pinctrl-0 = <&scif2_pins>;pinctrl-names = "default";status = "okay";+};
+&scif_clk {
clock-frequency = <14745600>;+};
+&i2c2 {
pinctrl-0 = <&i2c2_pins>;pinctrl-names = "default";status = "okay";clock-frequency = <100000>;ak4613: codec@10 {compatible = "asahi-kasei,ak4613";#sound-dai-cells = <0>;reg = <0x10>;clocks = <&rcar_sound 3>;asahi-kasei,in1-single-end;asahi-kasei,in2-single-end;asahi-kasei,out1-single-end;asahi-kasei,out2-single-end;asahi-kasei,out3-single-end;asahi-kasei,out4-single-end;asahi-kasei,out5-single-end;asahi-kasei,out6-single-end;};cs2000: clk-multiplier@4f {#clock-cells = <0>;compatible = "cirrus,cs2000-cp";reg = <0x4f>;clocks = <&audio_clkout>, <&x12_clk>;clock-names = "clk_in", "ref_clk";assigned-clocks = <&cs2000>;assigned-clock-rates = <24576000>; /* 1/1 divide */};+};
+&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;pinctrl-names = "default";/* Single DAI */#sound-dai-cells = <0>;/* audio_clkout0/1/2/3 */#clock-cells = <1>;clock-frequency = <11289600>;status = "okay";/* update <audio_clk_b> to <cs2000> */clocks = <&cpg CPG_MOD 1005>,<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,<&audio_clk_a>, <&cs2000>,<&audio_clk_c>,<&cpg CPG_CORE R8A7795_CLK_S0D4>;rcar_sound,dai {dai0 {playback = <&ssi0 &src0 &dvc0>;capture = <&ssi1 &src1 &dvc1>;};};+};
+&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;pinctrl-1 = <&sdhi0_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi0>;vqmmc-supply = <&vccq_sdhi0>;cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&sdhi2 {
/* used for on-board 8bit eMMC */pinctrl-0 = <&sdhi2_pins>;pinctrl-1 = <&sdhi2_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <®_3p3v>;vqmmc-supply = <®_1p8v>;bus-width = <8>;non-removable;status = "okay";+};
+&ssi1 {
shared-pin;+};
+&wdt0 {
timeout-sec = <60>;status = "okay";+};
+&audio_clk_a {
clock-frequency = <22579200>;+};
+&avb {
pinctrl-0 = <&avb_pins>;pinctrl-names = "default";renesas,no-ether-link;phy-handle = <&phy0>;status = "okay";phy0: ethernet-phy@0 {rxc-skew-ps = <1500>;reg = <0>;interrupt-parent = <&gpio2>;interrupts = <11 IRQ_TYPE_LEVEL_LOW>;};+};
+&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;pinctrl-names = "default";status = "okay";+};
+&ehci1 {
status = "okay";+};
+&ohci1 {
status = "okay";+}; diff --git a/arch/arm/dts/r8a7795-salvator-x.dts b/arch/arm/dts/r8a7795-salvator-x.dts new file mode 100644 index 0000000000..639aa085d9 --- /dev/null +++ b/arch/arm/dts/r8a7795-salvator-x.dts @@ -0,0 +1,584 @@ +/*
- Device Tree Source for the Salvator-X board
- Copyright (C) 2015 Renesas Electronics Corp.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+/*
- SSI-AK4613
- This command is required when Playback/Capture
amixer set "DVC Out" 100%
amixer set "DVC In" 100%
- You can use Mute
amixer set "DVC Out Mute" on
amixer set "DVC In Mute" on
- You can use Volume Ramp
amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
amixer set "DVC Out Ramp" on
aplay xxx.wav &
amixer set "DVC Out" 80% // Volume Down
amixer set "DVC Out" 100% // Volume Up- */
+/dts-v1/; +#include "r8a7795.dtsi" +#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Renesas Salvator-X board based on r8a7795";compatible = "renesas,salvator-x", "renesas,r8a7795";aliases {serial0 = &scif2;serial1 = &scif1;ethernet0 = &avb;};chosen {bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";stdout-path = "serial0:115200n8";};memory@48000000 {device_type = "memory";/* first 128MB is reserved for secure area. */reg = <0x0 0x48000000 0x0 0x38000000>;};x12_clk: x12 {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <24576000>;};reg_1p8v: regulator0 {compatible = "regulator-fixed";regulator-name = "fixed-1.8V";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-boot-on;regulator-always-on;};reg_3p3v: regulator1 {compatible = "regulator-fixed";regulator-name = "fixed-3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-boot-on;regulator-always-on;};vcc_sdhi0: regulator-vcc-sdhi0 {compatible = "regulator-fixed";regulator-name = "SDHI0 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi0: regulator-vccq-sdhi0 {compatible = "regulator-gpio";regulator-name = "SDHI0 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};vcc_sdhi3: regulator-vcc-sdhi3 {compatible = "regulator-fixed";regulator-name = "SDHI3 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi3: regulator-vccq-sdhi3 {compatible = "regulator-gpio";regulator-name = "SDHI3 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};vbus0_usb2: regulator-vbus0-usb2 {compatible = "regulator-fixed";regulator-name = "USB20_VBUS0";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;gpio = <&gpio6 16 GPIO_ACTIVE_HIGH>;enable-active-high;};audio_clkout: audio_clkout {/** This is same as <&rcar_sound 0>* but needed to avoid cs2000/rcar_sound probe dead-lock*/compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <11289600>;};rsnd_ak4613: sound {compatible = "simple-audio-card";simple-audio-card,format = "left_j";simple-audio-card,bitclock-master = <&sndcpu>;simple-audio-card,frame-master = <&sndcpu>;sndcpu: simple-audio-card,cpu {sound-dai = <&rcar_sound>;};sndcodec: simple-audio-card,codec {sound-dai = <&ak4613>;};};vga-encoder {compatible = "adi,adv7123";ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;adv7123_in: endpoint {remote-endpoint = <&du_out_rgb>;};};port@1 {reg = <1>;adv7123_out: endpoint {remote-endpoint = <&vga_in>;};};};};vga {compatible = "vga-connector";port {vga_in: endpoint {remote-endpoint = <&adv7123_out>;};};};+};
+&du {
pinctrl-0 = <&du_pins>;pinctrl-names = "default";status = "okay";ports {port@0 {endpoint {remote-endpoint = <&adv7123_in>;};};port@3 {lvds_connector: endpoint {};};};+};
+&extal_clk {
clock-frequency = <16666666>;+};
+&extalr_clk {
clock-frequency = <32768>;+};
+&pfc {
pinctrl-0 = <&scif_clk_pins>;pinctrl-names = "default";scif1_pins: scif1 {groups = "scif1_data_a", "scif1_ctrl";function = "scif1";};scif2_pins: scif2 {groups = "scif2_data_a";function = "scif2";};scif_clk_pins: scif_clk {groups = "scif_clk_a";function = "scif_clk";};i2c2_pins: i2c2 {groups = "i2c2_a";function = "i2c2";};avb_pins: avb {mux {groups = "avb_link", "avb_phy_int", "avb_mdc","avb_mii";function = "avb";};pins_mdc {groups = "avb_mdc";drive-strength = <24>;};pins_mii_tx {pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0","PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3";drive-strength = <12>;};};du_pins: du {groups = "du_rgb888", "du_sync", "du_oddf", "du_clk_out_0";function = "du";};sdhi0_pins: sd0 {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <3300>;};sdhi0_pins_uhs: sd0_uhs {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <1800>;};sdhi2_pins: sd2 {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <3300>;};sdhi2_pins_uhs: sd2_uhs {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <1800>;};sdhi3_pins: sd3 {groups = "sdhi3_data4", "sdhi3_ctrl";function = "sdhi3";power-source = <3300>;};sdhi3_pins_uhs: sd3_uhs {groups = "sdhi3_data4", "sdhi3_ctrl";function = "sdhi3";power-source = <1800>;};sound_pins: sound {groups = "ssi01239_ctrl", "ssi0_data", "ssi1_data_a";function = "ssi";};sound_clk_pins: sound_clk {groups = "audio_clk_a_a", "audio_clk_b_a", "audio_clk_c_a","audio_clkout_a", "audio_clkout3_a";function = "audio_clk";};usb0_pins: usb0 {groups = "usb0";function = "usb0";};usb1_pins: usb1 {mux {groups = "usb1";function = "usb1";};ovc {pins = "GP_6_27";bias-pull-up;};pwen {pins = "GP_6_26";bias-pull-down;};};usb2_pins: usb2 {groups = "usb2";function = "usb2";};+};
+&scif1 {
pinctrl-0 = <&scif1_pins>;pinctrl-names = "default";uart-has-rtscts;status = "okay";+};
+&scif2 {
pinctrl-0 = <&scif2_pins>;pinctrl-names = "default";status = "okay";+};
+&scif_clk {
clock-frequency = <14745600>;+};
+&i2c2 {
pinctrl-0 = <&i2c2_pins>;pinctrl-names = "default";status = "okay";clock-frequency = <100000>;ak4613: codec@10 {compatible = "asahi-kasei,ak4613";#sound-dai-cells = <0>;reg = <0x10>;clocks = <&rcar_sound 3>;asahi-kasei,in1-single-end;asahi-kasei,in2-single-end;asahi-kasei,out1-single-end;asahi-kasei,out2-single-end;asahi-kasei,out3-single-end;asahi-kasei,out4-single-end;asahi-kasei,out5-single-end;asahi-kasei,out6-single-end;};cs2000: clk_multiplier@4f {#clock-cells = <0>;compatible = "cirrus,cs2000-cp";reg = <0x4f>;clocks = <&audio_clkout>, <&x12_clk>;clock-names = "clk_in", "ref_clk";assigned-clocks = <&cs2000>;assigned-clock-rates = <24576000>; /* 1/1 divide */};+};
+&rcar_sound {
pinctrl-0 = <&sound_pins &sound_clk_pins>;pinctrl-names = "default";/* Single DAI */#sound-dai-cells = <0>;/* audio_clkout0/1/2/3 */#clock-cells = <1>;clock-frequency = <11289600>;status = "okay";/* update <audio_clk_b> to <cs2000> */clocks = <&cpg CPG_MOD 1005>,<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,<&audio_clk_a>, <&cs2000>,<&audio_clk_c>,<&cpg CPG_CORE R8A7795_CLK_S0D4>;rcar_sound,dai {dai0 {playback = <&ssi0 &src0 &dvc0>;capture = <&ssi1 &src1 &dvc1>;};};+};
+&sata {
status = "okay";+};
+&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;pinctrl-1 = <&sdhi0_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi0>;vqmmc-supply = <&vccq_sdhi0>;cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&sdhi2 {
/* used for on-board 8bit eMMC */pinctrl-0 = <&sdhi2_pins>;pinctrl-1 = <&sdhi2_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <®_3p3v>;vqmmc-supply = <®_1p8v>;bus-width = <8>;non-removable;status = "okay";+};
+&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;pinctrl-1 = <&sdhi3_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi3>;vqmmc-supply = <&vccq_sdhi3>;cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&ssi1 {
shared-pin;+};
+&wdt0 {
timeout-sec = <60>;status = "okay";+};
+&audio_clk_a {
clock-frequency = <22579200>;+};
+&i2c_dvfs {
status = "okay";+};
+&avb {
pinctrl-0 = <&avb_pins>;pinctrl-names = "default";renesas,no-ether-link;phy-handle = <&phy0>;status = "okay";phy0: ethernet-phy@0 {rxc-skew-ps = <1500>;reg = <0>;interrupt-parent = <&gpio2>;interrupts = <11 IRQ_TYPE_LEVEL_LOW>;};+};
+&xhci0 {
status = "okay";+};
+&usb2_phy0 {
pinctrl-0 = <&usb0_pins>;pinctrl-names = "default";vbus-supply = <&vbus0_usb2>;status = "okay";+};
+&usb2_phy1 {
pinctrl-0 = <&usb1_pins>;pinctrl-names = "default";status = "okay";+};
+&usb2_phy2 {
pinctrl-0 = <&usb2_pins>;pinctrl-names = "default";status = "okay";+};
+&ehci0 {
status = "okay";+};
+&ehci1 {
status = "okay";+};
+&ehci2 {
status = "okay";+};
+&ohci0 {
status = "okay";+};
+&ohci1 {
status = "okay";+};
+&ohci2 {
status = "okay";+};
+&hsusb {
status = "okay";+};
+&pcie_bus_clk {
clock-frequency = <100000000>;+};
+&pciec0 {
status = "okay";+};
+&pciec1 {
status = "okay";+}; diff --git a/arch/arm/dts/r8a7795.dtsi b/arch/arm/dts/r8a7795.dtsi new file mode 100644 index 0000000000..e99d6443b3 --- /dev/null +++ b/arch/arm/dts/r8a7795.dtsi @@ -0,0 +1,1866 @@ +/*
- Device Tree Source for the r8a7795 SoC
- Copyright (C) 2015 Renesas Electronics Corp.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+#include <dt-bindings/clock/r8a7795-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7795-sysc.h>
+/ {
compatible = "renesas,r8a7795";#address-cells = <2>;#size-cells = <2>;aliases {i2c0 = &i2c0;i2c1 = &i2c1;i2c2 = &i2c2;i2c3 = &i2c3;i2c4 = &i2c4;i2c5 = &i2c5;i2c6 = &i2c6;i2c7 = &i2c_dvfs;};psci {compatible = "arm,psci-1.0", "arm,psci-0.2";method = "smc";};cpus {#address-cells = <1>;#size-cells = <0>;a57_0: cpu@0 {compatible = "arm,cortex-a57", "arm,armv8";reg = <0x0>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA57_CPU0>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a57_1: cpu@1 {compatible = "arm,cortex-a57","arm,armv8";reg = <0x1>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA57_CPU1>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a57_2: cpu@2 {compatible = "arm,cortex-a57","arm,armv8";reg = <0x2>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA57_CPU2>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a57_3: cpu@3 {compatible = "arm,cortex-a57","arm,armv8";reg = <0x3>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA57_CPU3>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a53_0: cpu@100 {compatible = "arm,cortex-a53", "arm,armv8";reg = <0x100>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA53_CPU0>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_1: cpu@101 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x101>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA53_CPU1>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_2: cpu@102 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x102>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA53_CPU2>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_3: cpu@103 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x103>;device_type = "cpu";power-domains = <&sysc R8A7795_PD_CA53_CPU3>;next-level-cache = <&L2_CA53>;enable-method = "psci";};L2_CA57: cache-controller-0 {compatible = "cache";power-domains = <&sysc R8A7795_PD_CA57_SCU>;cache-unified;cache-level = <2>;};L2_CA53: cache-controller-1 {compatible = "cache";power-domains = <&sysc R8A7795_PD_CA53_SCU>;cache-unified;cache-level = <2>;};};extal_clk: extal {compatible = "fixed-clock";#clock-cells = <0>;/* This value must be overridden by the board */clock-frequency = <0>;};extalr_clk: extalr {compatible = "fixed-clock";#clock-cells = <0>;/* This value must be overridden by the board */clock-frequency = <0>;};/** The external audio clocks are configured as 0 Hz fixed frequency* clocks by default.* Boards that provide audio clocks should override them.*/audio_clk_a: audio_clk_a {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};audio_clk_b: audio_clk_b {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};audio_clk_c: audio_clk_c {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};/* External CAN clock - to be overridden by boards that provide it */can_clk: can {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};/* External SCIF clock - to be overridden by boards that provide it */scif_clk: scif {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};/* External PCIe clock - can be overridden by the board */pcie_bus_clk: pcie_bus {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&gic>;#address-cells = <2>;#size-cells = <2>;ranges;gic: interrupt-controller@f1010000 {compatible = "arm,gic-400";#interrupt-cells = <3>;#address-cells = <0>;interrupt-controller;reg = <0x0 0xf1010000 0 0x1000>,<0x0 0xf1020000 0 0x20000>,<0x0 0xf1040000 0 0x20000>,<0x0 0xf1060000 0 0x20000>;interrupts = <GIC_PPI 9(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;clocks = <&cpg CPG_MOD 408>;clock-names = "clk";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 408>;};wdt0: watchdog@e6020000 {compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";reg = <0 0xe6020000 0 0x0c>;clocks = <&cpg CPG_MOD 402>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 402>;status = "disabled";};gpio0: gpio@e6050000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6050000 0 0x50>;interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 0 16>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 912>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 912>;};gpio1: gpio@e6051000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6051000 0 0x50>;interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 32 28>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 911>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 911>;};gpio2: gpio@e6052000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6052000 0 0x50>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 64 15>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 910>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 910>;};gpio3: gpio@e6053000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6053000 0 0x50>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 96 16>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 909>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 909>;};gpio4: gpio@e6054000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6054000 0 0x50>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 128 18>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 908>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 908>;};gpio5: gpio@e6055000 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6055000 0 0x50>;interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 160 26>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 907>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 907>;};gpio6: gpio@e6055400 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6055400 0 0x50>;interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 192 32>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 906>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 906>;};gpio7: gpio@e6055800 {compatible = "renesas,gpio-r8a7795","renesas,gpio-rcar";reg = <0 0xe6055800 0 0x50>;interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 224 4>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 905>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 905>;};pmu_a57 {compatible = "arm,cortex-a57-pmu";interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;interrupt-affinity = <&a57_0>,<&a57_1>,<&a57_2>,<&a57_3>;};pmu_a53 {compatible = "arm,cortex-a53-pmu";interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;interrupt-affinity = <&a53_0>,<&a53_1>,<&a53_2>,<&a53_3>;};timer {compatible = "arm,armv8-timer";interrupts = <GIC_PPI 13(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 14(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 11(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 10(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;};cpg: clock-controller@e6150000 {compatible = "renesas,r8a7795-cpg-mssr";reg = <0 0xe6150000 0 0x1000>;clocks = <&extal_clk>, <&extalr_clk>;clock-names = "extal", "extalr";#clock-cells = <2>;#power-domain-cells = <0>;#reset-cells = <1>;};rst: reset-controller@e6160000 {compatible = "renesas,r8a7795-rst";reg = <0 0xe6160000 0 0x0200>;};prr: chipid@fff00044 {compatible = "renesas,prr";reg = <0 0xfff00044 0 4>;};sysc: system-controller@e6180000 {compatible = "renesas,r8a7795-sysc";reg = <0 0xe6180000 0 0x0400>;#power-domain-cells = <1>;};pfc: pfc@e6060000 {compatible = "renesas,pfc-r8a7795";reg = <0 0xe6060000 0 0x50c>;};intc_ex: interrupt-controller@e61c0000 {compatible = "renesas,intc-ex-r8a7795", "renesas,irqc";#interrupt-cells = <2>;interrupt-controller;reg = <0 0xe61c0000 0 0x200>;interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGHGIC_SPI 1 IRQ_TYPE_LEVEL_HIGHGIC_SPI 2 IRQ_TYPE_LEVEL_HIGHGIC_SPI 3 IRQ_TYPE_LEVEL_HIGHGIC_SPI 18 IRQ_TYPE_LEVEL_HIGHGIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 407>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 407>;};dmac0: dma-controller@e6700000 {compatible = "renesas,dmac-r8a7795","renesas,rcar-dmac";reg = <0 0xe6700000 0 0x10000>;interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGHGIC_SPI 200 IRQ_TYPE_LEVEL_HIGHGIC_SPI 201 IRQ_TYPE_LEVEL_HIGHGIC_SPI 202 IRQ_TYPE_LEVEL_HIGHGIC_SPI 203 IRQ_TYPE_LEVEL_HIGHGIC_SPI 204 IRQ_TYPE_LEVEL_HIGHGIC_SPI 205 IRQ_TYPE_LEVEL_HIGHGIC_SPI 206 IRQ_TYPE_LEVEL_HIGHGIC_SPI 207 IRQ_TYPE_LEVEL_HIGHGIC_SPI 208 IRQ_TYPE_LEVEL_HIGHGIC_SPI 209 IRQ_TYPE_LEVEL_HIGHGIC_SPI 210 IRQ_TYPE_LEVEL_HIGHGIC_SPI 211 IRQ_TYPE_LEVEL_HIGHGIC_SPI 212 IRQ_TYPE_LEVEL_HIGHGIC_SPI 213 IRQ_TYPE_LEVEL_HIGHGIC_SPI 214 IRQ_TYPE_LEVEL_HIGHGIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 219>;clock-names = "fck";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 219>;#dma-cells = <1>;dma-channels = <16>;};dmac1: dma-controller@e7300000 {compatible = "renesas,dmac-r8a7795","renesas,rcar-dmac";reg = <0 0xe7300000 0 0x10000>;interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGHGIC_SPI 216 IRQ_TYPE_LEVEL_HIGHGIC_SPI 217 IRQ_TYPE_LEVEL_HIGHGIC_SPI 218 IRQ_TYPE_LEVEL_HIGHGIC_SPI 219 IRQ_TYPE_LEVEL_HIGHGIC_SPI 308 IRQ_TYPE_LEVEL_HIGHGIC_SPI 309 IRQ_TYPE_LEVEL_HIGHGIC_SPI 310 IRQ_TYPE_LEVEL_HIGHGIC_SPI 311 IRQ_TYPE_LEVEL_HIGHGIC_SPI 312 IRQ_TYPE_LEVEL_HIGHGIC_SPI 313 IRQ_TYPE_LEVEL_HIGHGIC_SPI 314 IRQ_TYPE_LEVEL_HIGHGIC_SPI 315 IRQ_TYPE_LEVEL_HIGHGIC_SPI 316 IRQ_TYPE_LEVEL_HIGHGIC_SPI 317 IRQ_TYPE_LEVEL_HIGHGIC_SPI 318 IRQ_TYPE_LEVEL_HIGHGIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 218>;clock-names = "fck";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 218>;#dma-cells = <1>;dma-channels = <16>;};dmac2: dma-controller@e7310000 {compatible = "renesas,dmac-r8a7795","renesas,rcar-dmac";reg = <0 0xe7310000 0 0x10000>;interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGHGIC_SPI 417 IRQ_TYPE_LEVEL_HIGHGIC_SPI 418 IRQ_TYPE_LEVEL_HIGHGIC_SPI 419 IRQ_TYPE_LEVEL_HIGHGIC_SPI 420 IRQ_TYPE_LEVEL_HIGHGIC_SPI 421 IRQ_TYPE_LEVEL_HIGHGIC_SPI 422 IRQ_TYPE_LEVEL_HIGHGIC_SPI 423 IRQ_TYPE_LEVEL_HIGHGIC_SPI 424 IRQ_TYPE_LEVEL_HIGHGIC_SPI 425 IRQ_TYPE_LEVEL_HIGHGIC_SPI 426 IRQ_TYPE_LEVEL_HIGHGIC_SPI 427 IRQ_TYPE_LEVEL_HIGHGIC_SPI 428 IRQ_TYPE_LEVEL_HIGHGIC_SPI 429 IRQ_TYPE_LEVEL_HIGHGIC_SPI 430 IRQ_TYPE_LEVEL_HIGHGIC_SPI 431 IRQ_TYPE_LEVEL_HIGHGIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 217>;clock-names = "fck";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 217>;#dma-cells = <1>;dma-channels = <16>;};audma0: dma-controller@ec700000 {compatible = "renesas,dmac-r8a7795","renesas,rcar-dmac";reg = <0 0xec700000 0 0x10000>;interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGHGIC_SPI 320 IRQ_TYPE_LEVEL_HIGHGIC_SPI 321 IRQ_TYPE_LEVEL_HIGHGIC_SPI 322 IRQ_TYPE_LEVEL_HIGHGIC_SPI 323 IRQ_TYPE_LEVEL_HIGHGIC_SPI 324 IRQ_TYPE_LEVEL_HIGHGIC_SPI 325 IRQ_TYPE_LEVEL_HIGHGIC_SPI 326 IRQ_TYPE_LEVEL_HIGHGIC_SPI 327 IRQ_TYPE_LEVEL_HIGHGIC_SPI 328 IRQ_TYPE_LEVEL_HIGHGIC_SPI 329 IRQ_TYPE_LEVEL_HIGHGIC_SPI 330 IRQ_TYPE_LEVEL_HIGHGIC_SPI 331 IRQ_TYPE_LEVEL_HIGHGIC_SPI 332 IRQ_TYPE_LEVEL_HIGHGIC_SPI 333 IRQ_TYPE_LEVEL_HIGHGIC_SPI 334 IRQ_TYPE_LEVEL_HIGHGIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 502>;clock-names = "fck";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 502>;#dma-cells = <1>;dma-channels = <16>;};audma1: dma-controller@ec720000 {compatible = "renesas,dmac-r8a7795","renesas,rcar-dmac";reg = <0 0xec720000 0 0x10000>;interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGHGIC_SPI 336 IRQ_TYPE_LEVEL_HIGHGIC_SPI 337 IRQ_TYPE_LEVEL_HIGHGIC_SPI 338 IRQ_TYPE_LEVEL_HIGHGIC_SPI 339 IRQ_TYPE_LEVEL_HIGHGIC_SPI 340 IRQ_TYPE_LEVEL_HIGHGIC_SPI 341 IRQ_TYPE_LEVEL_HIGHGIC_SPI 342 IRQ_TYPE_LEVEL_HIGHGIC_SPI 343 IRQ_TYPE_LEVEL_HIGHGIC_SPI 344 IRQ_TYPE_LEVEL_HIGHGIC_SPI 345 IRQ_TYPE_LEVEL_HIGHGIC_SPI 346 IRQ_TYPE_LEVEL_HIGHGIC_SPI 347 IRQ_TYPE_LEVEL_HIGHGIC_SPI 348 IRQ_TYPE_LEVEL_HIGHGIC_SPI 349 IRQ_TYPE_LEVEL_HIGHGIC_SPI 382 IRQ_TYPE_LEVEL_HIGHGIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 501>;clock-names = "fck";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 501>;#dma-cells = <1>;dma-channels = <16>;};avb: ethernet@e6800000 {compatible = "renesas,etheravb-r8a7795","renesas,etheravb-rcar-gen3";reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15","ch16", "ch17", "ch18", "ch19","ch20", "ch21", "ch22", "ch23","ch24";clocks = <&cpg CPG_MOD 812>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 812>;phy-mode = "rgmii-txid";#address-cells = <1>;#size-cells = <0>;status = "disabled";};can0: can@e6c30000 {compatible = "renesas,can-r8a7795","renesas,rcar-gen3-can";reg = <0 0xe6c30000 0 0x1000>;interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 916>,<&cpg CPG_CORE R8A7795_CLK_CANFD>,<&can_clk>;clock-names = "clkp1", "clkp2", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 916>;status = "disabled";};can1: can@e6c38000 {compatible = "renesas,can-r8a7795","renesas,rcar-gen3-can";reg = <0 0xe6c38000 0 0x1000>;interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 915>,<&cpg CPG_CORE R8A7795_CLK_CANFD>,<&can_clk>;clock-names = "clkp1", "clkp2", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 915>;status = "disabled";};canfd: can@e66c0000 {compatible = "renesas,r8a7795-canfd","renesas,rcar-gen3-canfd";reg = <0 0xe66c0000 0 0x8000>;interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 914>,<&cpg CPG_CORE R8A7795_CLK_CANFD>,<&can_clk>;clock-names = "fck", "canfd", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 914>;status = "disabled";channel0 {status = "disabled";};channel1 {status = "disabled";};};hscif0: serial@e6540000 {compatible = "renesas,hscif-r8a7795","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6540000 0 96>;interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 520>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x31>, <&dmac1 0x30>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 520>;status = "disabled";};hscif1: serial@e6550000 {compatible = "renesas,hscif-r8a7795","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6550000 0 96>;interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 519>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x33>, <&dmac1 0x32>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 519>;status = "disabled";};hscif2: serial@e6560000 {compatible = "renesas,hscif-r8a7795","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6560000 0 96>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 518>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x35>, <&dmac1 0x34>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 518>;status = "disabled";};hscif3: serial@e66a0000 {compatible = "renesas,hscif-r8a7795","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe66a0000 0 96>;interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 517>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x37>, <&dmac0 0x36>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 517>;status = "disabled";};hscif4: serial@e66b0000 {compatible = "renesas,hscif-r8a7795","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe66b0000 0 96>;interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 516>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x39>, <&dmac0 0x38>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 516>;status = "disabled";};scif0: serial@e6e60000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e60000 0 64>;interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 207>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x51>, <&dmac1 0x50>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 207>;status = "disabled";};scif1: serial@e6e68000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e68000 0 64>;interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 206>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x53>, <&dmac1 0x52>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 206>;status = "disabled";};scif2: serial@e6e88000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e88000 0 64>;interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 310>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x13>, <&dmac1 0x12>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 310>;status = "disabled";};scif3: serial@e6c50000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6c50000 0 64>;interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 204>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x57>, <&dmac0 0x56>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 204>;status = "disabled";};scif4: serial@e6c40000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6c40000 0 64>;interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 203>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x59>, <&dmac0 0x58>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 203>;status = "disabled";};scif5: serial@e6f30000 {compatible = "renesas,scif-r8a7795","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6f30000 0 64>;interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 202>,<&cpg CPG_CORE R8A7795_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x5b>, <&dmac1 0x5a>;dma-names = "tx", "rx";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 202>;status = "disabled";};i2c_dvfs: i2c@e60b0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,iic-r8a7795","renesas,rcar-gen3-iic","renesas,rmobile-iic";reg = <0 0xe60b0000 0 0x425>;interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 926>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 926>;status = "disabled";};i2c0: i2c@e6500000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe6500000 0 0x40>;interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 931>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 931>;dmas = <&dmac1 0x91>, <&dmac1 0x90>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c1: i2c@e6508000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe6508000 0 0x40>;interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 930>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 930>;dmas = <&dmac1 0x93>, <&dmac1 0x92>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};i2c2: i2c@e6510000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe6510000 0 0x40>;interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 929>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 929>;dmas = <&dmac1 0x95>, <&dmac1 0x94>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};i2c3: i2c@e66d0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe66d0000 0 0x40>;interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 928>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 928>;dmas = <&dmac0 0x97>, <&dmac0 0x96>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c4: i2c@e66d8000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe66d8000 0 0x40>;interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 927>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 927>;dmas = <&dmac0 0x99>, <&dmac0 0x98>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c5: i2c@e66e0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe66e0000 0 0x40>;interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 919>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 919>;dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c6: i2c@e66e8000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7795","renesas,rcar-gen3-i2c";reg = <0 0xe66e8000 0 0x40>;interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 918>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 918>;dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};pwm0: pwm@e6e30000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e30000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm1: pwm@e6e31000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e31000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm2: pwm@e6e32000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e32000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm3: pwm@e6e33000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e33000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm4: pwm@e6e34000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e34000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm5: pwm@e6e35000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e35000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};pwm6: pwm@e6e36000 {compatible = "renesas,pwm-r8a7795", "renesas,pwm-rcar";reg = <0 0xe6e36000 0 0x8>;clocks = <&cpg CPG_MOD 523>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 523>;#pwm-cells = <2>;status = "disabled";};rcar_sound: sound@ec500000 {/** #sound-dai-cells is required** Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;*//** #clock-cells is required for audio_clkout0/1/2/3** clkout : #clock-cells = <0>; <&rcar_sound>;* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;*/compatible = "renesas,rcar_sound-r8a7795", "renesas,rcar_sound-gen3";reg = <0 0xec500000 0 0x1000>, /* SCU */<0 0xec5a0000 0 0x100>, /* ADG */<0 0xec540000 0 0x1000>, /* SSIU */<0 0xec541000 0 0x280>, /* SSI */<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";clocks = <&cpg CPG_MOD 1005>,<&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,<&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,<&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,<&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,<&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,<&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>,<&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>,<&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>,<&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>,<&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,<&audio_clk_a>, <&audio_clk_b>,<&audio_clk_c>,<&cpg CPG_CORE R8A7795_CLK_S0D4>;clock-names = "ssi-all","ssi.9", "ssi.8", "ssi.7", "ssi.6","ssi.5", "ssi.4", "ssi.3", "ssi.2","ssi.1", "ssi.0","src.9", "src.8", "src.7", "src.6","src.5", "src.4", "src.3", "src.2","src.1", "src.0","mix.1", "mix.0","ctu.1", "ctu.0","dvc.0", "dvc.1","clk_a", "clk_b", "clk_c", "clk_i";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;status = "disabled";rcar_sound,dvc {dvc0: dvc-0 {dmas = <&audma1 0xbc>;dma-names = "tx";};dvc1: dvc-1 {dmas = <&audma1 0xbe>;dma-names = "tx";};};rcar_sound,mix {mix0: mix-0 { };mix1: mix-1 { };};rcar_sound,ctu {ctu00: ctu-0 { };ctu01: ctu-1 { };ctu02: ctu-2 { };ctu03: ctu-3 { };ctu10: ctu-4 { };ctu11: ctu-5 { };ctu12: ctu-6 { };ctu13: ctu-7 { };};rcar_sound,src {src0: src-0 {interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x85>, <&audma1 0x9a>;dma-names = "rx", "tx";};src1: src-1 {interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x87>, <&audma1 0x9c>;dma-names = "rx", "tx";};src2: src-2 {interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x89>, <&audma1 0x9e>;dma-names = "rx", "tx";};src3: src-3 {interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x8b>, <&audma1 0xa0>;dma-names = "rx", "tx";};src4: src-4 {interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x8d>, <&audma1 0xb0>;dma-names = "rx", "tx";};src5: src-5 {interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x8f>, <&audma1 0xb2>;dma-names = "rx", "tx";};src6: src-6 {interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x91>, <&audma1 0xb4>;dma-names = "rx", "tx";};src7: src-7 {interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x93>, <&audma1 0xb6>;dma-names = "rx", "tx";};src8: src-8 {interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x95>, <&audma1 0xb8>;dma-names = "rx", "tx";};src9: src-9 {interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x97>, <&audma1 0xba>;dma-names = "rx", "tx";};};rcar_sound,ssi {ssi0: ssi-0 {interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;dma-names = "rx", "tx", "rxu", "txu";};ssi1: ssi-1 {interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;dma-names = "rx", "tx", "rxu", "txu";};ssi2: ssi-2 {interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;dma-names = "rx", "tx", "rxu", "txu";};ssi3: ssi-3 {interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;dma-names = "rx", "tx", "rxu", "txu";};ssi4: ssi-4 {interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;dma-names = "rx", "tx", "rxu", "txu";};ssi5: ssi-5 {interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;dma-names = "rx", "tx", "rxu", "txu";};ssi6: ssi-6 {interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;dma-names = "rx", "tx", "rxu", "txu";};ssi7: ssi-7 {interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;dma-names = "rx", "tx", "rxu", "txu";};ssi8: ssi-8 {interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;dma-names = "rx", "tx", "rxu", "txu";};ssi9: ssi-9 {interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;dma-names = "rx", "tx", "rxu", "txu";};};};sata: sata@ee300000 {compatible = "renesas,sata-r8a7795";reg = <0 0xee300000 0 0x200000>;interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 815>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 815>;status = "disabled";};xhci0: usb@ee000000 {compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";reg = <0 0xee000000 0 0xc00>;interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 328>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 328>;status = "disabled";};xhci1: usb@ee0400000 {compatible = "renesas,xhci-r8a7795", "renesas,rcar-gen3-xhci";reg = <0 0xee040000 0 0xc00>;interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 327>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 327>;status = "disabled";};usb_dmac0: dma-controller@e65a0000 {compatible = "renesas,r8a7795-usb-dmac","renesas,usb-dmac";reg = <0 0xe65a0000 0 0x100>;interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGHGIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "ch0", "ch1";clocks = <&cpg CPG_MOD 330>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 330>;#dma-cells = <1>;dma-channels = <2>;};usb_dmac1: dma-controller@e65b0000 {compatible = "renesas,r8a7795-usb-dmac","renesas,usb-dmac";reg = <0 0xe65b0000 0 0x100>;interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGHGIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "ch0", "ch1";clocks = <&cpg CPG_MOD 331>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 331>;#dma-cells = <1>;dma-channels = <2>;};sdhi0: sd@ee100000 {compatible = "renesas,sdhi-r8a7795";reg = <0 0xee100000 0 0x2000>;interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 314>;max-frequency = <200000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 314>;status = "disabled";};sdhi1: sd@ee120000 {compatible = "renesas,sdhi-r8a7795";reg = <0 0xee120000 0 0x2000>;interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 313>;max-frequency = <200000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 313>;status = "disabled";};sdhi2: sd@ee140000 {compatible = "renesas,sdhi-r8a7795";reg = <0 0xee140000 0 0x2000>;interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 312>;max-frequency = <200000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 312>;status = "disabled";};sdhi3: sd@ee160000 {compatible = "renesas,sdhi-r8a7795";reg = <0 0xee160000 0 0x2000>;interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 311>;max-frequency = <200000000>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 311>;status = "disabled";};usb2_phy0: usb-phy@ee080200 {compatible = "renesas,usb2-phy-r8a7795","renesas,rcar-gen3-usb2-phy";reg = <0 0xee080200 0 0x700>;interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 703>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 703>;#phy-cells = <0>;status = "disabled";};usb2_phy1: usb-phy@ee0a0200 {compatible = "renesas,usb2-phy-r8a7795","renesas,rcar-gen3-usb2-phy";reg = <0 0xee0a0200 0 0x700>;clocks = <&cpg CPG_MOD 702>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 702>;#phy-cells = <0>;status = "disabled";};usb2_phy2: usb-phy@ee0c0200 {compatible = "renesas,usb2-phy-r8a7795","renesas,rcar-gen3-usb2-phy";reg = <0 0xee0c0200 0 0x700>;clocks = <&cpg CPG_MOD 701>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 701>;#phy-cells = <0>;status = "disabled";};ehci0: usb@ee080100 {compatible = "generic-ehci";reg = <0 0xee080100 0 0x100>;interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 703>;phys = <&usb2_phy0>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 703>;status = "disabled";};ehci1: usb@ee0a0100 {compatible = "generic-ehci";reg = <0 0xee0a0100 0 0x100>;interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 702>;phys = <&usb2_phy1>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 702>;status = "disabled";};ehci2: usb@ee0c0100 {compatible = "generic-ehci";reg = <0 0xee0c0100 0 0x100>;interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 701>;phys = <&usb2_phy2>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 701>;status = "disabled";};ohci0: usb@ee080000 {compatible = "generic-ohci";reg = <0 0xee080000 0 0x100>;interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 703>;phys = <&usb2_phy0>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 703>;status = "disabled";};ohci1: usb@ee0a0000 {compatible = "generic-ohci";reg = <0 0xee0a0000 0 0x100>;interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 702>;phys = <&usb2_phy1>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 702>;status = "disabled";};ohci2: usb@ee0c0000 {compatible = "generic-ohci";reg = <0 0xee0c0000 0 0x100>;interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 701>;phys = <&usb2_phy2>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 701>;status = "disabled";};hsusb: usb@e6590000 {compatible = "renesas,usbhs-r8a7795","renesas,rcar-gen3-usbhs";reg = <0 0xe6590000 0 0x100>;interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 704>;dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,<&usb_dmac1 0>, <&usb_dmac1 1>;dma-names = "ch0", "ch1", "ch2", "ch3";renesas,buswait = <11>;phys = <&usb2_phy0>;phy-names = "usb";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 704>;status = "disabled";};pciec0: pcie@fe000000 {compatible = "renesas,pcie-r8a7795","renesas,pcie-rcar-gen3";reg = <0 0xfe000000 0 0x80000>;#address-cells = <3>;#size-cells = <2>;bus-range = <0x00 0xff>;device_type = "pci";ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x001000000x02000000 0 0xfe200000 0 0xfe200000 0 0x002000000x02000000 0 0x30000000 0 0x30000000 0 0x080000000x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;/* Map all possible DDR as inbound ranges */dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 0>;interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;clock-names = "pcie", "pcie_bus";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 319>;status = "disabled";};pciec1: pcie@ee800000 {compatible = "renesas,pcie-r8a7795","renesas,pcie-rcar-gen3";reg = <0 0xee800000 0 0x80000>;#address-cells = <3>;#size-cells = <2>;bus-range = <0x00 0xff>;device_type = "pci";ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x001000000x02000000 0 0xeea00000 0 0xeea00000 0 0x002000000x02000000 0 0xc0000000 0 0xc0000000 0 0x080000000x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;/* Map all possible DDR as inbound ranges */dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;#interrupt-cells = <1>;interrupt-map-mask = <0 0 0 0>;interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;clock-names = "pcie", "pcie_bus";power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 318>;status = "disabled";};vspbc: vsp@fe920000 {compatible = "renesas,vsp2";reg = <0 0xfe920000 0 0x8000>;interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 624>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 624>;renesas,fcp = <&fcpvb1>;};fcpvb1: fcp@fe92f000 {compatible = "renesas,fcpv";reg = <0 0xfe92f000 0 0x200>;clocks = <&cpg CPG_MOD 606>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 606>;};fcpf0: fcp@fe950000 {compatible = "renesas,fcpf";reg = <0 0xfe950000 0 0x200>;clocks = <&cpg CPG_MOD 615>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 615>;};fcpf1: fcp@fe951000 {compatible = "renesas,fcpf";reg = <0 0xfe951000 0 0x200>;clocks = <&cpg CPG_MOD 614>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 614>;};fcpf2: fcp@fe952000 {compatible = "renesas,fcpf";reg = <0 0xfe952000 0 0x200>;clocks = <&cpg CPG_MOD 613>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 613>;};vspbd: vsp@fe960000 {compatible = "renesas,vsp2";reg = <0 0xfe960000 0 0x8000>;interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 626>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 626>;renesas,fcp = <&fcpvb0>;};fcpvb0: fcp@fe96f000 {compatible = "renesas,fcpv";reg = <0 0xfe96f000 0 0x200>;clocks = <&cpg CPG_MOD 607>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 607>;};vspi0: vsp@fe9a0000 {compatible = "renesas,vsp2";reg = <0 0xfe9a0000 0 0x8000>;interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 631>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 631>;renesas,fcp = <&fcpvi0>;};fcpvi0: fcp@fe9af000 {compatible = "renesas,fcpv";reg = <0 0xfe9af000 0 0x200>;clocks = <&cpg CPG_MOD 611>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 611>;};vspi1: vsp@fe9b0000 {compatible = "renesas,vsp2";reg = <0 0xfe9b0000 0 0x8000>;interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 630>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 630>;renesas,fcp = <&fcpvi1>;};fcpvi1: fcp@fe9bf000 {compatible = "renesas,fcpv";reg = <0 0xfe9bf000 0 0x200>;clocks = <&cpg CPG_MOD 610>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 610>;};vspi2: vsp@fe9c0000 {compatible = "renesas,vsp2";reg = <0 0xfe9c0000 0 0x8000>;interrupts = <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 629>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 629>;renesas,fcp = <&fcpvi2>;};fcpvi2: fcp@fe9cf000 {compatible = "renesas,fcpv";reg = <0 0xfe9cf000 0 0x200>;clocks = <&cpg CPG_MOD 609>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 609>;};vspd0: vsp@fea20000 {compatible = "renesas,vsp2";reg = <0 0xfea20000 0 0x4000>;interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 623>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 623>;renesas,fcp = <&fcpvd0>;};fcpvd0: fcp@fea27000 {compatible = "renesas,fcpv";reg = <0 0xfea27000 0 0x200>;clocks = <&cpg CPG_MOD 603>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 603>;};vspd1: vsp@fea28000 {compatible = "renesas,vsp2";reg = <0 0xfea28000 0 0x4000>;interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 622>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 622>;renesas,fcp = <&fcpvd1>;};fcpvd1: fcp@fea2f000 {compatible = "renesas,fcpv";reg = <0 0xfea2f000 0 0x200>;clocks = <&cpg CPG_MOD 602>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 602>;};vspd2: vsp@fea30000 {compatible = "renesas,vsp2";reg = <0 0xfea30000 0 0x4000>;interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 621>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 621>;renesas,fcp = <&fcpvd2>;};fcpvd2: fcp@fea37000 {compatible = "renesas,fcpv";reg = <0 0xfea37000 0 0x200>;clocks = <&cpg CPG_MOD 601>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 601>;};vspd3: vsp@fea38000 {compatible = "renesas,vsp2";reg = <0 0xfea38000 0 0x4000>;interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 620>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 620>;renesas,fcp = <&fcpvd3>;};fcpvd3: fcp@fea3f000 {compatible = "renesas,fcpv";reg = <0 0xfea3f000 0 0x200>;clocks = <&cpg CPG_MOD 600>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 600>;};fdp1@fe940000 {compatible = "renesas,fdp1";reg = <0 0xfe940000 0 0x2400>;interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 119>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 119>;renesas,fcp = <&fcpf0>;};fdp1@fe944000 {compatible = "renesas,fdp1";reg = <0 0xfe944000 0 0x2400>;interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 118>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 118>;renesas,fcp = <&fcpf1>;};fdp1@fe948000 {compatible = "renesas,fdp1";reg = <0 0xfe948000 0 0x2400>;interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 117>;power-domains = <&sysc R8A7795_PD_A3VP>;resets = <&cpg 117>;renesas,fcp = <&fcpf2>;};du: display@feb00000 {compatible = "renesas,du-r8a7795";reg = <0 0xfeb00000 0 0x80000>,<0 0xfeb90000 0 0x14>;reg-names = "du", "lvds.0";interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 724>,<&cpg CPG_MOD 723>,<&cpg CPG_MOD 722>,<&cpg CPG_MOD 721>,<&cpg CPG_MOD 727>;clock-names = "du.0", "du.1", "du.2", "du.3", "lvds.0";status = "disabled";vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;ports {#address-cells = <1>;#size-cells = <0>;port@0 {reg = <0>;du_out_rgb: endpoint {};};port@1 {reg = <1>;du_out_hdmi0: endpoint {};};port@2 {reg = <2>;du_out_hdmi1: endpoint {};};port@3 {reg = <3>;du_out_lvds0: endpoint {};};};};tsc: thermal@e6198000 {compatible = "renesas,r8a7795-thermal";reg = <0 0xe6198000 0 0x68>,<0 0xe61a0000 0 0x5c>,<0 0xe61a8000 0 0x5c>;interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 522>;power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;resets = <&cpg 522>;#thermal-sensor-cells = <1>;status = "okay";};thermal-zones {sensor_thermal1: sensor-thermal1 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 0>;trips {sensor1_crit: sensor1-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};sensor_thermal2: sensor-thermal2 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 1>;trips {sensor2_crit: sensor2-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};sensor_thermal3: sensor-thermal3 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 2>;trips {sensor3_crit: sensor3-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};};};+}; diff --git a/arch/arm/dts/r8a7796-m3ulcb.dts b/arch/arm/dts/r8a7796-m3ulcb.dts new file mode 100644 index 0000000000..372b2a9447 --- /dev/null +++ b/arch/arm/dts/r8a7796-m3ulcb.dts @@ -0,0 +1,188 @@ +/*
- Device Tree Source for the M3ULCB (R-Car Starter Kit Pro) board
- Copyright (C) 2016 Renesas Electronics Corp.
- Copyright (C) 2016 Cogent Embedded, Inc.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h>
+/ {
model = "Renesas M3ULCB board based on r8a7796";compatible = "renesas,m3ulcb", "renesas,r8a7796";aliases {serial0 = &scif2;};chosen {stdout-path = "serial0:115200n8";};memory@48000000 {device_type = "memory";/* first 128MB is reserved for secure area. */reg = <0x0 0x48000000 0x0 0x38000000>;};leds {compatible = "gpio-leds";led5 {gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;};led6 {gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;};};keyboard {compatible = "gpio-keys";key-1 {linux,code = <KEY_1>;label = "SW3";wakeup-source;debounce-interval = <20>;gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;};};reg_1p8v: regulator0 {compatible = "regulator-fixed";regulator-name = "fixed-1.8V";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-boot-on;regulator-always-on;};reg_3p3v: regulator1 {compatible = "regulator-fixed";regulator-name = "fixed-3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-boot-on;regulator-always-on;};vcc_sdhi0: regulator-vcc-sdhi0 {compatible = "regulator-fixed";regulator-name = "SDHI0 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi0: regulator-vccq-sdhi0 {compatible = "regulator-gpio";regulator-name = "SDHI0 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};+};
+&extal_clk {
clock-frequency = <16666666>;+};
+&extalr_clk {
clock-frequency = <32768>;+};
+&pfc {
pinctrl-0 = <&scif_clk_pins>;pinctrl-names = "default";scif2_pins: scif2 {groups = "scif2_data_a";function = "scif2";};scif_clk_pins: scif_clk {groups = "scif_clk_a";function = "scif_clk";};sdhi0_pins: sd0 {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <3300>;};sdhi0_pins_uhs: sd0_uhs {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <1800>;};sdhi2_pins: sd2 {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <3300>;};sdhi2_pins_uhs: sd2_uhs {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <1800>;};+};
+&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;pinctrl-1 = <&sdhi0_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi0>;vqmmc-supply = <&vccq_sdhi0>;cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&sdhi2 {
/* used for on-board 8bit eMMC */pinctrl-0 = <&sdhi2_pins>;pinctrl-1 = <&sdhi2_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <®_3p3v>;vqmmc-supply = <®_1p8v>;bus-width = <8>;non-removable;status = "okay";+};
+&scif2 {
pinctrl-0 = <&scif2_pins>;pinctrl-names = "default";status = "okay";+};
+&scif_clk {
clock-frequency = <14745600>;+};
+&wdt0 {
timeout-sec = <60>;status = "okay";+}; diff --git a/arch/arm/dts/r8a7796-salvator-x.dts b/arch/arm/dts/r8a7796-salvator-x.dts new file mode 100644 index 0000000000..c9f59b6ce3 --- /dev/null +++ b/arch/arm/dts/r8a7796-salvator-x.dts @@ -0,0 +1,269 @@ +/*
- Device Tree Source for the Salvator-X board
- Copyright (C) 2016 Renesas Electronics Corp.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+/dts-v1/; +#include "r8a7796.dtsi" +#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Renesas Salvator-X board based on r8a7796";compatible = "renesas,salvator-x", "renesas,r8a7796";aliases {serial0 = &scif2;serial1 = &scif1;ethernet0 = &avb;};chosen {bootargs = "ignore_loglevel";stdout-path = "serial0:115200n8";};memory@48000000 {device_type = "memory";/* first 128MB is reserved for secure area. */reg = <0x0 0x48000000 0x0 0x78000000>;};memory@600000000 {device_type = "memory";reg = <0x6 0x00000000 0x0 0x80000000>;};reg_1p8v: regulator0 {compatible = "regulator-fixed";regulator-name = "fixed-1.8V";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-boot-on;regulator-always-on;};reg_3p3v: regulator1 {compatible = "regulator-fixed";regulator-name = "fixed-3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-boot-on;regulator-always-on;};vcc_sdhi0: regulator-vcc-sdhi0 {compatible = "regulator-fixed";regulator-name = "SDHI0 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi0: regulator-vccq-sdhi0 {compatible = "regulator-gpio";regulator-name = "SDHI0 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};vcc_sdhi3: regulator-vcc-sdhi3 {compatible = "regulator-fixed";regulator-name = "SDHI3 Vcc";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;enable-active-high;};vccq_sdhi3: regulator-vccq-sdhi3 {compatible = "regulator-gpio";regulator-name = "SDHI3 VccQ";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <3300000>;gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;gpios-states = <1>;states = <3300000 11800000 0>;};+};
+&pfc {
pinctrl-0 = <&scif_clk_pins>;pinctrl-names = "default";avb_pins: avb {groups = "avb_mdc";function = "avb";};scif1_pins: scif1 {groups = "scif1_data_a", "scif1_ctrl";function = "scif1";};scif2_pins: scif2 {groups = "scif2_data_a";function = "scif2";};scif_clk_pins: scif_clk {groups = "scif_clk_a";function = "scif_clk";};i2c2_pins: i2c2 {groups = "i2c2_a";function = "i2c2";};sdhi0_pins: sd0 {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <3300>;};sdhi0_pins_uhs: sd0_uhs {groups = "sdhi0_data4", "sdhi0_ctrl";function = "sdhi0";power-source = <1800>;};sdhi2_pins: sd2 {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <3300>;};sdhi2_pins_uhs: sd2_uhs {groups = "sdhi2_data8", "sdhi2_ctrl";function = "sdhi2";power-source = <1800>;};sdhi3_pins: sd3 {groups = "sdhi3_data4", "sdhi3_ctrl";function = "sdhi3";power-source = <3300>;};sdhi3_pins_uhs: sd3_uhs {groups = "sdhi3_data4", "sdhi3_ctrl";function = "sdhi3";power-source = <1800>;};+};
+&avb {
pinctrl-0 = <&avb_pins>;pinctrl-names = "default";renesas,no-ether-link;phy-handle = <&phy0>;status = "okay";phy0: ethernet-phy@0 {rxc-skew-ps = <1500>;reg = <0>;interrupt-parent = <&gpio2>;interrupts = <11 IRQ_TYPE_LEVEL_LOW>;};+};
+&extal_clk {
clock-frequency = <16666666>;+};
+&extalr_clk {
clock-frequency = <32768>;+};
+&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;pinctrl-1 = <&sdhi0_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi0>;vqmmc-supply = <&vccq_sdhi0>;cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&sdhi2 {
/* used for on-board 8bit eMMC */pinctrl-0 = <&sdhi2_pins>;pinctrl-1 = <&sdhi2_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <®_3p3v>;vqmmc-supply = <®_1p8v>;bus-width = <8>;non-removable;status = "okay";+};
+&sdhi3 {
pinctrl-0 = <&sdhi3_pins>;pinctrl-1 = <&sdhi3_pins_uhs>;pinctrl-names = "default", "state_uhs";vmmc-supply = <&vcc_sdhi3>;vqmmc-supply = <&vccq_sdhi3>;cd-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;wp-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;bus-width = <4>;sd-uhs-sdr50;status = "okay";+};
+&scif1 {
pinctrl-0 = <&scif1_pins>;pinctrl-names = "default";uart-has-rtscts;status = "okay";+};
+&scif2 {
pinctrl-0 = <&scif2_pins>;pinctrl-names = "default";status = "okay";+};
+&scif_clk {
clock-frequency = <14745600>;+};
+&i2c2 {
pinctrl-0 = <&i2c2_pins>;pinctrl-names = "default";status = "okay";+};
+&wdt0 {
timeout-sec = <60>;status = "okay";+};
+&i2c_dvfs {
status = "okay";+}; diff --git a/arch/arm/dts/r8a7796.dtsi b/arch/arm/dts/r8a7796.dtsi new file mode 100644 index 0000000000..2ec1ed5f49 --- /dev/null +++ b/arch/arm/dts/r8a7796.dtsi @@ -0,0 +1,1037 @@ +/*
- Device Tree Source for the r8a7796 SoC
- Copyright (C) 2016 Renesas Electronics Corp.
- This file is licensed under the terms of the GNU General Public License
- version 2. This program is licensed "as is" without any warranty of any
- kind, whether express or implied.
- */
+#include <dt-bindings/clock/r8a7796-cpg-mssr.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/r8a7796-sysc.h>
+/ {
compatible = "renesas,r8a7796";#address-cells = <2>;#size-cells = <2>;aliases {i2c0 = &i2c0;i2c1 = &i2c1;i2c2 = &i2c2;i2c3 = &i2c3;i2c4 = &i2c4;i2c5 = &i2c5;i2c6 = &i2c6;i2c7 = &i2c_dvfs;};psci {compatible = "arm,psci-1.0", "arm,psci-0.2";method = "smc";};cpus {#address-cells = <1>;#size-cells = <0>;a57_0: cpu@0 {compatible = "arm,cortex-a57", "arm,armv8";reg = <0x0>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA57_CPU0>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a57_1: cpu@1 {compatible = "arm,cortex-a57","arm,armv8";reg = <0x1>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA57_CPU1>;next-level-cache = <&L2_CA57>;enable-method = "psci";};a53_0: cpu@100 {compatible = "arm,cortex-a53", "arm,armv8";reg = <0x100>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA53_CPU0>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_1: cpu@101 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x101>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA53_CPU1>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_2: cpu@102 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x102>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA53_CPU2>;next-level-cache = <&L2_CA53>;enable-method = "psci";};a53_3: cpu@103 {compatible = "arm,cortex-a53","arm,armv8";reg = <0x103>;device_type = "cpu";power-domains = <&sysc R8A7796_PD_CA53_CPU3>;next-level-cache = <&L2_CA53>;enable-method = "psci";};L2_CA57: cache-controller-0 {compatible = "cache";power-domains = <&sysc R8A7796_PD_CA57_SCU>;cache-unified;cache-level = <2>;};L2_CA53: cache-controller-1 {compatible = "cache";power-domains = <&sysc R8A7796_PD_CA53_SCU>;cache-unified;cache-level = <2>;};};extal_clk: extal {compatible = "fixed-clock";#clock-cells = <0>;/* This value must be overridden by the board */clock-frequency = <0>;};extalr_clk: extalr {compatible = "fixed-clock";#clock-cells = <0>;/* This value must be overridden by the board */clock-frequency = <0>;};/* External CAN clock - to be overridden by boards that provide it */can_clk: can {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};/* External SCIF clock - to be overridden by boards that provide it */scif_clk: scif {compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <0>;};soc {compatible = "simple-bus";interrupt-parent = <&gic>;#address-cells = <2>;#size-cells = <2>;ranges;gic: interrupt-controller@f1010000 {compatible = "arm,gic-400";#interrupt-cells = <3>;#address-cells = <0>;interrupt-controller;reg = <0x0 0xf1010000 0 0x1000>,<0x0 0xf1020000 0 0x20000>,<0x0 0xf1040000 0 0x20000>,<0x0 0xf1060000 0 0x20000>;interrupts = <GIC_PPI 9(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;clocks = <&cpg CPG_MOD 408>;clock-names = "clk";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 408>;};timer {compatible = "arm,armv8-timer";interrupts = <GIC_PPI 13(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 14(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 11(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,<GIC_PPI 10(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;};wdt0: watchdog@e6020000 {compatible = "renesas,r8a7796-wdt","renesas,rcar-gen3-wdt";reg = <0 0xe6020000 0 0x0c>;clocks = <&cpg CPG_MOD 402>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 402>;status = "disabled";};gpio0: gpio@e6050000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6050000 0 0x50>;interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 0 16>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 912>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 912>;};gpio1: gpio@e6051000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6051000 0 0x50>;interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 32 29>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 911>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 911>;};gpio2: gpio@e6052000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6052000 0 0x50>;interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 64 15>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 910>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 910>;};gpio3: gpio@e6053000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6053000 0 0x50>;interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 96 16>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 909>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 909>;};gpio4: gpio@e6054000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6054000 0 0x50>;interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 128 18>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 908>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 908>;};gpio5: gpio@e6055000 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6055000 0 0x50>;interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 160 26>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 907>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 907>;};gpio6: gpio@e6055400 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6055400 0 0x50>;interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 192 32>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 906>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 906>;};gpio7: gpio@e6055800 {compatible = "renesas,gpio-r8a7796","renesas,gpio-rcar";reg = <0 0xe6055800 0 0x50>;interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;#gpio-cells = <2>;gpio-controller;gpio-ranges = <&pfc 0 224 4>;#interrupt-cells = <2>;interrupt-controller;clocks = <&cpg CPG_MOD 905>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 905>;};pfc: pin-controller@e6060000 {compatible = "renesas,pfc-r8a7796";reg = <0 0xe6060000 0 0x50c>;};pmu_a57 {compatible = "arm,cortex-a57-pmu";interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;interrupt-affinity = <&a57_0>,<&a57_1>;};pmu_a53 {compatible = "arm,cortex-a53-pmu";interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;interrupt-affinity = <&a53_0>,<&a53_1>,<&a53_2>,<&a53_3>;};cpg: clock-controller@e6150000 {compatible = "renesas,r8a7796-cpg-mssr";reg = <0 0xe6150000 0 0x1000>;clocks = <&extal_clk>, <&extalr_clk>;clock-names = "extal", "extalr";#clock-cells = <2>;#power-domain-cells = <0>;#reset-cells = <1>;};rst: reset-controller@e6160000 {compatible = "renesas,r8a7796-rst";reg = <0 0xe6160000 0 0x0200>;};prr: chipid@fff00044 {compatible = "renesas,prr";reg = <0 0xfff00044 0 4>;};sysc: system-controller@e6180000 {compatible = "renesas,r8a7796-sysc";reg = <0 0xe6180000 0 0x0400>;#power-domain-cells = <1>;};i2c_dvfs: i2c@e60b0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,iic-r8a7796","renesas,rcar-gen3-iic","renesas,rmobile-iic";reg = <0 0xe60b0000 0 0x425>;interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 926>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 926>;status = "disabled";};i2c0: i2c@e6500000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe6500000 0 0x40>;interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 931>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 931>;dmas = <&dmac1 0x91>, <&dmac1 0x90>,<&dmac2 0x91>, <&dmac2 0x90>;dma-names = "tx", "rx", "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c1: i2c@e6508000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe6508000 0 0x40>;interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 930>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 930>;dmas = <&dmac1 0x93>, <&dmac1 0x92>,<&dmac2 0x93>, <&dmac2 0x92>;dma-names = "tx", "rx", "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};i2c2: i2c@e6510000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe6510000 0 0x40>;interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 929>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 929>;dmas = <&dmac1 0x95>, <&dmac1 0x94>,<&dmac2 0x95>, <&dmac2 0x94>;dma-names = "tx", "rx", "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};i2c3: i2c@e66d0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe66d0000 0 0x40>;interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 928>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 928>;dmas = <&dmac0 0x97>, <&dmac0 0x96>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c4: i2c@e66d8000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe66d8000 0 0x40>;interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 927>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 927>;dmas = <&dmac0 0x99>, <&dmac0 0x98>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c5: i2c@e66e0000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe66e0000 0 0x40>;interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 919>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 919>;dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <110>;status = "disabled";};i2c6: i2c@e66e8000 {#address-cells = <1>;#size-cells = <0>;compatible = "renesas,i2c-r8a7796","renesas,rcar-gen3-i2c";reg = <0 0xe66e8000 0 0x40>;interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 918>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 918>;dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;dma-names = "tx", "rx";i2c-scl-internal-delay-ns = <6>;status = "disabled";};can0: can@e6c30000 {compatible = "renesas,can-r8a7796","renesas,rcar-gen3-can";reg = <0 0xe6c30000 0 0x1000>;interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 916>,<&cpg CPG_CORE R8A7796_CLK_CANFD>,<&can_clk>;clock-names = "clkp1", "clkp2", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 916>;status = "disabled";};can1: can@e6c38000 {compatible = "renesas,can-r8a7796","renesas,rcar-gen3-can";reg = <0 0xe6c38000 0 0x1000>;interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 915>,<&cpg CPG_CORE R8A7796_CLK_CANFD>,<&can_clk>;clock-names = "clkp1", "clkp2", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 915>;status = "disabled";};canfd: can@e66c0000 {compatible = "renesas,r8a7796-canfd","renesas,rcar-gen3-canfd";reg = <0 0xe66c0000 0 0x8000>;interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 914>,<&cpg CPG_CORE R8A7796_CLK_CANFD>,<&can_clk>;clock-names = "fck", "canfd", "can_clk";assigned-clocks = <&cpg CPG_CORE R8A7796_CLK_CANFD>;assigned-clock-rates = <40000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 914>;status = "disabled";channel0 {status = "disabled";};channel1 {status = "disabled";};};avb: ethernet@e6800000 {compatible = "renesas,etheravb-r8a7796","renesas,etheravb-rcar-gen3";reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15","ch16", "ch17", "ch18", "ch19","ch20", "ch21", "ch22", "ch23","ch24";clocks = <&cpg CPG_MOD 812>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 812>;phy-mode = "rgmii-txid";#address-cells = <1>;#size-cells = <0>;status = "disabled";};hscif0: serial@e6540000 {compatible = "renesas,hscif-r8a7796","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6540000 0 0x60>;interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 520>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x31>, <&dmac1 0x30>,<&dmac2 0x31>, <&dmac2 0x30>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 520>;status = "disabled";};hscif1: serial@e6550000 {compatible = "renesas,hscif-r8a7796","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6550000 0 0x60>;interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 519>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x33>, <&dmac1 0x32>,<&dmac2 0x33>, <&dmac2 0x32>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 519>;status = "disabled";};hscif2: serial@e6560000 {compatible = "renesas,hscif-r8a7796","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe6560000 0 0x60>;interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 518>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x35>, <&dmac1 0x34>,<&dmac2 0x35>, <&dmac2 0x34>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 518>;status = "disabled";};hscif3: serial@e66a0000 {compatible = "renesas,hscif-r8a7796","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe66a0000 0 0x60>;interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 517>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x37>, <&dmac0 0x36>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 517>;status = "disabled";};hscif4: serial@e66b0000 {compatible = "renesas,hscif-r8a7796","renesas,rcar-gen3-hscif","renesas,hscif";reg = <0 0xe66b0000 0 0x60>;interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 516>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x39>, <&dmac0 0x38>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 516>;status = "disabled";};scif0: serial@e6e60000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e60000 0 64>;interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 207>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x51>, <&dmac1 0x50>,<&dmac2 0x51>, <&dmac2 0x50>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 207>;status = "disabled";};scif1: serial@e6e68000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e68000 0 64>;interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 206>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x53>, <&dmac1 0x52>,<&dmac2 0x53>, <&dmac2 0x52>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 206>;status = "disabled";};scif2: serial@e6e88000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6e88000 0 64>;interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 310>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 310>;status = "disabled";};scif3: serial@e6c50000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6c50000 0 64>;interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 204>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x57>, <&dmac0 0x56>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 204>;status = "disabled";};scif4: serial@e6c40000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6c40000 0 64>;interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 203>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac0 0x59>, <&dmac0 0x58>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 203>;status = "disabled";};scif5: serial@e6f30000 {compatible = "renesas,scif-r8a7796","renesas,rcar-gen3-scif", "renesas,scif";reg = <0 0xe6f30000 0 64>;interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 202>,<&cpg CPG_CORE R8A7796_CLK_S3D1>,<&scif_clk>;clock-names = "fck", "brg_int", "scif_clk";dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,<&dmac2 0x5b>, <&dmac2 0x5a>;dma-names = "tx", "rx", "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 202>;status = "disabled";};msiof0: spi@e6e90000 {compatible = "renesas,msiof-r8a7796","renesas,rcar-gen3-msiof";reg = <0 0xe6e90000 0 0x0064>;interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 211>;dmas = <&dmac1 0x41>, <&dmac1 0x40>,<&dmac2 0x41>, <&dmac2 0x40>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 211>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};msiof1: spi@e6ea0000 {compatible = "renesas,msiof-r8a7796","renesas,rcar-gen3-msiof";reg = <0 0xe6ea0000 0 0x0064>;interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 210>;dmas = <&dmac1 0x43>, <&dmac1 0x42>,<&dmac2 0x43>, <&dmac2 0x42>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 210>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};msiof2: spi@e6c00000 {compatible = "renesas,msiof-r8a7796","renesas,rcar-gen3-msiof";reg = <0 0xe6c00000 0 0x0064>;interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 209>;dmas = <&dmac0 0x45>, <&dmac0 0x44>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 209>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};msiof3: spi@e6c10000 {compatible = "renesas,msiof-r8a7796","renesas,rcar-gen3-msiof";reg = <0 0xe6c10000 0 0x0064>;interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 208>;dmas = <&dmac0 0x47>, <&dmac0 0x46>;dma-names = "tx", "rx";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 208>;#address-cells = <1>;#size-cells = <0>;status = "disabled";};dmac0: dma-controller@e6700000 {compatible = "renesas,dmac-r8a7796","renesas,rcar-dmac";reg = <0 0xe6700000 0 0x10000>;interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGHGIC_SPI 200 IRQ_TYPE_LEVEL_HIGHGIC_SPI 201 IRQ_TYPE_LEVEL_HIGHGIC_SPI 202 IRQ_TYPE_LEVEL_HIGHGIC_SPI 203 IRQ_TYPE_LEVEL_HIGHGIC_SPI 204 IRQ_TYPE_LEVEL_HIGHGIC_SPI 205 IRQ_TYPE_LEVEL_HIGHGIC_SPI 206 IRQ_TYPE_LEVEL_HIGHGIC_SPI 207 IRQ_TYPE_LEVEL_HIGHGIC_SPI 208 IRQ_TYPE_LEVEL_HIGHGIC_SPI 209 IRQ_TYPE_LEVEL_HIGHGIC_SPI 210 IRQ_TYPE_LEVEL_HIGHGIC_SPI 211 IRQ_TYPE_LEVEL_HIGHGIC_SPI 212 IRQ_TYPE_LEVEL_HIGHGIC_SPI 213 IRQ_TYPE_LEVEL_HIGHGIC_SPI 214 IRQ_TYPE_LEVEL_HIGHGIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 219>;clock-names = "fck";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 219>;#dma-cells = <1>;dma-channels = <16>;};dmac1: dma-controller@e7300000 {compatible = "renesas,dmac-r8a7796","renesas,rcar-dmac";reg = <0 0xe7300000 0 0x10000>;interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGHGIC_SPI 216 IRQ_TYPE_LEVEL_HIGHGIC_SPI 217 IRQ_TYPE_LEVEL_HIGHGIC_SPI 218 IRQ_TYPE_LEVEL_HIGHGIC_SPI 219 IRQ_TYPE_LEVEL_HIGHGIC_SPI 308 IRQ_TYPE_LEVEL_HIGHGIC_SPI 309 IRQ_TYPE_LEVEL_HIGHGIC_SPI 310 IRQ_TYPE_LEVEL_HIGHGIC_SPI 311 IRQ_TYPE_LEVEL_HIGHGIC_SPI 312 IRQ_TYPE_LEVEL_HIGHGIC_SPI 313 IRQ_TYPE_LEVEL_HIGHGIC_SPI 314 IRQ_TYPE_LEVEL_HIGHGIC_SPI 315 IRQ_TYPE_LEVEL_HIGHGIC_SPI 316 IRQ_TYPE_LEVEL_HIGHGIC_SPI 317 IRQ_TYPE_LEVEL_HIGHGIC_SPI 318 IRQ_TYPE_LEVEL_HIGHGIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 218>;clock-names = "fck";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 218>;#dma-cells = <1>;dma-channels = <16>;};dmac2: dma-controller@e7310000 {compatible = "renesas,dmac-r8a7796","renesas,rcar-dmac";reg = <0 0xe7310000 0 0x10000>;interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGHGIC_SPI 417 IRQ_TYPE_LEVEL_HIGHGIC_SPI 418 IRQ_TYPE_LEVEL_HIGHGIC_SPI 419 IRQ_TYPE_LEVEL_HIGHGIC_SPI 420 IRQ_TYPE_LEVEL_HIGHGIC_SPI 421 IRQ_TYPE_LEVEL_HIGHGIC_SPI 422 IRQ_TYPE_LEVEL_HIGHGIC_SPI 423 IRQ_TYPE_LEVEL_HIGHGIC_SPI 424 IRQ_TYPE_LEVEL_HIGHGIC_SPI 425 IRQ_TYPE_LEVEL_HIGHGIC_SPI 426 IRQ_TYPE_LEVEL_HIGHGIC_SPI 427 IRQ_TYPE_LEVEL_HIGHGIC_SPI 428 IRQ_TYPE_LEVEL_HIGHGIC_SPI 429 IRQ_TYPE_LEVEL_HIGHGIC_SPI 430 IRQ_TYPE_LEVEL_HIGHGIC_SPI 431 IRQ_TYPE_LEVEL_HIGHGIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "error","ch0", "ch1", "ch2", "ch3","ch4", "ch5", "ch6", "ch7","ch8", "ch9", "ch10", "ch11","ch12", "ch13", "ch14", "ch15";clocks = <&cpg CPG_MOD 217>;clock-names = "fck";power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 217>;#dma-cells = <1>;dma-channels = <16>;};sdhi0: sd@ee100000 {compatible = "renesas,sdhi-r8a7796";reg = <0 0xee100000 0 0x2000>;interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 314>;max-frequency = <200000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 314>;status = "disabled";};sdhi1: sd@ee120000 {compatible = "renesas,sdhi-r8a7796";reg = <0 0xee120000 0 0x2000>;interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 313>;max-frequency = <200000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 313>;status = "disabled";};sdhi2: sd@ee140000 {compatible = "renesas,sdhi-r8a7796";reg = <0 0xee140000 0 0x2000>;interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 312>;max-frequency = <200000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 312>;status = "disabled";};sdhi3: sd@ee160000 {compatible = "renesas,sdhi-r8a7796";reg = <0 0xee160000 0 0x2000>;interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 311>;max-frequency = <200000000>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 311>;status = "disabled";};tsc: thermal@e6198000 {compatible = "renesas,r8a7796-thermal";reg = <0 0xe6198000 0 0x68>,<0 0xe61a0000 0 0x5c>,<0 0xe61a8000 0 0x5c>;interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;clocks = <&cpg CPG_MOD 522>;power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;resets = <&cpg 522>;#thermal-sensor-cells = <1>;status = "okay";};thermal-zones {sensor_thermal1: sensor-thermal1 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 0>;trips {sensor1_crit: sensor1-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};sensor_thermal2: sensor-thermal2 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 1>;trips {sensor2_crit: sensor2-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};sensor_thermal3: sensor-thermal3 {polling-delay-passive = <250>;polling-delay = <1000>;thermal-sensors = <&tsc 2>;trips {sensor3_crit: sensor3-crit {temperature = <120000>;hysteresis = <2000>;type = "critical";};};};};};+}; diff --git a/include/dt-bindings/clock/r8a7795-cpg-mssr.h b/include/dt-bindings/clock/r8a7795-cpg-mssr.h new file mode 100644 index 0000000000..f047eaf261 --- /dev/null +++ b/include/dt-bindings/clock/r8a7795-cpg-mssr.h @@ -0,0 +1,70 @@ +/*
- Copyright (C) 2015 Renesas Electronics Corp.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#ifndef __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+/* r8a7795 CPG Core Clocks */ +#define R8A7795_CLK_Z 0 +#define R8A7795_CLK_Z2 1 +#define R8A7795_CLK_ZR 2 +#define R8A7795_CLK_ZG 3 +#define R8A7795_CLK_ZTR 4 +#define R8A7795_CLK_ZTRD2 5 +#define R8A7795_CLK_ZT 6 +#define R8A7795_CLK_ZX 7 +#define R8A7795_CLK_S0D1 8 +#define R8A7795_CLK_S0D4 9 +#define R8A7795_CLK_S1D1 10 +#define R8A7795_CLK_S1D2 11 +#define R8A7795_CLK_S1D4 12 +#define R8A7795_CLK_S2D1 13 +#define R8A7795_CLK_S2D2 14 +#define R8A7795_CLK_S2D4 15 +#define R8A7795_CLK_S3D1 16 +#define R8A7795_CLK_S3D2 17 +#define R8A7795_CLK_S3D4 18 +#define R8A7795_CLK_LB 19 +#define R8A7795_CLK_CL 20 +#define R8A7795_CLK_ZB3 21 +#define R8A7795_CLK_ZB3D2 22 +#define R8A7795_CLK_CR 23 +#define R8A7795_CLK_CRD2 24 +#define R8A7795_CLK_SD0H 25 +#define R8A7795_CLK_SD0 26 +#define R8A7795_CLK_SD1H 27 +#define R8A7795_CLK_SD1 28 +#define R8A7795_CLK_SD2H 29 +#define R8A7795_CLK_SD2 30 +#define R8A7795_CLK_SD3H 31 +#define R8A7795_CLK_SD3 32 +#define R8A7795_CLK_SSP2 33 +#define R8A7795_CLK_SSP1 34 +#define R8A7795_CLK_SSPRS 35 +#define R8A7795_CLK_RPC 36 +#define R8A7795_CLK_RPCD2 37 +#define R8A7795_CLK_MSO 38 +#define R8A7795_CLK_CANFD 39 +#define R8A7795_CLK_HDMI 40 +#define R8A7795_CLK_CSI0 41 +#define R8A7795_CLK_CSIREF 42 +#define R8A7795_CLK_CP 43 +#define R8A7795_CLK_CPEX 44 +#define R8A7795_CLK_R 45 +#define R8A7795_CLK_OSC 46
+/* r8a7795 ES2.0 CPG Core Clocks */ +#define R8A7795_CLK_S0D2 47 +#define R8A7795_CLK_S0D3 48 +#define R8A7795_CLK_S0D6 49 +#define R8A7795_CLK_S0D8 50 +#define R8A7795_CLK_S0D12 51
+#endif /* __DT_BINDINGS_CLOCK_R8A7795_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/r8a7796-cpg-mssr.h b/include/dt-bindings/clock/r8a7796-cpg-mssr.h new file mode 100644 index 0000000000..1e5942695f --- /dev/null +++ b/include/dt-bindings/clock/r8a7796-cpg-mssr.h @@ -0,0 +1,69 @@ +/*
- Copyright (C) 2016 Renesas Electronics Corp.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#ifndef __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__
+#include <dt-bindings/clock/renesas-cpg-mssr.h>
+/* r8a7796 CPG Core Clocks */ +#define R8A7796_CLK_Z 0 +#define R8A7796_CLK_Z2 1 +#define R8A7796_CLK_ZR 2 +#define R8A7796_CLK_ZG 3 +#define R8A7796_CLK_ZTR 4 +#define R8A7796_CLK_ZTRD2 5 +#define R8A7796_CLK_ZT 6 +#define R8A7796_CLK_ZX 7 +#define R8A7796_CLK_S0D1 8 +#define R8A7796_CLK_S0D2 9 +#define R8A7796_CLK_S0D3 10 +#define R8A7796_CLK_S0D4 11 +#define R8A7796_CLK_S0D6 12 +#define R8A7796_CLK_S0D8 13 +#define R8A7796_CLK_S0D12 14 +#define R8A7796_CLK_S1D1 15 +#define R8A7796_CLK_S1D2 16 +#define R8A7796_CLK_S1D4 17 +#define R8A7796_CLK_S2D1 18 +#define R8A7796_CLK_S2D2 19 +#define R8A7796_CLK_S2D4 20 +#define R8A7796_CLK_S3D1 21 +#define R8A7796_CLK_S3D2 22 +#define R8A7796_CLK_S3D4 23 +#define R8A7796_CLK_LB 24 +#define R8A7796_CLK_CL 25 +#define R8A7796_CLK_ZB3 26 +#define R8A7796_CLK_ZB3D2 27 +#define R8A7796_CLK_ZB3D4 28 +#define R8A7796_CLK_CR 29 +#define R8A7796_CLK_CRD2 30 +#define R8A7796_CLK_SD0H 31 +#define R8A7796_CLK_SD0 32 +#define R8A7796_CLK_SD1H 33 +#define R8A7796_CLK_SD1 34 +#define R8A7796_CLK_SD2H 35 +#define R8A7796_CLK_SD2 36 +#define R8A7796_CLK_SD3H 37 +#define R8A7796_CLK_SD3 38 +#define R8A7796_CLK_SSP2 39 +#define R8A7796_CLK_SSP1 40 +#define R8A7796_CLK_SSPRS 41 +#define R8A7796_CLK_RPC 42 +#define R8A7796_CLK_RPCD2 43 +#define R8A7796_CLK_MSO 44 +#define R8A7796_CLK_CANFD 45 +#define R8A7796_CLK_HDMI 46 +#define R8A7796_CLK_CSI0 47 +#define R8A7796_CLK_CSIREF 48 +#define R8A7796_CLK_CP 49 +#define R8A7796_CLK_CPEX 50 +#define R8A7796_CLK_R 51 +#define R8A7796_CLK_OSC 52
+#endif /* __DT_BINDINGS_CLOCK_R8A7796_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/clock/renesas-cpg-mssr.h b/include/dt-bindings/clock/renesas-cpg-mssr.h new file mode 100644 index 0000000000..569a3cc33f --- /dev/null +++ b/include/dt-bindings/clock/renesas-cpg-mssr.h @@ -0,0 +1,15 @@ +/*
- Copyright (C) 2015 Renesas Electronics Corp.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
- */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__
+#define CPG_CORE 0 /* Core Clock */ +#define CPG_MOD 1 /* Module Clock */
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_CPG_MSSR_H__ */ diff --git a/include/dt-bindings/power/r8a7795-sysc.h b/include/dt-bindings/power/r8a7795-sysc.h new file mode 100644 index 0000000000..ad679eeda1 --- /dev/null +++ b/include/dt-bindings/power/r8a7795-sysc.h @@ -0,0 +1,42 @@ +/*
- Copyright (C) 2016 Glider bvba
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; version 2 of the License.
- */
+#ifndef __DT_BINDINGS_POWER_R8A7795_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7795_SYSC_H__
+/*
- These power domain indices match the numbers of the interrupt bits
- representing the power areas in the various Interrupt Registers
- (e.g. SYSCISR, Interrupt Status Register)
- */
+#define R8A7795_PD_CA57_CPU0 0 +#define R8A7795_PD_CA57_CPU1 1 +#define R8A7795_PD_CA57_CPU2 2 +#define R8A7795_PD_CA57_CPU3 3 +#define R8A7795_PD_CA53_CPU0 5 +#define R8A7795_PD_CA53_CPU1 6 +#define R8A7795_PD_CA53_CPU2 7 +#define R8A7795_PD_CA53_CPU3 8 +#define R8A7795_PD_A3VP 9 +#define R8A7795_PD_CA57_SCU 12 +#define R8A7795_PD_CR7 13 +#define R8A7795_PD_A3VC 14 +#define R8A7795_PD_3DG_A 17 +#define R8A7795_PD_3DG_B 18 +#define R8A7795_PD_3DG_C 19 +#define R8A7795_PD_3DG_D 20 +#define R8A7795_PD_CA53_SCU 21 +#define R8A7795_PD_3DG_E 22 +#define R8A7795_PD_A3IR 24 +#define R8A7795_PD_A2VC0 25 /* ES1.x only */ +#define R8A7795_PD_A2VC1 26
+/* Always-on power area */ +#define R8A7795_PD_ALWAYS_ON 32
+#endif /* __DT_BINDINGS_POWER_R8A7795_SYSC_H__ */ diff --git a/include/dt-bindings/power/r8a7796-sysc.h b/include/dt-bindings/power/r8a7796-sysc.h new file mode 100644 index 0000000000..5b4daab44d --- /dev/null +++ b/include/dt-bindings/power/r8a7796-sysc.h @@ -0,0 +1,36 @@ +/*
- Copyright (C) 2016 Glider bvba
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; version 2 of the License.
- */
+#ifndef __DT_BINDINGS_POWER_R8A7796_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A7796_SYSC_H__
+/*
- These power domain indices match the numbers of the interrupt bits
- representing the power areas in the various Interrupt Registers
- (e.g. SYSCISR, Interrupt Status Register)
- */
+#define R8A7796_PD_CA57_CPU0 0 +#define R8A7796_PD_CA57_CPU1 1 +#define R8A7796_PD_CA53_CPU0 5 +#define R8A7796_PD_CA53_CPU1 6 +#define R8A7796_PD_CA53_CPU2 7 +#define R8A7796_PD_CA53_CPU3 8 +#define R8A7796_PD_CA57_SCU 12 +#define R8A7796_PD_CR7 13 +#define R8A7796_PD_A3VC 14 +#define R8A7796_PD_3DG_A 17 +#define R8A7796_PD_3DG_B 18 +#define R8A7796_PD_CA53_SCU 21 +#define R8A7796_PD_A3IR 24 +#define R8A7796_PD_A2VC0 25 +#define R8A7796_PD_A2VC1 26
+/* Always-on power area */ +#define R8A7796_PD_ALWAYS_ON 32
+#endif /* __DT_BINDINGS_POWER_R8A7796_SYSC_H__ */
2.11.0
participants (2)
-
Marek Vasut -
Nobuhiro Iwamatsu