[U-Boot] [PATCH] arm: socfpga: set the mpuclk divider in the Altera group register
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Signed-off-by: Dinh Nguyen dinguyen@kernel.org --- arch/arm/mach-socfpga/clock_manager.c | 3 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++ arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++ 3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..29e18f8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg) /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
+ /* altera group mpuclk */ + writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); + /* main main clock */ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 2675951..803c926 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -55,6 +55,9 @@ struct cm_config { uint32_t ddr2xdqsclk; uint32_t ddrdqclk; uint32_t s2fuser2clk; + + /* altera group */ + uint32_t altera_grp_mpuclk; };
void cm_basic_init(const struct cm_config * const cfg); diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET), + + /* altera group */ + CONFIG_HPS_ALTERAGRP_MPUCLK, };
const struct cm_config * const cm_get_default_config(void)
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Signed-off-by: Dinh Nguyen dinguyen@kernel.org
Reviewed-by: Marek Vasut marex@denx.de
That's real neat, does that mean we get up to twice as much performance?
arch/arm/mach-socfpga/clock_manager.c | 3 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++ arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++ 3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..29e18f8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg) /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
- /* altera group mpuclk */
- writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
- /* main main clock */ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 2675951..803c926 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -55,6 +55,9 @@ struct cm_config { uint32_t ddr2xdqsclk; uint32_t ddrdqclk; uint32_t s2fuser2clk;
- /* altera group */
- uint32_t altera_grp_mpuclk;
};
void cm_basic_init(const struct cm_config * const cfg); diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
- /* altera group */
- CONFIG_HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
It'd still be great to have people test it, so I added some more people to CC.
Signed-off-by: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/clock_manager.c | 3 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++ arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++ 3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..29e18f8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg) /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
- /* altera group mpuclk */
- writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
- /* main main clock */ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 2675951..803c926 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -55,6 +55,9 @@ struct cm_config { uint32_t ddr2xdqsclk; uint32_t ddrdqclk; uint32_t s2fuser2clk;
- /* altera group */
- uint32_t altera_grp_mpuclk;
};
void cm_basic_init(const struct cm_config * const cfg); diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
- /* altera group */
- CONFIG_HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
It'd still be great to have people test it, so I added some more people to CC.
Signed-off-by: Dinh Nguyen dinguyen@kernel.org
arch/arm/mach-socfpga/clock_manager.c | 3 +++ arch/arm/mach-socfpga/include/mach/clock_manager.h | 3 +++ arch/arm/mach-socfpga/wrap_pll_config.c | 3 +++ 3 files changed, 9 insertions(+)
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index aa71636..29e18f8 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -167,6 +167,9 @@ void cm_basic_init(const struct cm_config * const cfg) /* main mpu */ writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
- /* altera group mpuclk */
- writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk);
- /* main main clock */ writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index 2675951..803c926 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -55,6 +55,9 @@ struct cm_config { uint32_t ddr2xdqsclk; uint32_t ddrdqclk; uint32_t s2fuser2clk;
- /* altera group */
- uint32_t altera_grp_mpuclk;
};
void cm_basic_init(const struct cm_config * const cfg); diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index 8a0a0e6..72b5f92 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -116,6 +116,9 @@ static const struct cm_config cm_default_cfg = { CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
- /* altera group */
- CONFIG_HPS_ALTERAGRP_MPUCLK,
};
const struct cm_config * const cm_get_default_config(void)
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Dinh
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Cool, thanks for confirming. Maybe I should get it into 2017.03 release? What do you think ?
On 02/08/2017 03:04 PM, Marek Vasut wrote:
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Cool, thanks for confirming. Maybe I should get it into 2017.03 release? What do you think ?
Yes, I think the earlier the better.
Thanks, Dinh
On 02/08/2017 11:51 PM, Dinh Nguyen wrote:
On 02/08/2017 03:04 PM, Marek Vasut wrote:
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote:
The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll.
Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Cool, thanks for confirming. Maybe I should get it into 2017.03 release? What do you think ?
Yes, I think the earlier the better.
OK fine. Done.
On Wed, Feb 8, 2017 at 5:23 PM, Marek Vasut marex@denx.de wrote:
On 02/08/2017 11:51 PM, Dinh Nguyen wrote:
On 02/08/2017 03:04 PM, Marek Vasut wrote:
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote:
On 01/31/2017 07:33 PM, Dinh Nguyen wrote: > The mpuclk register in the Altera group of the clock manager > divides the mpu_clk that is generated from the C0 output of the main > pll. > > Without this patch, the default value of the register is 1, so the mpuclk > will always get divided by 2 if the correct value is not set. For example, > on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be > 1.05 GHz.
Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and I'd rather be a bit careful here. Is my assumption correct that until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Cool, thanks for confirming. Maybe I should get it into 2017.03 release? What do you think ?
Yes, I think the earlier the better.
OK fine. Done.
Thanks!
Pretty simple test:
time dd if=/dev/urandom of=/dev/null bs=1M count=500
with patch ~11 seconds, without patch ~22 seconds.
Dinh
On 02/09/2017 04:29 AM, Dinh Nguyen wrote:
On Wed, Feb 8, 2017 at 5:23 PM, Marek Vasut marex@denx.de wrote:
On 02/08/2017 11:51 PM, Dinh Nguyen wrote:
On 02/08/2017 03:04 PM, Marek Vasut wrote:
On 02/08/2017 06:59 PM, Dinh Nguyen wrote:
On 02/07/2017 07:32 PM, Marek Vasut wrote:
On 02/08/2017 02:21 AM, Marek Vasut wrote: > On 01/31/2017 07:33 PM, Dinh Nguyen wrote: >> The mpuclk register in the Altera group of the clock manager >> divides the mpu_clk that is generated from the C0 output of the main >> pll. >> >> Without this patch, the default value of the register is 1, so the mpuclk >> will always get divided by 2 if the correct value is not set. For example, >> on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be >> 1.05 GHz. > > Applied to u-boot-socfpga/next (so for 2017.05), as the MW is closed and > I'd rather be a bit careful here. Is my assumption correct that > until now, the performance of the CPU in both C/V and A/V was halved?
Hm in fact, it is already zero on C/V (I just checked) , so this seems to be A/V specific ?
Yes, that's correct. It's A/V specific. But patch is good for all C/V as well. For the C/V devices, it numerator for the MPU clock is higher, so dividing by 2 put the mpuclk ~1GHz. But for A/V, dividing by 2 puts the clock at 525MHz. Pretty slow.
Cool, thanks for confirming. Maybe I should get it into 2017.03 release? What do you think ?
Yes, I think the earlier the better.
OK fine. Done.
Thanks!
Pretty simple test:
time dd if=/dev/urandom of=/dev/null bs=1M count=500
with patch ~11 seconds, without patch ~22 seconds.
Hehe, that's an interesting way to test CPU speed :)
participants (3)
-
Dinh Nguyen -
Dinh Nguyen -
Marek Vasut