[RFC] rockchip: spl: Enable caches to speed up checksum validation
FIT checksum validation is very slow in SPL due to D-cache not being enabled.
Enable caches in SPL to speed up FIT checksum validation, from seconds to milliseconds.
Signed-off-by: Jonas Karlman jonas@kwiboo.se --- I am not sure if it is even a good idea to enable caches in SPL, if this is the best way to enable caches and maybe this should be behind a Kconfig option?
Have only been able to runtime test this on RK3328, RK3399 and RK3568.
Any advice on this would be grateful.
Regards, Jonas
arch/arm/mach-rockchip/spl.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-rockchip/spl.c b/arch/arm/mach-rockchip/spl.c index 30be64042521..29fe3353105b 100644 --- a/arch/arm/mach-rockchip/spl.c +++ b/arch/arm/mach-rockchip/spl.c @@ -149,6 +149,10 @@ void board_init_f(ulong dummy) } gd->ram_top = gd->ram_base + get_effective_memsize(); gd->ram_top = board_get_usable_ram_top(gd->ram_size); + gd->relocaddr = gd->ram_top; + + arch_reserve_mmu(); + enable_caches(); #endif preloader_console_init(); }
On Sun, Jul 2, 2023 at 4:31 PM Jonas Karlman jonas@kwiboo.se wrote:
FIT checksum validation is very slow in SPL due to D-cache not being enabled.
Enable caches in SPL to speed up FIT checksum validation, from seconds to milliseconds.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
I am not sure if it is even a good idea to enable caches in SPL, if this is the best way to enable caches and maybe this should be behind a Kconfig option?
It would. I would suggest giving board options instead of marking them for SoC.
Be careful to proceed with this to make it default, as it affects other drivers as well.
Jagan.
On 2023-07-02 13:07, Jagan Teki wrote:
On Sun, Jul 2, 2023 at 4:31 PM Jonas Karlman jonas@kwiboo.se wrote:
FIT checksum validation is very slow in SPL due to D-cache not being enabled.
Enable caches in SPL to speed up FIT checksum validation, from seconds to milliseconds.
Signed-off-by: Jonas Karlman jonas@kwiboo.se
I am not sure if it is even a good idea to enable caches in SPL, if this is the best way to enable caches and maybe this should be behind a Kconfig option?
It would. I would suggest giving board options instead of marking them for SoC.
There is already SPL_SYS_ICACHE_OFF and SPL_SYS_DCACHE_OFF that can be used by board/SoC to disable I/D-cache in SPL/U-Boot proper, those are however opt-out instead of opt-in Kconfig options. And they protect the lower level functions called from enable_caches().
Maybe an opt-in wrapper Kconfig could still be needed? One that has e.g. "default y if SPL_FIT_SIGNATURE".
Vendor u-boot also enable caches early in SPL instead of just in U-Boot proper. There caches are enabled slightly different and even earlier.
Be careful to proceed with this to make it default, as it affects other drivers as well.
Any particular driver in mind that is in use by SPL that could be affected?
Based on limited testing at least SD/eMMC/SPI flash and pinctrl seemed to work okay on RK3328, RK3399 and RK356x. FIT checksum validated and boards could load and run TF-A and U-Boot proper.
Regards, Jonas
Jagan.
participants (2)
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Jagan Teki -
Jonas Karlman