[U-Boot] [PATCH 00/14] Add integrated phy support for rk322x and rk3328
To support the integrated phy, it is necessary that the gmac need to get 50M clock rate from internal PLL, the integrated phy can't generate 50M clock itself.
David Wu (14): net: rockchip: Separate rmii and rgmii speed setup net: rockchip: Add rmii interface and rmii speed setup for rk3228 and rk3328 net: rockchip: Add integrated phy ops net: rockchip: Add integrated phy for rk3228 and rk3328 cllk: rockchip: Change the defined name for CONFIG_RESET_ROCKCHIP clk: rockchip: fix the gmac selection of pll source for rk322x clk: rockchip: Init CPLL 600M for rk322x clk: rockchip: Add SCLK_MAC_SRC clock rate setup ARM: dts: rockchip: Add integrated phy reset and clock for rk322x ARM: dts: rockchip: Enable integrated phy support for rk3229-evb clk: rk3328: Implement the gmac2phy clock assignment ARM: dts: rockchip: Add gmac2phy dts node for rk3328 ARM: dts: rockchip: Enable gmac2phy feature for rk3328-evb rockchip: defconfig: Enable CONFIG_RESET_ROCKCHIP for rk3329-evb and rk3328-evb
arch/arm/dts/rk3229-evb.dts | 22 ++ arch/arm/dts/rk322x.dtsi | 8 +- arch/arm/dts/rk3328-evb.dts | 10 + arch/arm/dts/rk3328.dtsi | 35 +++ arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 18 +- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3328.c | 90 ++++++- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/rockchip/clk_rv1108.c | 2 +- drivers/net/gmac_rockchip.c | 328 ++++++++++++++++++++++-- 15 files changed, 487 insertions(+), 37 deletions(-)
Some Socs both have rgmii and rmii interface, so we need to separate their speed setting.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/net/gmac_rockchip.c | 62 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 683e820..4396ca1 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -40,7 +40,10 @@ struct gmac_rockchip_platdata { };
struct rk_gmac_ops { - int (*fix_mac_speed)(struct dw_eth_dev *priv); + int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv); + int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv); void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk322x_grf *grf; int clk; @@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3288_grf *grf; int clk; @@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3328_grf_regs *grf; int clk; @@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3368_grf *grf; int clk; @@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3399_grf_regs *grf; int clk; @@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rv1108_grf *grf; int clk, speed; @@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break; default: - debug("NO interface defined!\n"); + debug("%s: NO interface defined!\n", __func__); return -ENXIO; }
@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); int ret;
- ret = designware_eth_init(priv, pdata->enetaddr); - if (ret) - return ret; - ret = ops->fix_mac_speed(priv); + ret = designware_eth_init(priv, eth_pdata->enetaddr); if (ret) return ret; + + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = ops->fix_rgmii_speed(pdata, priv); + if (ret) + return ret; + break; + case PHY_INTERFACE_MODE_RMII: + ret = ops->fix_rmii_speed(pdata, priv); + if (ret) + return ret; + break; + default: + debug("%s: NO interface defined!\n", __func__); + return -ENXIO; + } + ret = designware_eth_enable(priv); if (ret) return ret; @@ -527,32 +551,32 @@ const struct eth_ops gmac_rockchip_eth_ops = { };
const struct rk_gmac_ops rk3228_gmac_ops = { - .fix_mac_speed = rk3228_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rgmii = rk3228_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3288_gmac_ops = { - .fix_mac_speed = rk3288_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3328_gmac_ops = { - .fix_mac_speed = rk3328_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rgmii = rk3328_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3368_gmac_ops = { - .fix_mac_speed = rk3368_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3399_gmac_ops = { - .fix_mac_speed = rk3399_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, .set_to_rgmii = rk3399_gmac_set_to_rgmii, };
const struct rk_gmac_ops rv1108_gmac_ops = { - .fix_mac_speed = rv1108_set_rmii_speed, + .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, .set_to_rmii = rv1108_gmac_set_to_rmii, };
Some Socs both have rgmii and rmii interface, so we need to separate their speed setting.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/net/gmac_rockchip.c | 62 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 19 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to separate their speed setting.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/net/gmac_rockchip.c | 62 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 683e820..4396ca1 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -40,7 +40,10 @@ struct gmac_rockchip_platdata { };
struct rk_gmac_ops {
- int (*fix_mac_speed)(struct dw_eth_dev *priv);
- int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv);- int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv);
Why can't this be a single fix_mac_speed function that does the right thing both for RMII and RGMII depending on the platdata?
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rk322x_grf *grf; int clk; @@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rk3288_grf *grf; int clk; @@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rk3328_grf_regs *grf; int clk; @@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rk3368_grf *grf; int clk; @@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rk3399_grf_regs *grf; int clk; @@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata,
struct dw_eth_dev *priv){ struct rv1108_grf *grf; int clk, speed; @@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break;default:
debug("NO interface defined!\n");
debug("%s: NO interface defined!\n", __func__);@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev) {
- struct eth_pdata *pdata = dev_get_platdata(dev);
- struct eth_pdata *eth_pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev);
- struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); int ret;
- ret = designware_eth_init(priv, pdata->enetaddr);
- if (ret)
return ret;- ret = ops->fix_mac_speed(priv);
- ret = designware_eth_init(priv, eth_pdata->enetaddr); if (ret) return ret;
- switch (eth_pdata->phy_interface) {
- case PHY_INTERFACE_MODE_RGMII:
ret = ops->fix_rgmii_speed(pdata, priv);if (ret)return ret;break;- case PHY_INTERFACE_MODE_RMII:
ret = ops->fix_rmii_speed(pdata, priv);if (ret)return ret;break;
Looking at this, the fix_mac_speed()-function could look into pdata to determine what needs to be done... no need to complicate the common code path with this.
- default:
debug("%s: NO interface defined!\n", __func__);return -ENXIO;- }
- ret = designware_eth_enable(priv); if (ret) return ret;
@@ -527,32 +551,32 @@ const struct eth_ops gmac_rockchip_eth_ops = { };
const struct rk_gmac_ops rk3228_gmac_ops = {
- .fix_mac_speed = rk3228_gmac_fix_mac_speed,
- .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rgmii = rk3228_gmac_set_to_rgmii,
};
const struct rk_gmac_ops rk3288_gmac_ops = {
- .fix_mac_speed = rk3288_gmac_fix_mac_speed,
- .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii,
};
const struct rk_gmac_ops rk3328_gmac_ops = {
- .fix_mac_speed = rk3328_gmac_fix_mac_speed,
- .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rgmii = rk3328_gmac_set_to_rgmii,
};
const struct rk_gmac_ops rk3368_gmac_ops = {
- .fix_mac_speed = rk3368_gmac_fix_mac_speed,
- .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii,
};
const struct rk_gmac_ops rk3399_gmac_ops = {
- .fix_mac_speed = rk3399_gmac_fix_mac_speed,
- .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, .set_to_rgmii = rk3399_gmac_set_to_rgmii,
};
const struct rk_gmac_ops rv1108_gmac_ops = {
- .fix_mac_speed = rv1108_set_rmii_speed,
- .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, .set_to_rmii = rv1108_gmac_set_to_rmii,
};
Hi Philipp,
在 2018年02月19日 03:36, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
Some Socs both have rgmii and rmii interface, so we need to separate their speed setting.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
drivers/net/gmac_rockchip.c | 62 +++++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 683e820..4396ca1 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -40,7 +40,10 @@ struct gmac_rockchip_platdata { };
struct rk_gmac_ops { - int (*fix_mac_speed)(struct dw_eth_dev *priv); + int (*fix_rmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv); + int (*fix_rgmii_speed)(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv);
Why can't this be a single fix_mac_speed function that does the right thing both for RMII and RGMII depending on the platdata?
I think this part is similar to the kernel code, and it's better to maintain.
void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -70,7 +73,8 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
-static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk322x_grf *grf; int clk; @@ -103,7 +107,8 @@ static int rk3228_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3288_grf *grf; int clk; @@ -129,7 +134,8 @@ static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3328_grf_regs *grf; int clk; @@ -162,7 +168,8 @@ static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3368_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3368_grf *grf; int clk; @@ -194,7 +201,8 @@ static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) +static int rk3399_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rk3399_grf_regs *grf; int clk; @@ -220,7 +228,8 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; }
-static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) { struct rv1108_grf *grf; int clk, speed; @@ -489,7 +498,7 @@ static int gmac_rockchip_probe(struct udevice *dev)
break; default: - debug("NO interface defined!\n"); + debug("%s: NO interface defined!\n", __func__); return -ENXIO; }
@@ -498,18 +507,33 @@ static int gmac_rockchip_probe(struct udevice *dev)
static int gmac_rockchip_eth_start(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); int ret;
- ret = designware_eth_init(priv, pdata->enetaddr); - if (ret) - return ret; - ret = ops->fix_mac_speed(priv); + ret = designware_eth_init(priv, eth_pdata->enetaddr); if (ret) return ret;
+ switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = ops->fix_rgmii_speed(pdata, priv); + if (ret) + return ret; + break; + case PHY_INTERFACE_MODE_RMII: + ret = ops->fix_rmii_speed(pdata, priv); + if (ret) + return ret; + break;
Looking at this, the fix_mac_speed()-function could look into pdata to determine what needs to be done... no need to complicate the common code path with this.
+ default: + debug("%s: NO interface defined!\n", __func__); + return -ENXIO; + }
ret = designware_eth_enable(priv); if (ret) return ret; @@ -527,32 +551,32 @@ const struct eth_ops gmac_rockchip_eth_ops = { };
const struct rk_gmac_ops rk3228_gmac_ops = { - .fix_mac_speed = rk3228_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rgmii = rk3228_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3288_gmac_ops = { - .fix_mac_speed = rk3288_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3288_gmac_fix_rgmii_speed, .set_to_rgmii = rk3288_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3328_gmac_ops = { - .fix_mac_speed = rk3328_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rgmii = rk3328_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3368_gmac_ops = { - .fix_mac_speed = rk3368_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3368_gmac_fix_rgmii_speed, .set_to_rgmii = rk3368_gmac_set_to_rgmii, };
const struct rk_gmac_ops rk3399_gmac_ops = { - .fix_mac_speed = rk3399_gmac_fix_mac_speed, + .fix_rgmii_speed = rk3399_gmac_fix_rgmii_speed, .set_to_rgmii = rk3399_gmac_set_to_rgmii, };
const struct rk_gmac_ops rv1108_gmac_ops = { - .fix_mac_speed = rv1108_set_rmii_speed, + .fix_rmii_speed = rv1108_gmac_fix_rmii_speed, .set_to_rmii = rv1108_gmac_set_to_rmii, };
The rk3228 and rk3328 Socs both have rmii interface, that might be used, so add them for usage.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/net/gmac_rockchip.c | 115 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 4396ca1..5afc415 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -73,6 +73,41 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) return designware_eth_ofdata_to_platdata(dev); }
+static int rk3228_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) +{ + struct rk322x_grf *grf; + int clk; + enum { + RK3228_GMAC_RMII_CLK_MASK = BIT(7), + RK3228_GMAC_RMII_CLK_2_5M = 0, + RK3228_GMAC_RMII_CLK_25M = BIT(7), + + RK3228_GMAC_RMII_SPEED_MASK = BIT(2), + RK3228_GMAC_RMII_SPEED_10 = 0, + RK3228_GMAC_RMII_SPEED_100 = BIT(2), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3228_GMAC_RMII_CLK_2_5M | RK3228_GMAC_RMII_SPEED_10; + break; + case 100: + clk = RK3228_GMAC_RMII_CLK_25M | RK3228_GMAC_RMII_SPEED_100; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_GMAC_RMII_CLK_MASK | RK3228_GMAC_RMII_SPEED_MASK, + clk); + + return 0; +} + static int rk3228_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, struct dw_eth_dev *priv) { @@ -134,6 +169,41 @@ static int rk3288_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, return 0; }
+static int rk3328_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, + struct dw_eth_dev *priv) +{ + struct rk3328_grf_regs *grf; + int clk; + enum { + RK3328_GMAC_RMII_CLK_MASK = BIT(7), + RK3328_GMAC_RMII_CLK_2_5M = 0, + RK3328_GMAC_RMII_CLK_25M = BIT(7), + + RK3328_GMAC_RMII_SPEED_MASK = BIT(2), + RK3328_GMAC_RMII_SPEED_10 = 0, + RK3328_GMAC_RMII_SPEED_100 = BIT(2), + }; + + switch (priv->phydev->speed) { + case 10: + clk = RK3328_GMAC_RMII_CLK_2_5M | RK3328_GMAC_RMII_SPEED_10; + break; + case 100: + clk = RK3328_GMAC_RMII_CLK_25M | RK3328_GMAC_RMII_SPEED_100; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], + RK3328_GMAC_RMII_CLK_MASK | RK3328_GMAC_RMII_SPEED_MASK, + clk); + + return 0; +} + static int rk3328_gmac_fix_rgmii_speed(struct gmac_rockchip_platdata *pdata, struct dw_eth_dev *priv) { @@ -264,6 +334,28 @@ static int rv1108_gmac_fix_rmii_speed(struct gmac_rockchip_platdata *pdata, return 0; }
+static void rk3228_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_GRF_CON_RMII_MODE_MASK = BIT(11), + RK3228_GRF_CON_RMII_MODE_SEL = BIT(11), + RK3228_RMII_MODE_MASK = BIT(10), + RK3228_RMII_MODE_SEL = BIT(10), + RK3228_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3228_GMAC_PHY_INTF_SEL_RMII = BIT(6), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->mac_con[1], + RK3228_GRF_CON_RMII_MODE_MASK | + RK3228_RMII_MODE_MASK | + RK3228_GMAC_PHY_INTF_SEL_MASK, + RK3228_GRF_CON_RMII_MODE_SEL | + RK3228_RMII_MODE_SEL | + RK3228_GMAC_PHY_INTF_SEL_RMII); +} + static void rk3228_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk322x_grf *grf; @@ -328,6 +420,25 @@ static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT); }
+static void rk3328_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_RMII_MODE_MASK = BIT(9), + RK3328_RMII_MODE = BIT(9), + + RK3328_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RK3328_GMAC_PHY_INTF_SEL_RMII = BIT(6), + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(pdata->integrated_phy ? &grf->mac_con[2] : &grf->mac_con[1], + RK3328_RMII_MODE_MASK | + RK3328_GMAC_PHY_INTF_SEL_MASK, + RK3328_GMAC_PHY_INTF_SEL_RMII | + RK3328_RMII_MODE); +} + static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3328_grf_regs *grf; @@ -551,7 +662,9 @@ const struct eth_ops gmac_rockchip_eth_ops = { };
const struct rk_gmac_ops rk3228_gmac_ops = { + .fix_rmii_speed = rk3228_gmac_fix_rmii_speed, .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, + .set_to_rmii = rk3228_gmac_set_to_rmii, .set_to_rgmii = rk3228_gmac_set_to_rgmii, };
@@ -561,7 +674,9 @@ const struct rk_gmac_ops rk3288_gmac_ops = { };
const struct rk_gmac_ops rk3328_gmac_ops = { + .fix_rmii_speed = rk3328_gmac_fix_rmii_speed, .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, + .set_to_rmii = rk3328_gmac_set_to_rmii, .set_to_rgmii = rk3328_gmac_set_to_rgmii, };
The rk3228 and rk3328 Socs both have rmii interface, that might be used, so add them for usage.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/net/gmac_rockchip.c | 115 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Some rockchio Socs have integrated phy inside, to support it, add the integrated phy ops.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/net/gmac_rockchip.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 5afc415..bca0a2a 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -10,6 +10,7 @@ #include <dm.h> #include <clk.h> #include <phy.h> +#include <reset.h> #include <syscon.h> #include <asm/io.h> #include <asm/arch/periph.h> @@ -22,6 +23,7 @@ #include <asm/arch/grf_rk3399.h> #include <asm/arch/grf_rv1108.h> #include <dm/pinctrl.h> +#include <dm/of_access.h> #include <dt-bindings/clock/rk3288-cru.h> #include "designware.h"
@@ -35,6 +37,8 @@ DECLARE_GLOBAL_DATA_PTR; struct gmac_rockchip_platdata { struct dw_eth_pdata dw_eth_pdata; bool clock_input; + bool integrated_phy; + struct reset_ctl phy_reset; int tx_delay; int rx_delay; }; @@ -46,13 +50,16 @@ struct rk_gmac_ops { struct dw_eth_dev *priv); void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); + void (*integrated_phy_powerup)(struct gmac_rockchip_platdata *pdata); };
static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + struct ofnode_phandle_args args; const char *string; + int ret;
string = dev_read_string(dev, "clock_in_out"); if (!strcmp(string, "input")) @@ -60,6 +67,25 @@ static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) else pdata->clock_input = false;
+ /* If phy-handle property is passed from DT, use it as the PHY */ + ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &args); + if (ret) { + debug("Cannot get phy phandle: ret=%d\n", ret); + pdata->integrated_phy = dev_read_bool(dev, "phy-is-integrated"); + } else { + debug("Found phy-handle subnode\n"); + pdata->integrated_phy = ofnode_read_bool(args.node, + "phy-is-integrated"); + } + + if (pdata->integrated_phy) { + ret = reset_get_by_name(dev, "mac-phy", &pdata->phy_reset); + if (ret) { + debug("No PHY reset control found: ret=%d\n", ret); + return ret; + } + } + /* Check the new naming-style first... */ pdata->tx_delay = dev_read_u32_default(dev, "tx_delay", -ENOENT); pdata->rx_delay = dev_read_u32_default(dev, "rx_delay", -ENOENT); @@ -572,6 +598,9 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret;
+ if (pdata->integrated_phy && ops->integrated_phy_powerup) + ops->integrated_phy_powerup(pdata); + switch (eth_pdata->phy_interface) { case PHY_INTERFACE_MODE_RGMII: /*
Some rockchio Socs have integrated phy inside, to support it, add the integrated phy ops.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/net/gmac_rockchip.c | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The rk3228 and rk3328 Socs both support integrated phy, implement their power up function to support it.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/net/gmac_rockchip.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+)
diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index bca0a2a..ec47933 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -583,6 +583,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) RV1108_GMAC_PHY_INTF_SEL_RMII); }
+static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), + }; + enum { + RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3228_MACPHY_CFG_CLK_50M = BIT(14), + + RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3228_MACPHY_RMII_MODE = BIT(6), + + RK3228_MACPHY_ENABLE_MASK = BIT(0), + RK3228_MACPHY_DISENABLE = 0, + RK3228_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->con_iomux, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); + + rk_clrsetreg(&grf->macphy_con[2], + RK3228_RK_GRF_CON2_MACPHY_ID_MASK, + RK3228_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3228_RK_GRF_CON3_MACPHY_ID_MASK, + RK3228_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_CFG_CLK_50M_MASK | + RK3228_MACPHY_RMII_MODE_MASK | + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_CFG_CLK_50M | + RK3228_MACPHY_RMII_MODE | + RK3228_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_ENABLE); + udelay(30 * 1000); +} + +static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), + RK3328_GRF_CON_RMII_MODE = BIT(9), + }; + enum { + RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3328_MACPHY_CFG_CLK_50M = BIT(14), + + RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3328_MACPHY_RMII_MODE = BIT(6), + + RK3328_MACPHY_ENABLE_MASK = BIT(0), + RK3328_MACPHY_DISENABLE = 0, + RK3328_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->macphy_con[1], + RK3328_GRF_CON_RMII_MODE_MASK, + RK3328_GRF_CON_RMII_MODE); + + rk_clrsetreg(&grf->macphy_con[2], + RK3328_RK_GRF_CON2_MACPHY_ID_MASK, + RK3328_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3328_RK_GRF_CON3_MACPHY_ID_MASK, + RK3328_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_CFG_CLK_50M_MASK | + RK3328_MACPHY_RMII_MODE_MASK | + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_CFG_CLK_50M | + RK3328_MACPHY_RMII_MODE | + RK3328_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_ENABLE); + udelay(30 * 1000); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); @@ -695,6 +815,7 @@ const struct rk_gmac_ops rk3228_gmac_ops = { .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rmii = rk3228_gmac_set_to_rmii, .set_to_rgmii = rk3228_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, };
const struct rk_gmac_ops rk3288_gmac_ops = { @@ -707,6 +828,7 @@ const struct rk_gmac_ops rk3328_gmac_ops = { .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rmii = rk3328_gmac_set_to_rmii, .set_to_rgmii = rk3328_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, };
const struct rk_gmac_ops rk3368_gmac_ops = {
The rk3228 and rk3328 Socs both support integrated phy, implement their power up function to support it.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/net/gmac_rockchip.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always should not been active.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 4 ++-- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3328.c | 4 ++-- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/rockchip/clk_rv1108.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c index 510a00a..3c74189 100644 --- a/drivers/clk/rockchip/clk_rk3036.c +++ b/drivers/clk/rockchip/clk_rk3036.c @@ -347,7 +347,7 @@ static int rk3036_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3036_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 9); if (ret) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4e6d2f0..4bbcaf8 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -509,9 +509,9 @@ static int rk322x_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk322x_cru, cru_softrst_con[0]); - ret = rockchip_reset_bind(dev, ret, 9); + ret = rockchip_reset_bind(dev, ret, 63); if (ret) debug("Warning: software reset driver bind faile\n"); #endif diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c index 552a71a..0c6b14b 100644 --- a/drivers/clk/rockchip/clk_rk3288.c +++ b/drivers/clk/rockchip/clk_rk3288.c @@ -968,7 +968,7 @@ static int rk3288_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3288_cru, cru_softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 12); if (ret) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 2ccc798..3f8cdc0 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -792,9 +792,9 @@ static int rk3328_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3328_cru, softrst_con[0]); - ret = rockchip_reset_bind(dev, ret, 12); + ret = rockchip_reset_bind(dev, ret, 100); if (ret) debug("Warning: software reset driver bind faile\n"); #endif diff --git a/drivers/clk/rockchip/clk_rk3368.c b/drivers/clk/rockchip/clk_rk3368.c index 3ac9add..bde3635 100644 --- a/drivers/clk/rockchip/clk_rk3368.c +++ b/drivers/clk/rockchip/clk_rk3368.c @@ -622,7 +622,7 @@ static int rk3368_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3368_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 15); if (ret) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 42926ba..a0fc329 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -1320,7 +1320,7 @@ static int rk3399_pmuclk_ofdata_to_platdata(struct udevice *dev)
static int rk3399_pmuclk_bind(struct udevice *dev) { -#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) int ret;
ret = offsetof(struct rk3399_pmucru, pmucru_softrst_con[0]); diff --git a/drivers/clk/rockchip/clk_rv1108.c b/drivers/clk/rockchip/clk_rv1108.c index 224c813..a2a1223 100644 --- a/drivers/clk/rockchip/clk_rv1108.c +++ b/drivers/clk/rockchip/clk_rv1108.c @@ -240,7 +240,7 @@ static int rv1108_clk_bind(struct udevice *dev) sys_child->priv = priv; }
-#if CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP) +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) ret = offsetof(struct rk3368_cru, softrst_con[0]); ret = rockchip_reset_bind(dev, ret, 13); if (ret)
It seems that the "CONFIG_IS_ENABLED(CONFIG_RESET_ROCKCHIP)" always should not been active.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk3036.c | 2 +- drivers/clk/rockchip/clk_rk322x.c | 4 ++-- drivers/clk/rockchip/clk_rk3288.c | 2 +- drivers/clk/rockchip/clk_rk3328.c | 4 ++-- drivers/clk/rockchip/clk_rk3368.c | 2 +- drivers/clk/rockchip/clk_rk3399.c | 2 +- drivers/clk/rockchip/clk_rv1108.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
There is a wrong selection for gmac pll source, fix it.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4bbcaf8..72c8757 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -255,7 +255,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) ulong pll_rate; u8 div;
- if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) + if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else /* CPLL is not set */
There is a wrong selection for gmac pll source, fix it.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
There is a wrong selection for gmac pll source, fix it.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk322x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The gmac for integrated phy need 50M clock, it seems that only come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + drivers/clk/rockchip/clk_rk322x.c | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h index a7999ca..801363d 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk322x.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk322x.h @@ -13,6 +13,7 @@
#define APLL_HZ (600 * MHz) #define GPLL_HZ (594 * MHz) +#define CPLL_HZ (600 * MHz)
#define CORE_PERI_HZ 150000000 #define CORE_ACLK_HZ 300000000 diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 72c8757..4022065 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -40,6 +40,7 @@ enum { /* use integer mode*/ static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 2, 2, 1);
static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, const struct pll_div *div) @@ -89,11 +90,13 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_SLOW << GPLL_MODE_SHIFT | - APLL_MODE_SLOW << APLL_MODE_SHIFT); + APLL_MODE_SLOW << APLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT);
/* init pll */ rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg);
/* * select apll as cpu/core clock pll source and @@ -166,7 +169,8 @@ static void rkclk_init(struct rk322x_cru *cru) rk_clrsetreg(&cru->cru_mode_con, GPLL_MODE_MASK | APLL_MODE_MASK, GPLL_MODE_NORM << GPLL_MODE_SHIFT | - APLL_MODE_NORM << APLL_MODE_SHIFT); + APLL_MODE_NORM << APLL_MODE_SHIFT | + CPLL_MODE_NORM << CPLL_MODE_SHIFT); }
/* Get pll rate by id */ @@ -258,8 +262,7 @@ static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) if (con & MAC_PLL_SEL_MASK) pll_rate = GPLL_HZ; else - /* CPLL is not set */ - return -EPERM; + pll_rate = CPLL_HZ;
div = DIV_ROUND_UP(pll_rate, freq) - 1; if (div <= 0x1f)
The gmac for integrated phy need 50M clock, it seems that only come from CPLL 600M, the GPLL is not suitable.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/include/asm/arch-rockchip/cru_rk322x.h | 1 + drivers/clk/rockchip/clk_rk322x.c | 11 +++++++---- 2 files changed, 8 insertions(+), 4 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index 4022065..7276c4a 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -390,6 +390,7 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC_SRC: case SCLK_MAC: new_rate = rk322x_mac_set_clk(priv->cru, rate); break;
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The SCLK_MAC_SRC is the same as the SCLK_MAC, it is requested by the integrated phy usuage.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk322x.c | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
To support the integrated phy for rk322x, add their reset and clock property at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/dts/rk322x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi index 22324f9..b0254a3 100644 --- a/arch/arm/dts/rk322x.dtsi +++ b/arch/arm/dts/rk322x.dtsi @@ -449,13 +449,13 @@ clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, - <&cru PCLK_GMAC>; + <&cru PCLK_GMAC>, <&cru SCLK_MAC_PHY>; clock-names = "stmmaceth", "mac_clk_rx", "mac_clk_tx", "clk_mac_ref", "clk_mac_refout", "aclk_mac", - "pclk_mac"; - resets = <&cru SRST_GMAC>; - reset-names = "stmmaceth"; + "pclk_mac", "clk_macphy"; + resets = <&cru SRST_GMAC>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; rockchip,grf = <&grf>; status = "disabled"; };
To support the integrated phy for rk322x, add their reset and clock property at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/dts/rk322x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
To support the integrated phy for rk322x, add their reset and clock property at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/dts/rk322x.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/dts/rk3229-evb.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ae0b0a4..547c7a2 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -63,7 +63,29 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; + status = "disabled"; +}; + +&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-supply = <&vcc_phy>; + phy-mode = "rmii"; + phy-handle = <&phy>; status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-is-integrated; + }; + }; };
&emmc {
In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/dts/rk3229-evb.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3229-evb.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ae0b0a4..547c7a2 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -63,7 +63,29 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>;
- status = "disabled";
+};
+&gmac {
- assigned-clocks = <&cru SCLK_MAC_SRC>;
- assigned-clock-rates = <50000000>;
- clock_in_out = "output";
- phy-supply = <&vcc_phy>;
- phy-mode = "rmii";
- phy-handle = <&phy>; status = "okay";
- mdio {
compatible = "snps,dwmac-mdio";#address-cells = <1>;#size-cells = <0>;phy: phy@0 {compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
Where is "ethernet-phy-id1234.d400" defined/used? I don't see anything in Linux or U-Boot.
reg = <0>;phy-is-integrated;
Documentation in the documentation for DTS bindings? Shouldn't this be rockchip,phy-is-integrated? What is the status of this on the Linux side?
};- };
};
&emmc {
Hi Philipp,
在 2018年02月19日 03:38, Philipp Tomsich 写道:
On Sat, 3 Feb 2018, David Wu wrote:
In fact, the evb-rk3229 is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3229-evb.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/rk3229-evb.dts b/arch/arm/dts/rk3229-evb.dts index ae0b0a4..547c7a2 100644 --- a/arch/arm/dts/rk3229-evb.dts +++ b/arch/arm/dts/rk3229-evb.dts @@ -63,7 +63,29 @@ snps,reset-delays-us = <0 10000 1000000>; tx_delay = <0x30>; rx_delay = <0x10>; + status = "disabled"; +};
+&gmac { + assigned-clocks = <&cru SCLK_MAC_SRC>; + assigned-clock-rates = <50000000>; + clock_in_out = "output"; + phy-supply = <&vcc_phy>; + phy-mode = "rmii"; + phy-handle = <&phy>; status = "okay";
+ mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>;
+ phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
Where is "ethernet-phy-id1234.d400" defined/used? I don't see anything in Linux or U-Boot.
Yes, The "ethernet-phy-id1234.d400" is not defined at linux/U-Boot. It does use the "ethernet-phy-ieee802.3-c22". The "ethernet-phy-id1234.d400" is a decorated aliases, the 0x1234d0 is the phy-id.
+ reg = <0>; + phy-is-integrated;
Documentation in the documentation for DTS bindings? Shouldn't this be rockchip,phy-is-integrated? What is the status of this on the Linux side?
I think it's consistent with kernel, especially if we might use kernel DTB file.
+ }; + }; };
&emmc {
Implement the setting parent and rate for gmac2phy clock, and add internal pll div set for gmac2phy clk.
Signed-off-by: David Wu david.wu@rock-chips.com ---
drivers/clk/rockchip/clk_rk3328.c | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 3f8cdc0..c576262 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -95,6 +95,14 @@ enum { PCLK_DBG_DIV_SHIFT = 0, PCLK_DBG_DIV_MASK = 0xF << PCLK_DBG_DIV_SHIFT,
+ /* CLKSEL_CON26 */ + GMAC2PHY_PLL_SEL_SHIFT = 7, + GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT, + GMAC2PHY_PLL_SEL_CPLL = 0, + GMAC2PHY_PLL_SEL_GPLL = 1, + GMAC2PHY_CLK_DIV_MASK = 0x1f, + GMAC2PHY_CLK_DIV_SHIFT = 0, + /* CLKSEL_CON27 */ GMAC2IO_PLL_SEL_SHIFT = 7, GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT, @@ -440,6 +448,39 @@ static ulong rk3328_gmac2io_set_clk(struct rk3328_cru *cru, ulong rate) return ret; }
+static ulong rk3328_gmac2phy_src_set_clk(struct rk3328_cru *cru, ulong rate) +{ + u32 con = readl(&cru->clksel_con[26]); + ulong pll_rate; + u8 div; + + if ((con >> GMAC2PHY_PLL_SEL_SHIFT) & GMAC2PHY_PLL_SEL_GPLL) + pll_rate = GPLL_HZ; + else + pll_rate = CPLL_HZ; + + div = DIV_ROUND_UP(pll_rate, rate) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->clksel_con[26], GMAC2PHY_CLK_DIV_MASK, + div << GMAC2PHY_CLK_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); +} + +static ulong rk3328_gmac2phy_set_clk(struct rk3328_cru *cru, ulong rate) +{ + struct rk3328_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (readl(&grf->mac_con[2]) & BIT(10)) + /* An external clock will always generate the right rate... */ + return rate; + else + return rk3328_gmac2phy_src_set_clk(cru, rate); +} + static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) { u32 div, con, con_id; @@ -608,6 +649,12 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_MAC2IO: ret = rk3328_gmac2io_set_clk(priv->cru, rate); break; + case SCLK_MAC2PHY: + ret = rk3328_gmac2phy_set_clk(priv->cru, rate); + break; + case SCLK_MAC2PHY_SRC: + ret = rk3328_gmac2phy_src_set_clk(priv->cru, rate); + break; case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; @@ -728,6 +775,43 @@ static int rk3328_gmac2io_ext_set_parent(struct clk *clk, struct clk *parent) return -EINVAL; }
+static int rk3328_gmac2phy_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk3328_grf_regs *grf; + const char *clock_output_name; + int ret; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + + /* + * If the requested parent is in the same clock-controller and the id + * is SCLK_MAC2PHY_SRC ("clk_mac2phy_src"), switch to the internal clock. + */ + if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC2PHY_SRC)) { + debug("%s: switching MAC CLK to SCLK_MAC2IO_PHY\n", __func__); + rk_clrreg(&grf->mac_con[2], BIT(10)); + return 0; + } + + /* + * Otherwise, we need to check the clock-output-names of the + * requested parent to see if the requested id is "phy_50m_out". + */ + ret = dev_read_string_index(parent->dev, "clock-output-names", + parent->id, &clock_output_name); + if (ret < 0) + return -ENODATA; + + /* If this is "phy_50m_out", switch to the external clock input */ + if (!strcmp(clock_output_name, "phy_50m_out")) { + debug("%s: switching MAC CLK to PHY_50M_OUT\n", __func__); + rk_setreg(&grf->mac_con[2], BIT(10)); + return 0; + } + + return -EINVAL; +} + static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) { switch (clk->id) { @@ -735,6 +819,8 @@ static int rk3328_clk_set_parent(struct clk *clk, struct clk *parent) return rk3328_gmac2io_set_parent(clk, parent); case SCLK_MAC2IO_EXT: return rk3328_gmac2io_ext_set_parent(clk, parent); + case SCLK_MAC2PHY: + return rk3328_gmac2phy_set_parent(clk, parent); case DCLK_LCDC: case SCLK_PDM: case SCLK_RTC32K:
Implement the setting parent and rate for gmac2phy clock, and add internal pll div set for gmac2phy clk.
Signed-off-by: David Wu david.wu@rock-chips.com
drivers/clk/rockchip/clk_rk3328.c | 86 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 5de1059..7026601 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -475,6 +475,41 @@ status = "disabled"; };
+ gmac2phy: ethernet@ff550000 { + compatible = "rockchip,rk3328-gmac"; + reg = <0x0 0xff550000 0x0 0x10000>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>, + <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>, + <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>, + <&cru SCLK_MAC2PHY_OUT>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_macphy"; + resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>; + reset-names = "stmmaceth", "mac-phy"; + phy-mode = "rmii"; + phy-handle = <&phy>; + pinctrl-names = "default"; + pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>; + status = "disabled"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + phy: phy@0 { + compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + phy-is-integrated; + }; + }; + }; + usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>;
The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
On Sat, 3 Feb 2018, David Wu wrote:
The gmac2phy is connected with integrated with phy, we can fix the phy node at dtsi level.
Signed-off-by: David Wu david.wu@rock-chips.com Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3328.dtsi | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 5de1059..7026601 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -475,6 +475,41 @@ status = "disabled"; };
- gmac2phy: ethernet@ff550000 {
compatible = "rockchip,rk3328-gmac";reg = <0x0 0xff550000 0x0 0x10000>;rockchip,grf = <&grf>;interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;interrupt-names = "macirq";clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,<&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,<&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,<&cru SCLK_MAC2PHY_OUT>;clock-names = "stmmaceth", "mac_clk_rx","mac_clk_tx", "clk_mac_ref","aclk_mac", "pclk_mac","clk_macphy";resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;reset-names = "stmmaceth", "mac-phy";phy-mode = "rmii";phy-handle = <&phy>;pinctrl-names = "default";pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;status = "disabled";mdio {compatible = "snps,dwmac-mdio";#address-cells = <1>;#size-cells = <0>;phy: phy@0 {compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";reg = <0>;phy-is-integrated;
Again: is this a common config option? If not: shouldn't this be "rockchip,phy-is-integrated"?
};};- };
- usb_host0_ehci: usb@ff5c0000 { compatible = "generic-ehci"; reg = <0x0 0xff5c0000 0x0 0x10000>;
In fact, the rk3328-evb is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com ---
arch/arm/dts/rk3328-evb.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 336c2d5..1e09f7d 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -101,6 +101,16 @@ pinctrl-0 = <&rgmiim1_pins>; tx_delay = <0x26>; rx_delay = <0x11>; + status = "disabled"; +}; + +&gmac2phy { + phy-supply = <&vcc_phy>; + clock_in_out = "output"; + assigned-clocks = <&cru SCLK_MAC2PHY_SRC>; + assigned-clock-rate = <50000000>; + assigned-clocks = <&cru SCLK_MAC2PHY>; + assigned-clock-parents = <&cru SCLK_MAC2PHY_SRC>; status = "okay"; };
In fact, the rk3328-evb is default supported the integrated phy, not need to change any hardware. So it is better to enbale it and disable external 1000M phy.
Signed-off-by: David Wu david.wu@rock-chips.com
arch/arm/dts/rk3328-evb.dts | 10 ++++++++++ 1 file changed, 10 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The integtated phy inside the rk3229 and rk3328 need the reset request for power up.
Signed-off-by: David Wu david.wu@rock-chips.com ---
configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/evb-rk3229_defconfig b/configs/evb-rk3229_defconfig index 39469b4..311019d 100644 --- a/configs/evb-rk3229_defconfig +++ b/configs/evb-rk3229_defconfig @@ -40,6 +40,7 @@ CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK322X=y CONFIG_RAM=y CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0x11030000 CONFIG_DEBUG_UART_CLOCK=24000000 diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3d8c04d..12497fa 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -38,6 +38,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_REGULATOR_RK8XX=y CONFIG_PWM_ROCKCHIP=y CONFIG_RAM=y +CONFIG_DM_RESET=y CONFIG_BAUDRATE=1500000 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000
The integtated phy inside the rk3229 and rk3328 need the reset request for power up.
Signed-off-by: David Wu david.wu@rock-chips.com
configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+)
Acked-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
The integtated phy inside the rk3229 and rk3328 need the reset request for power up.
Signed-off-by: David Wu david.wu@rock-chips.com
configs/evb-rk3229_defconfig | 1 + configs/evb-rk3328_defconfig | 1 + 2 files changed, 2 insertions(+)
Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
participants (2)
-
David Wu -
Philipp Tomsich