On Fri, 10 Mar 2017 12:26:36 +0100 Gary Bisson gary.bisson@boundarydevices.com wrote:

No need to check the region range and send commands when the cache isn't even enabled.

Signed-off-by: Gary Bisson gary.bisson@boundarydevices.com

Hi all,

This is a follow-up to this thread: https://lists.denx.de/pipermail/u-boot/2017-March/283423.html

Although what started the conversation was the sparse-image flashing procedure, it appears cache maintenance functions don't check on cache status.

Regards, Gary

---

arch/arm/cpu/armv7/cache_v7.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index c4bbcc3cc3..992cdeaa6e 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -117,6 +117,9 @@ void flush_dcache_all(void) */ void invalidate_dcache_range(unsigned long start, unsigned long stop) {

• if (!dcache_status())

• return;
  

• check_cache_range(start, stop);

  v7_dcache_maint_range(start, stop, ARMV7_DCACHE_INVAL_RANGE);

@@ -131,6 +134,9 @@ void invalidate_dcache_range(unsigned long start, unsigned long stop) */ void flush_dcache_range(unsigned long start, unsigned long stop) {

• if (!dcache_status())

• return;
  

• check_cache_range(start, stop);

  v7_dcache_maint_range(start, stop, ARMV7_DCACHE_CLEAN_INVAL_RANGE);

Hello Gary,

Please be very careful with this stuff:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABHEJFF.html

"6.4.3. Cache disabled behavior

When you clear the C bit in the CP15 System Control Register for a given processor, see System Control Register, data caching is disabled and no new cache lines are allocated to the L1 data cache and L2 cache because of requests from that processor. This is important when cleaning and invalidating the caches for power down. Cache lines can be allocated from memory requests of other processors, unless their cache enable bits are also cleared. The effect on the L1 memory system is that all Write-Back Read-Write-Allocate pages are treated as Write-Back No-Allocate pages.

When you disable the cache, all Write-Back Cacheable requests still look up the L1 cache. If there is a cache hit, the cache is read or updated in the same way as if the cache is enabled. This enables Cacheable memory to remain fully coherent while the cache is disabled.

While the cache is disabled, it remains fully coherent with the L2 cache and the other L1 data caches."

Basically, disabling cache only disables allocation of new cache lines. We still need to do proper cache maintenance.