CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.

This patch add new CONFIG defination and move existing register space definaton of CCI-400 bus from from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3.

Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com --- v2: Add new Kconfig in alphabetic order

README | 9 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 6 +++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 1 + arch/arm/cpu/armv8/fsl-layerscape/soc.c | 1 + .../include/asm/arch-fsl-layerscape/immap_lsch2.h | 48 -------------------- .../include/asm/arch-fsl-layerscape/immap_lsch3.h | 1 + include/fsl_immap.h | 51 ++++++++++++++++++++++ 7 files changed, 69 insertions(+), 48 deletions(-)

diff --git a/README b/README index 4f0dbd4..34f5bd3 100644 --- a/README +++ b/README @@ -315,6 +315,15 @@ Many of the options are named exactly as the corresponding Linux kernel configuration options. The intention is to make it easier to build a config tool - later.

+- ARM Platform Bus Type(CCI): + CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which + provides full cache coherency between two clusters of multi-core + CPUs and I/O coherency for devices and I/O masters + + CONFIG_SYS_FSL_HAS_CCI400 + + Defined For SoC that has cache coherent interconnect + CCN-400

The following options need to be configured:

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index adccdf1..64fae17 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -7,6 +7,7 @@ config ARCH_LS1012A select SYS_FSL_ERRATUM_A010315 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400

config ARCH_LS1043A bool @@ -26,6 +27,7 @@ config ARCH_LS1043A select SYS_FSL_HAS_DDR4 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400

config ARCH_LS1046A bool @@ -45,6 +47,7 @@ config ARCH_LS1046A select SYS_FSL_SRDS_2 select ARCH_EARLY_INIT_R select BOARD_EARLY_INIT_F + select SYS_FSL_HAS_CCI400

config ARCH_LS2080A bool @@ -182,6 +185,9 @@ config SYS_FSL_IFC_BANK_COUNT default 4 if ARCH_LS1046A default 8 if ARCH_LS2080A

+config SYS_FSL_HAS_CCI400 + bool + config SYS_FSL_HAS_DP_DDR bool

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 335f225..a1ac4a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -29,6 +29,7 @@ #ifdef CONFIG_SYS_FSL_DDR #include <fsl_ddr.h> #endif +#include <fsl_immap.h>

DECLARE_GLOBAL_DATA_PTR;

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 9489f85..d64fe7b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -5,6 +5,7 @@ */

#include <common.h> +#include <fsl_immap.h> #include <fsl_ifc.h> #include <ahci.h> #include <scsi.h> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 8ad199f..5210b8c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -543,54 +543,6 @@ struct ccsr_serdes { u8 res_19a0[0x2000-0x19a0]; /* from 0x19a0 to 0x1fff */ };

-#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 -#define CCI400_CTRLORD_EN_BARRIER 0 -#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 -#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 -#define CCI400_SNOOP_REQ_EN 0x00000001 - -/* CCI-400 registers */ -struct ccsr_cci400 { - u32 ctrl_ord; /* Control Override */ - u32 spec_ctrl; /* Speculation Control */ - u32 secure_access; /* Secure Access */ - u32 status; /* Status */ - u32 impr_err; /* Imprecise Error */ - u8 res_14[0x100 - 0x14]; - u32 pmcr; /* Performance Monitor Control */ - u8 res_104[0xfd0 - 0x104]; - u32 pid[8]; /* Peripheral ID */ - u32 cid[4]; /* Component ID */ - struct { - u32 snoop_ctrl; /* Snoop Control */ - u32 sha_ord; /* Shareable Override */ - u8 res_1008[0x1100 - 0x1008]; - u32 rc_qos_ord; /* read channel QoS Value Override */ - u32 wc_qos_ord; /* read channel QoS Value Override */ - u8 res_1108[0x110c - 0x1108]; - u32 qos_ctrl; /* QoS Control */ - u32 max_ot; /* Max OT */ - u8 res_1114[0x1130 - 0x1114]; - u32 target_lat; /* Target Latency */ - u32 latency_regu; /* Latency Regulation */ - u32 qos_range; /* QoS Range */ - u8 res_113c[0x2000 - 0x113c]; - } slave[5]; /* Slave Interface */ - u8 res_6000[0x9004 - 0x6000]; - u32 cycle_counter; /* Cycle counter */ - u32 count_ctrl; /* Count Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_9010[0xa000 - 0x9010]; - struct { - u32 event_select; /* Event Select */ - u32 event_count; /* Event Count */ - u32 counter_ctrl; /* Counter Control */ - u32 overflow_status; /* Overflow Flag Status */ - u8 res_a010[0xb000 - 0xa010]; - } pcounter[4]; /* Performance Counter */ - u8 res_e004[0x10000 - 0xe004]; -}; - /* MMU 500 */ #define SMMU_SCR0 (SMMU_BASE + 0x0) #define SMMU_SCR1 (SMMU_BASE + 0x4) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 0678fba..04add3b 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -10,6 +10,7 @@ #define __ARCH_FSL_LSCH3_IMMAP_H_

#define CONFIG_SYS_IMMR 0x01000000 +#define CONFIG_SYS_CCI400_ADDR (CONFIG_SYS_IMMR + 0x3090000) #define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) #define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 diff --git a/include/fsl_immap.h b/include/fsl_immap.h index b1c4fe7..4f5a19c 100644 --- a/include/fsl_immap.h +++ b/include/fsl_immap.h @@ -133,4 +133,55 @@ struct ccsr_ddr { u8 res_e5c[164]; u32 debug[64]; /* debug_1 to debug_64 */ }; + +#ifdef CONFIG_SYS_FSL_HAS_CCI400 +#define CCI400_CTRLORD_TERM_BARRIER 0x00000008 +#define CCI400_CTRLORD_EN_BARRIER 0 +#define CCI400_SHAORD_NON_SHAREABLE 0x00000002 +#define CCI400_DVM_MESSAGE_REQ_EN 0x00000002 +#define CCI400_SNOOP_REQ_EN 0x00000001 + +/* CCI-400 registers */ +struct ccsr_cci400 { + u32 ctrl_ord; /* Control Override */ + u32 spec_ctrl; /* Speculation Control */ + u32 secure_access; /* Secure Access */ + u32 status; /* Status */ + u32 impr_err; /* Imprecise Error */ + u8 res_14[0x100 - 0x14]; + u32 pmcr; /* Performance Monitor Control */ + u8 res_104[0xfd0 - 0x104]; + u32 pid[8]; /* Peripheral ID */ + u32 cid[4]; /* Component ID */ + struct { + u32 snoop_ctrl; /* Snoop Control */ + u32 sha_ord; /* Shareable Override */ + u8 res_1008[0x1100 - 0x1008]; + u32 rc_qos_ord; /* read channel QoS Value Override */ + u32 wc_qos_ord; /* read channel QoS Value Override */ + u8 res_1108[0x110c - 0x1108]; + u32 qos_ctrl; /* QoS Control */ + u32 max_ot; /* Max OT */ + u8 res_1114[0x1130 - 0x1114]; + u32 target_lat; /* Target Latency */ + u32 latency_regu; /* Latency Regulation */ + u32 qos_range; /* QoS Range */ + u8 res_113c[0x2000 - 0x113c]; + } slave[5]; /* Slave Interface */ + u8 res_6000[0x9004 - 0x6000]; + u32 cycle_counter; /* Cycle counter */ + u32 count_ctrl; /* Count Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_9010[0xa000 - 0x9010]; + struct { + u32 event_select; /* Event Select */ + u32 event_count; /* Event Count */ + u32 counter_ctrl; /* Counter Control */ + u32 overflow_status; /* Overflow Flag Status */ + u8 res_a010[0xb000 - 0xa010]; + } pcounter[4]; /* Performance Counter */ + u8 res_e004[0x10000 - 0xe004]; +}; +#endif + #endif /* __FSL_IMMAP_H */