Hi Tom,

Please pull some riscv updates:

- Fix sifive serial y-modem transfer. - Access CSRs using CSR numbers. - Update doc sifive-fu540 - Support big endian hosts and target.

https://travis-ci.org/rickchen36/u-boot-riscv/builds/572159567

Thanks Rick

The following changes since commit df33f8646855e65b8e7232c7fd5739e1ae1eb58b:

configs: Resync with savedefconfig (2019-08-14 08:11:27 -0400)

are available in the Git repository at:

git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to 4539926a9c47638951f29f550f3a640e4c223032:

riscv: tools: Add big endian target support to prelink-riscv (2019-08-15 13:42:28 +0800)

---------------------------------------------------------------- Anup Patel (1): doc: sifive-fu540: Update README to explicitly load DTB for Linux

Bin Meng (2): riscv: Sync csr.h with Linux kernel v5.2 riscv: Access CSRs using CSR numbers

Marcus Comstedt (2): riscv: tools: Fix prelink-riscv to work on big endian hosts riscv: tools: Add big endian target support to prelink-riscv

Sagar Shrikant Kadam (1): riscv : serial: use rx watermark to indicate rx data is present

arch/riscv/cpu/cpu.c | 9 ++- arch/riscv/cpu/start.S | 3 +- arch/riscv/include/asm/asm.h | 68 ++++++++++++++++++++ arch/riscv/include/asm/csr.h | 74 +++++++++++++++++----- arch/riscv/include/asm/encoding.h | 238 +-------------------------------------------------------------------- doc/board/sifive/fu540.rst | 396 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++--------------------------------------------------- drivers/serial/serial_sifive.c | 23 +++---- tools/prelink-riscv.c | 39 +++++++++--- tools/prelink-riscv.inc | 60 ++++++++++-------- 9 files changed, 426 insertions(+), 484 deletions(-) create mode 100644 arch/riscv/include/asm/asm.h