Hi Przemyslaw,

I have a question.

"dfu_alt_bootloader" env is settings successfully

dfu_alt_bootloader=u-boot raw 0x3e 0x800 mmcpart 1

But, In order to replace bootloader binary in thor mode, How can I use the "dfu_alt_bootloader" env?

DFU gadget use "dfu_alt_info" env for DFU entities configuration.

Is there any patch to support multiple "dfu_alt" environment, or "dfu_alt_info" environment settings to use "dfu_alt_bootloader" env?

best regards, Inha Song.

On Tue, 10 Jun 2014 13:32:58 +0200 Przemyslaw Marczak p.marczak@samsung.com wrote:

This change adds new function:

• set_dfu_boot_alt(bootmode) - where bootmode is the value of Exynos ompin[5:1] masked with BOOT_MODE(x) macro.

This change is useful for devices with more than one boot device, e.g. with a separated SD and eMMC slots. Different dfu entities are required for SD and eMMC cards. The board config should define:

• CONFIG_MISC_COMMON
• CONFIG_SET_DFU_BOOT_ALT

and at least one of below alt setting:

• CONFIG_DFU_BOOT_ALT_SD, e.g: "u-boot raw 1 2048"
• CONFIG_DFU_BOOT_ALT_eMMC, e.g: "u-boot raw 0 2048 mmcpart 1"

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

---

board/samsung/common/board.c | 3 +++ board/samsung/common/misc.c | 23 +++++++++++++++++++++++ include/samsung/misc.h | 4 ++++ 3 files changed, 30 insertions(+)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 2970340..9a745d9 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -323,6 +323,9 @@ int arch_early_init_r(void) #ifdef CONFIG_MISC_INIT_R int misc_init_r(void) { +#ifdef CONFIG_SET_DFU_BOOT_ALT

• set_dfu_boot_alt(bootmode);

+#endif #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG set_board_info(); #endif diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index a453a82..d31583b 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -21,6 +21,29 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SET_DFU_BOOT_ALT +void set_dfu_boot_alt(int bootmode) +{

• char *alt_bootloader = NULL;
• switch (bootmode) {
• case BOOT_SDMMC:

+#ifdef CONFIG_DFU_BOOT_ALT_SD

• alt_bootloader = CONFIG_DFU_BOOT_ALT_SD;
  

+#endif

• break;
  

• default:

+#ifdef CONFIG_DFU_BOOT_ALT_EMMC

• alt_bootloader = CONFIG_DFU_BOOT_ALT_EMMC;
  

+#endif

• break;
  

• }
• if (alt_bootloader)

• setenv("dfu_alt_bootloader", alt_bootloader);
  

+} +#endif

#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG void set_board_info(void) { diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 87b53ec..dfc0946 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -33,4 +33,8 @@ void draw_logo(void); #define BOOT_MODE_SHIFT (0x1) #define BOOT_MODE(x) ((x >> BOOT_MODE_SHIFT) & BOOT_MODE_MASK)

+#ifdef CONFIG_SET_DFU_BOOT_ALT +void set_dfu_boot_alt(int bootmode); +#endif

#endif /* __SAMSUNG_MISC_COMMON_H__ */

1.9.1

Hi Przemyslaw,

In U3 board, cooling pan is not work. I think, cooling pan setting is need in board_gpio_init(). (X2 board use cooling pan pwr form USB port)

best regards, Inha Song.

On Tue, 10 Jun 2014 13:33:02 +0200 Przemyslaw Marczak p.marczak@samsung.com wrote:

This board file supports standard features of Odroid X2 and U3 boards:

• Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
• MAX77686 power regulator,
• USB PHY,
• enable XCL205 - power for board peripherials
• check board type: U3 or X2.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com

---

board/samsung/odroid/Makefile | 8 + board/samsung/odroid/odroid.c | 432 ++++++++++++++++++++++++++++++++++++++++++ board/samsung/odroid/setup.h | 227 ++++++++++++++++++++++ 3 files changed, 667 insertions(+) create mode 100644 board/samsung/odroid/Makefile create mode 100644 board/samsung/odroid/odroid.c create mode 100644 board/samsung/odroid/setup.h

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile new file mode 100644 index 0000000..b98aaeb --- /dev/null +++ b/board/samsung/odroid/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# Przemyslaw Marczak p.marczak@samsung.com +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := odroid.o diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c new file mode 100644 index 0000000..20a41b2 --- /dev/null +++ b/board/samsung/odroid/odroid.c @@ -0,0 +1,432 @@ +/*

• • Copyright (C) 2014 Samsung Electronics
• • Przemyslaw Marczak p.marczak@samsung.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/cpu.h> +#include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <errno.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include "setup.h"

+DECLARE_GLOBAL_DATA_PTR;

+/* Odroid board types */ +enum {

• ODROID_TYPE_U3,
• ODROID_TYPE_X2,

+};

+static void set_board_type(void) +{

• int val;
• /* Check GPC1 pin 2 */
• gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
• gpio_direction_input(EXYNOS4X12_GPIO_C12);
• /* XCL205 - needs some latch time */
• mdelay(10);
• /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
• val = gpio_get_value(EXYNOS4X12_GPIO_C12);
• if (val)

• gd->board_type = ODROID_TYPE_X2;
  

• else

• gd->board_type = ODROID_TYPE_U3;
  

+}

+const char *get_board_type(void) +{

• const char *board_type_str[] = {"U3", "X2"};
• set_board_type();
• return board_type_str[gd->board_type];

+}

+const char *get_board_type_fdt(void) +{

• const char *board_type_fdt[] = {"u3", "x2"};
• return board_type_fdt[gd->board_type];

+}

+static void board_clock_init(void) +{

• unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
• struct exynos4x12_clock *clk = (struct exynos4x12_clock *)

• 				samsung_get_base_clock();
  

• /*

• * CMU_CPU clocks src to MPLL
  

• * Bit values:                 0  ; 1
  

• * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
  

• * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
  

• * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
  

• * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
  

• */
• clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |

•       MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
  

• set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |

•      MUX_MPLL_USER_SEL_C(1);
  

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

• continue;
  

• /* Set APLL to 1000MHz */
• clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1);
• set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
• clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))

• continue;
  

• /* Set CMU_CPU clocks src to APLL */
• set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |

•      MUX_MPLL_USER_SEL_C(1);
  

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

• continue;
  

• set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |

•      PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  

•      APLL_RATIO(0) | CORE2_RATIO(0);
  

• /*

• * Set dividers for MOUTcore = 1000 MHz
  

• * coreout =      MOUT / (ratio + 1) = 1000 MHz (0)
  

• * corem0 =     armclk / (ratio + 1) = 333 MHz (2)
  

• * corem1 =     armclk / (ratio + 1) = 166 MHz (5)
  

• * periph =     armclk / (ratio + 1) = 1000 MHz (0)
  

• * atbout =       MOUT / (ratio + 1) = 200 MHz (4)
  

• * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  

• * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  

• * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  

• */
• clr = CORE_RATIO(0x7) | COREM0_RATIO(0x7) | COREM1_RATIO(0x7) |

•      PERIPH_RATIO(0x7) | ATB_RATIO(0x7) | PCLK_DBG_RATIO(0x7) |
  

•      APLL_RATIO(0x7) | CORE2_RATIO(0x7);
  

• clrsetbits_le32(&clk->div_cpu0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)

• continue;
  

• /*

• * For MOUThpm = 1000 MHz (MOUTapll)
  

• * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  

• * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  

• * cores_out = armclk / (ratio + 1) = 1000 (0)
  

• */
  

• clr = COPY_RATIO(0x7) | HPM_RATIO(0x7) | CORES_RATIO(0x7);
• set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
• clrsetbits_le32(&clk->div_cpu1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)

• continue;
  

• /*

• * Set CMU_DMC clocks src to APLL
  

• * Bit values:             0  ; 1
  

• * MUX_C2C_SEL:      SCLKMPLL ; SCLKAPLL
  

• * MUX_DMC_BUS_SEL:  SCLKMPLL ; SCLKAPLL
  

• * MUX_DPHY_SEL:     SCLKMPLL ; SCLKAPLL
  

• * MUX_MPLL_SEL:     FINPLL   ; MOUT_MPLL_FOUT
  

• * MUX_PWI_SEL:      0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  

• * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  

• * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  

• * MUX_G2D_ACP_SEL:  OUT_ACP0 ; OUT_ACP1
  

• */
• clr_src_dmc = MUX_C2C_SEL(0x1) | MUX_DMC_BUS_SEL(0x1) |

•       MUX_DPHY_SEL(0x1) | MUX_MPLL_SEL(0x1) |
  

•       MUX_PWI_SEL(0xf) | MUX_G2D_ACP0_SEL(0x1) |
  

•       MUX_G2D_ACP1_SEL(0x1) | MUX_G2D_ACP_SEL(0x1);
  

• set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |

•      MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  

•      MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

• continue;
  

• /* Set MPLL to 800MHz */
• set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
• clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))

• continue;
  

• /* Switch back CMU_DMC mux */
• set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |

•      MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  

•      MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

• continue;
  

• /* CLK_DIV_DMC0 */
• clr = ACP_RATIO(0x7) | ACP_PCLK_RATIO(0x7) | DPHY_RATIO(0x7) |

•      DMC_RATIO(0x7) | DMCD_RATIO(0x7) | DMCP_RATIO(0x7);
  

• /*

• * For:
  

• * MOUTdmc = 800 MHz
  

• * MOUTdphy = 800 MHz
  

• *
  

• * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  

• * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  

• * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  

• * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  

• * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  

• * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
  

• */
  

• set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |

•      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)

• continue;
  

• /* CLK_DIV_DMC1 */
• clr = G2D_ACP_RATIO(0xf) | C2C_RATIO(0x7) | PWI_RATIO(0xf) |

•      C2C_ACLK_RATIO(0x7) | DVSEM_RATIO(0x7f) | DPM_RATIO(0x7f);
  

• /*

• * For:
  

• * MOUTg2d = 800 MHz
  

• * MOUTc2c = 800 Mhz
  

• * MOUTpwi = 108 MHz
  

• *
  

• * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
  

• * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  

• * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
  

• * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  

• */
  

• set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |

•      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)

• continue;
  

• /* CLK_SRC_PERIL0 */
• clr = UART0_SEL(0xf) | UART1_SEL(0xf) | UART2_SEL(0xf) |

•      UART3_SEL(0xf) | UART4_SEL(0xf);
  

• /*

• * Set CLK_SRC_PERIL0 clocks src to MPLL
  

• * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  

• *             5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  

• *             8(SCLK_VPLL)
  

• *
  

• * Set all to SCLK_MPLL_USER_T
  

• */
  

• set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |

•      UART4_SEL(6);
  

• clrsetbits_le32(&clk->src_peril0, clr, set);
• /* CLK_DIV_PERIL0 */
• clr = UART0_RATIO(0xf) | UART1_RATIO(0xf) | UART2_RATIO(0xf) |

•      UART3_RATIO(0xf) | UART4_RATIO(0xf);
  

• /*

• * For MOUTuart0-4: 800MHz
  

• *
  

• * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
  

• */
• set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |

•      UART3_RATIO(7) | UART4_RATIO(7);
  

• clrsetbits_le32(&clk->div_peril0, clr, set);
• while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS1 */
• clr = MMC0_RATIO(0xf) | MMC0_PRE_RATIO(0xff) | MMC1_RATIO(0xf) |

•      MMC1_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  

• * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  

• * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  

• * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
  

• */
• set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |

•      MMC1_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS2 */
• clr = MMC2_RATIO(0xf) | MMC2_PRE_RATIO(0xff) | MMC3_RATIO(0xf) |

•      MMC3_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  

• * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  

• * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  

• * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
  

• */
• set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |

•      MMC3_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys2, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS3 */
• clr = MMC4_RATIO(0xf) | MMC4_PRE_RATIO(0xff);
• /*

• * For MOUTmmc4 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  

• * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
  

• */
• set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
• clrsetbits_le32(&clk->div_fsys3, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)

• continue;
  

• return;

+}

+static void board_gpio_init(void) +{

• /* Set GPA1 pin 1 to HI - enable XCL205 output */
• gpio_set_pull(EXYNOS4X12_GPIO_A11, S5P_GPIO_PULL_UP);
• gpio_set_drv(EXYNOS4X12_GPIO_A11, S5P_GPIO_DRV_4X);
• gpio_direction_output(EXYNOS4X12_GPIO_A11, 1);
• gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
• gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);

+}

+static int pmic_init_max77686(void) +{

• struct pmic *p = pmic_get("MAX77686_PMIC");
• if (pmic_probe(p))

• return -ENODEV;
  

• /* Set LDO Voltage */
• max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
• max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
• max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */
• return 0;

+}

+#ifdef CONFIG_SYS_I2C_INIT_BOARD +static void board_init_i2c(void) +{

• /* I2C_0 */
• if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))

• debug("I2C%d not configured\n", (I2C_0));
  

+} +#endif

+int exynos_early_init_f(void) +{

• board_clock_init();
• board_gpio_init();
• return 0;

+}

+int exynos_init(void) +{

• return 0;

+}

+int exynos_power_init(void) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD

• board_init_i2c();

+#endif

• pmic_init(I2C_0);
• pmic_init_max77686();
• return 0;

+}

+#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{

• struct pmic *p_pmic;
• p_pmic = pmic_get("MAX77686_PMIC");
• if (!p_pmic)

• return -ENODEV;
  

• if (pmic_probe(p_pmic))

• return -1;
  

• if (on)

• return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
  

• else

• return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
  

+}

+struct s3c_plat_otg_data s5pc210_otg_data = {

• .phy_control = s5pc210_phy_control,
• .regs_phy = EXYNOS4X12_USBPHY_BASE,
• .regs_otg = EXYNOS4X12_USBOTG_BASE,
• .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
• .usb_flags = PHY0_SLEEP,

+};

+int board_usb_init(int index, enum usb_init_type init) +{

• debug("USB_udc_probe\n");
• return s3c_udc_probe(&s5pc210_otg_data);

+} +#endif

+void reset_misc(void) +{

• /* Reset eMMC*/
• gpio_set_value(EXYNOS4X12_GPIO_K12, 0);
• mdelay(10);
• gpio_set_value(EXYNOS4X12_GPIO_K12, 1);

+} diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h new file mode 100644 index 0000000..982d676 --- /dev/null +++ b/board/samsung/odroid/setup.h @@ -0,0 +1,227 @@ +/*

• • Copyright (C) 2014 Samsung Electronics
• • Przemyslaw Marczak p.marczak@samsung.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __ODROIDU3_SETUP__ +#define __ODROIDU3_SETUP__

+/* A/M PLL_CON0 */ +#define SDIV(x) (x & 0x7) +#define PDIV(x) ((x & 0x3f) << 8) +#define MDIV(x) ((x & 0x3ff) << 16) +#define FSEL(x) ((x & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) ((x & 0x1) << 31)

+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) (x & 0x1) +#define MUX_CORE_SEL(x) ((x & 0x1) << 16) +#define MUX_HPM_SEL(x) ((x & 0x1) << 20) +#define MUX_MPLL_USER_SEL_C(x) ((x & 0x1) << 24)

+#define MUX_STAT_CHANGING 0x100

+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) (x & 0x7) +#define CORE_SEL(x) ((x & 0x7) << 16) +#define HPM_SEL(x) ((x & 0x7) << 20) +#define MPLL_USER_SEL_C(x) ((x & 0x7) << 24) +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \

• 		CORE_SEL(MUX_STAT_CHANGING) | \
  

• 		HPM_SEL(MUX_STAT_CHANGING) | \
  

• 		MPLL_USER_SEL_C(MUX_STAT_CHANGING))
  

+/* CLK_DIV_CPU0 */ +#define CORE_RATIO(x) (x & 0x7) +#define COREM0_RATIO(x) ((x & 0x7) << 4) +#define COREM1_RATIO(x) ((x & 0x7) << 8) +#define PERIPH_RATIO(x) ((x & 0x7) << 12) +#define ATB_RATIO(x) ((x & 0x7) << 16) +#define PCLK_DBG_RATIO(x) ((x & 0x7) << 20) +#define APLL_RATIO(x) ((x & 0x7) << 24) +#define CORE2_RATIO(x) ((x & 0x7) << 28)

+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CORE(x) (x & 0x1) +#define DIV_COREM0(x) ((x & 0x1) << 4) +#define DIV_COREM1(x) ((x & 0x1) << 8) +#define DIV_PERIPH(x) ((x & 0x1) << 12) +#define DIV_ATB(x) ((x & 0x1) << 16) +#define DIV_PCLK_DBG(x) ((x & 0x1) << 20) +#define DIV_APLL(x) ((x & 0x1) << 24) +#define DIV_CORE2(x) ((x & 0x1) << 28)

+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \

• 		DIV_COREM0(DIV_STAT_CHANGING) | \
  

• 		DIV_COREM1(DIV_STAT_CHANGING) | \
  

• 		DIV_PERIPH(DIV_STAT_CHANGING) | \
  

• 		DIV_ATB(DIV_STAT_CHANGING) | \
  

• 		DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
  

• 		DIV_APLL(DIV_STAT_CHANGING) | \
  

• 		DIV_CORE2(DIV_STAT_CHANGING))
  

+/* CLK_DIV_CPU1 */ +#define COPY_RATIO(x) (x & 0x7) +#define HPM_RATIO(x) ((x & 0x7) << 4) +#define CORES_RATIO(x) ((x & 0x7) << 8)

+/* CLK_DIV_STAT_CPU1 */ +#define DIV_COPY(x) (x & 0x7) +#define DIV_HPM(x) ((x & 0x1) << 4) +#define DIV_CORES(x) ((x & 0x1) << 8)

+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \

• 		DIV_HPM(DIV_STAT_CHANGING) | \
  

• 		DIV_CORES(DIV_STAT_CHANGING))
  

+/* CLK_SRC_DMC */ +#define MUX_C2C_SEL(x) (x & 0x1) +#define MUX_DMC_BUS_SEL(x) ((x & 0x1) << 4) +#define MUX_DPHY_SEL(x) ((x & 0x1) << 8) +#define MUX_MPLL_SEL(x) ((x & 0x1) << 12) +#define MUX_PWI_SEL(x) ((x & 0xf) << 16) +#define MUX_G2D_ACP0_SEL(x) ((x & 0x1) << 20) +#define MUX_G2D_ACP1_SEL(x) ((x & 0x1) << 24) +#define MUX_G2D_ACP_SEL(x) ((x & 0x1) << 28)

+/* CLK_MUX_STAT_DMC */ +#define C2C_SEL(x) ((x) & 0x7) +#define DMC_BUS_SEL(x) ((x & 0x7) << 4) +#define DPHY_SEL(x) ((x & 0x7) << 8) +#define MPLL_SEL(x) ((x & 0x7) << 12) +/* #define PWI_SEL(x) ((x & 0xf) << 16) - Reserved */ +#define G2D_ACP0_SEL(x) ((x & 0x7) << 20) +#define G2D_ACP1_SEL(x) ((x & 0x7) << 24) +#define G2D_ACP_SEL(x) ((x & 0x7) << 28)

+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \

• 		DMC_BUS_SEL(MUX_STAT_CHANGING) | \
  

• 		DPHY_SEL(MUX_STAT_CHANGING) | \
  

• 		MPLL_SEL(MUX_STAT_CHANGING) |\
  

• 		G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
  

• 		G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
  

• 		G2D_ACP_SEL(MUX_STAT_CHANGING))
  

+/* CLK_DIV_DMC0 */ +#define ACP_RATIO(x) (x & 0x7) +#define ACP_PCLK_RATIO(x) ((x & 0x7) << 4) +#define DPHY_RATIO(x) ((x & 0x7) << 8) +#define DMC_RATIO(x) ((x & 0x7) << 12) +#define DMCD_RATIO(x) ((x & 0x7) << 16) +#define DMCP_RATIO(x) ((x & 0x7) << 20)

+/* CLK_DIV_STAT_DMC0 */ +#define DIV_ACP(x) (x & 0x1) +#define DIV_ACP_PCLK(x) ((x & 0x1) << 4) +#define DIV_DPHY(x) ((x & 0x1) << 8) +#define DIV_DMC(x) ((x & 0x1) << 12) +#define DIV_DMCD(x) ((x & 0x1) << 16) +#define DIV_DMCP(x) ((x & 0x1) << 20)

+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \

• 		DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
  

• 		DIV_DPHY(DIV_STAT_CHANGING) | \
  

• 		DIV_DMC(DIV_STAT_CHANGING) | \
  

• 		DIV_DMCD(DIV_STAT_CHANGING) | \
  

• 		DIV_DMCP(DIV_STAT_CHANGING))
  

+/* CLK_DIV_DMC1 */ +#define G2D_ACP_RATIO(x) (x & 0xf) +#define C2C_RATIO(x) ((x & 0x7) << 4) +#define PWI_RATIO(x) ((x & 0xf) << 8) +#define C2C_ACLK_RATIO(x) ((x & 0x7) << 12) +#define DVSEM_RATIO(x) ((x & 0x7f) << 16) +#define DPM_RATIO(x) ((x & 0x7f) << 24)

+/* CLK_DIV_STAT_DMC1 */ +#define DIV_G2D_ACP(x) (x & 0x1) +#define DIV_C2C(x) ((x & 0x1) << 4) +#define DIV_PWI(x) ((x & 0x1) << 8) +#define DIV_C2C_ACLK(x) ((x & 0x1) << 12) +#define DIV_DVSEM(x) ((x & 0x1) << 16) +#define DIV_DPM(x) ((x & 0x1) << 24)

+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \

• 		DIV_C2C(DIV_STAT_CHANGING) | \
  

• 		DIV_PWI(DIV_STAT_CHANGING) | \
  

• 		DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
  

• 		DIV_DVSEM(DIV_STAT_CHANGING) | \
  

• 		DIV_DPM(DIV_STAT_CHANGING))
  

+/* Set CLK_SRC_PERIL0 */ +#define UART4_SEL(x) ((x & 0xf) << 16) +#define UART3_SEL(x) ((x & 0xf) << 12) +#define UART2_SEL(x) ((x & 0xf) << 8) +#define UART1_SEL(x) ((x & 0xf) << 4) +#define UART0_SEL(x) ((x) & 0xf)

+/* Set CLK_DIV_PERIL0 */ +#define UART4_RATIO(x) ((x & 0xf) << 16) +#define UART3_RATIO(x) ((x & 0xf) << 12) +#define UART2_RATIO(x) ((x & 0xf) << 8) +#define UART1_RATIO(x) ((x & 0xf) << 4) +#define UART0_RATIO(x) ((x) & 0xf)

+/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART4(x) ((x & 0x1) << 16) +#define DIV_UART3(x) ((x & 0x1) << 12) +#define DIV_UART2(x) ((x & 0x1) << 8) +#define DIV_UART1(x) ((x & 0x1) << 4) +#define DIV_UART0(x) ((x) & 0x1)

+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \

• 			DIV_UART3(DIV_STAT_CHANGING) | \
  

• 			DIV_UART2(DIV_STAT_CHANGING) | \
  

• 			DIV_UART1(DIV_STAT_CHANGING) | \
  

• 			DIV_UART0(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0xf) +#define MMC0_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC1_RATIO(x) ((x & 0xf) << 16) +#define MMC1_PRE_RATIO(x) ((x & 0xff) << 24)

+/* CLK_DIV_STAT_FSYS1 */ +#define DIV_MMC0(x) ((x) & 1) +#define DIV_MMC0_PRE(x) ((x & 1) << 8) +#define DIV_MMC1(x) ((x & 1) << 16) +#define DIV_MMC1_PRE(x) ((x & 1) << 24)

+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \

• 			DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC1(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC1_PRE(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO(x) (x & 0xf) +#define MMC2_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC3_RATIO(x) ((x & 0xf) << 16) +#define MMC3_PRE_RATIO(x) ((x & 0xff) << 24)

+/* CLK_DIV_STAT_FSYS2 */ +#define DIV_MMC2(x) (x & 0x1) +#define DIV_MMC2_PRE(x) ((x & 0x1) << 8) +#define DIV_MMC3(x) ((x & 0x1) << 16) +#define DIV_MMC3_PRE(x) ((x & 0x1) << 24)

+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \

• 			DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC3(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC3_PRE(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO(x) (x & 0x7) +#define MMC4_PRE_RATIO(x) ((x & 0xff) << 8)

+/* CLK_DIV_STAT_FSYS3 */ +#define DIV_MMC4(x) (x & 0x1) +#define DIV_MMC4_PRE(x) ((x & 0x1) << 8)

+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \

• 			DIV_MMC4_PRE(DIV_STAT_CHANGING))
  

+#endif /*__ODROIDU3_SETUP__ */

1.9.1

It is possible to boot from a few media devices, especially using a micro SD or eMMC slots. In this situation, boot device should be registered as block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com --- board/samsung/common/board.c | 32 ++++++++++++++++++++++++-------- include/samsung/misc.h | 5 +++++ 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..2970340 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -25,6 +25,8 @@ #include <lcd.h> #include <samsung/misc.h>

+static int bootmode; + DECLARE_GLOBAL_DATA_PTR;

int __exynos_early_init_f(void) @@ -243,19 +245,33 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { int ret; + struct exynos4_power *pwr = (struct exynos4_power *) + samsung_get_base_power(); + + bootmode = BOOT_MODE(readl(&pwr->om_stat)); + if (bootmode == BOOT_SDMMC) { +#ifdef CONFIG_SDHCI + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); +#endif #ifdef CONFIG_DWMMC - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); +#endif + } else { +#ifdef CONFIG_DWMMC + /* dwmmc initializattion for available channels */ + ret = exynos_dwmmc_init(gd->fdt_blob); #endif - #ifdef CONFIG_SDHCI - /* mmc initializattion for available channels */ - ret = exynos_mmc_init(gd->fdt_blob); + /* mmc initializattion for available channels */ + ret = exynos_mmc_init(gd->fdt_blob); +#endif + } + if (ret) debug("mmc init failed\n"); -#endif + return ret; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 10653a1..87b53ec 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -28,4 +28,9 @@ void check_boot_mode(void); void draw_logo(void); #endif

+#define BOOT_SDMMC 0x2 +#define BOOT_MODE_MASK (0x1f) +#define BOOT_MODE_SHIFT (0x1) +#define BOOT_MODE(x) ((x >> BOOT_MODE_SHIFT) & BOOT_MODE_MASK) + #endif /* __SAMSUNG_MISC_COMMON_H__ */

Hello Minkyu, On 06/18/2014 08:30 AM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,

On 12/06/14 18:46, Przemyslaw Marczak wrote:

...

It is possible to boot from a few media devices, especially using a micro SD or eMMC slots. In this situation, boot device should be registered as block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

---

board/samsung/common/board.c | 32 ++++++++++++++++++++++++-------- include/samsung/misc.h | 5 +++++ 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..2970340 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -25,6 +25,8 @@ #include <lcd.h> #include <samsung/misc.h>

+static int bootmode;

• DECLARE_GLOBAL_DATA_PTR;

  int __exynos_early_init_f(void)

@@ -243,19 +245,33 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { int ret;

• struct exynos4_power *pwr = (struct exynos4_power *)

• 			samsung_get_base_power();
  

Hm, no. This file is samsung common not only for exynos4. Although this code will not be made any problems for other SoCs (because om_stat is always first item of power), it looks weird. I think you can make new function for getting boot mode.

Yes, this was bad. What about that: # unsigned int om_stat = samsung_get_base_power(); # # bootmode = BOOT_MODE(readl(om_stat));

or maybe just

# bootmode = BOOT_MODE(readl(samsung_get_base_power()));

like in the Exynos spl code.

Simply and proper for every SOC. And a function for this code will be added.

...

• bootmode = BOOT_MODE(readl(&pwr->om_stat));
• if (bootmode == BOOT_SDMMC) {

+#ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif #ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
• ret = exynos_dwmmc_init(gd->fdt_blob);
• if (ret)

• debug("dwmmc init failed\n");
  

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

+#endif

• } else {

+#ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

  #endif

• #ifdef CONFIG_SDHCI
• /* mmc initializattion for available channels */
• ret = exynos_mmc_init(gd->fdt_blob);

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif

• }
• if (ret) debug("mmc init failed\n");

-#endif

• return ret; } #endif

diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 10653a1..87b53ec 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -28,4 +28,9 @@ void check_boot_mode(void); void draw_logo(void); #endif

+#define BOOT_SDMMC 0x2 +#define BOOT_MODE_MASK (0x1f) +#define BOOT_MODE_SHIFT (0x1) +#define BOOT_MODE(x) ((x >> BOOT_MODE_SHIFT) & BOOT_MODE_MASK)

((x) >> BOOT_MODE_SHIFT)

Ok, will fix this.

...

• #endif /* __SAMSUNG_MISC_COMMON_H__ */

Thanks, Minkyu Kang.

Thank you,

This patch introduces new feature: initialization of the dfu bootloader entity from a separate environmental variable which can be set on a boot time.

By default, DFU always check environmental variable: $dfu_alt_info.

Changes: - DFU will also look for environmental variable: $dfu_alt_bootloader - if any of dfu_alt_* variable is properly defined, then function dfu_init_env_entities() will return success.

Use case: Some devices can boot from various media type (SD, eMMC, NAND, etc.) or some board configs are common for more than one board type. In a such case, bootloader is probably placed on a different devices or even offsets. So such DFU feature is welcome.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

--- Changes v2: - new commit --- drivers/dfu/dfu.c | 28 ++++++++++++++++++---------- 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index a938109..8848624 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -44,24 +44,32 @@ static int dfu_find_alt_num(const char *s)

int dfu_init_env_entities(char *interface, int dev) { + const char *alt_info[] = {"dfu_alt_info", "dfu_alt_bootloader"}; const char *str_env; char *env_bkp; - int ret; + int ret, i; + int alt_init_cnt = 0; + + for (i = 0; i < ARRAY_SIZE(alt_info); i++) { + str_env = getenv(alt_info[i]); + if (!str_env) + continue;

- str_env = getenv("dfu_alt_info"); - if (!str_env) { - error(""dfu_alt_info" env variable not defined!\n"); - return -EINVAL; + env_bkp = strdup(str_env); + ret = dfu_config_entities(env_bkp, interface, dev); + free(env_bkp); + + if (ret) + continue; + + alt_init_cnt++; }

- env_bkp = strdup(str_env); - ret = dfu_config_entities(env_bkp, interface, dev); - if (ret) { + if (!alt_init_cnt) { error("DFU entities configuration failed!\n"); - return ret; + return -1; }

- free(env_bkp); return 0; }

On an Odroid U3 board, the SOC is unable to reset an eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com --- arch/arm/lib/reset.c | 7 +++++++ include/common.h | 1 + 2 files changed, 8 insertions(+)

diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a03580..3b39466 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,11 @@

#include <common.h>

+void __reset_misc(void) {} + +void reset_misc(void) + __attribute((weak, alias("__reset_misc"))); + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { puts ("resetting ...\n"); @@ -30,6 +35,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) udelay (50000); /* wait 50 ms */

disable_interrupts(); + + reset_misc(); reset_cpu(0);

/*NOTREACHED*/ diff --git a/include/common.h b/include/common.h index 232136c..04bab78 100644 --- a/include/common.h +++ b/include/common.h @@ -629,6 +629,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_misc (void); void reset_cpu (ulong addr); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd);

For support of multiple board types in a one config - it is welcome to display the current board model. This is what get_board_type() should return.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com --- board/samsung/common/board.c | 5 ++++- include/samsung/misc.h | 1 + 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 87d42e5..5cb86a4 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -283,7 +283,10 @@ int checkboard(void)

board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); printf("Board: %s\n", board_name ? board_name : "unknown"); - +#ifdef CONFIG_BOARD_TYPES + const char *board_type = get_board_type(); + printf("Model: %s\n", board_type ? board_type : "unknown"); +#endif return 0; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 914137e..a302432 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -37,6 +37,7 @@ void draw_logo(void); void set_dfu_alt_boot(int bootmode); #endif #ifdef CONFIG_BOARD_TYPES +const char *get_board_type(void); const char *get_board_type_fdt(void); #endif

This is a standard description for Odroid boards.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com --- arch/arm/dts/Makefile | 3 +- arch/arm/dts/exynos4412-odroid.dts | 70 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/exynos4412-odroid.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5554615..32cb6f5 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,7 +1,8 @@ dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ - exynos4412-trats2.dtb + exynos4412-trats2.dtb \ + exynos4412-odroid.dtb

dtb-$(CONFIG_EXYNOS5) += exynos5250-arndale.dtb \ exynos5250-snow.dtb \ diff --git a/arch/arm/dts/exynos4412-odroid.dts b/arch/arm/dts/exynos4412-odroid.dts new file mode 100644 index 0000000..24d0bf1 --- /dev/null +++ b/arch/arm/dts/exynos4412-odroid.dts @@ -0,0 +1,70 @@ +/* + * Odroid-U3/X2 board device tree source + * + * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Odroid based on Exynos4412"; + compatible = "samsung,odroid", "samsung,exynos4412"; + + aliases { + i2c0 = "/i2c@13860000"; + serial0 = "/serial@13800000"; + console = "/serial@13810000"; + mmc2 = "sdhci@12530000"; + mmc4 = "dwmmc@12550000"; + }; + + i2c@13860000 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + status = "okay"; + + max77686_pmic@09 { + compatible = "maxim,max77686_pmic"; + interrupts = <7 0>; + reg = <0x09 0 0>; + #clock-cells = <1>; + }; + }; + + serial@13810000 { + status = "okay"; + }; + + sdhci@12510000 { + status = "disabled"; + }; + + sdhci@12520000 { + status = "disabled"; + }; + + sdhci@12530000 { + samsung,bus-width = <4>; + samsung,timing = <1 2 3>; + cd-gpios = <&gpio 0xC2 0>; + }; + + sdhci@12540000 { + status = "disabled"; + }; + + dwmmc@12550000 { + samsung,bus-width = <8>; + samsung,timing = <2 1 0>; + samsung,removable = <0>; + fifoth_val = <0x203f0040>; + bus_hz = <400000000>; + div = <0x3>; + index = <4>; + }; +};

It is possible to boot from a few media devices, especially using a micro SD or eMMC slots. In this situation depends on a boot device - some setup can be changeg.

This change adds function: boot_device() - which returns an OM[1:5] bits value

This allows checking if boot device is SD(0x2).

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

--- Changes v3: - new commit after separate one into two --- board/samsung/common/board.c | 10 +++++++++- include/samsung/misc.h | 7 +++++++ 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..ecf3f76 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -41,6 +41,13 @@ int __exynos_power_init(void) int exynos_power_init(void) __attribute__((weak, alias("__exynos_power_init")));

+unsigned int boot_device(void) +{ + unsigned int om_stat = samsung_get_base_power(); + + return BOOT_DEVICE(readl(om_stat)); +} + #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ static void boot_temp_check(void) @@ -243,19 +250,20 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { int ret; + #ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); if (ret) debug("dwmmc init failed\n"); #endif - #ifdef CONFIG_SDHCI /* mmc initializattion for available channels */ ret = exynos_mmc_init(gd->fdt_blob); if (ret) debug("mmc init failed\n"); #endif + return ret; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 10653a1..57bac7d 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -28,4 +28,11 @@ void check_boot_mode(void); void draw_logo(void); #endif

+#define BOOT_DEVICE_SDMMC 0x2 +#define BOOT_DEVICE_MASK 0x1f +#define BOOT_DEVICE_SHIFT 0x1 +#define BOOT_DEVICE(x) (((x) >> BOOT_DEVICE_SHIFT) & BOOT_DEVICE_MASK) + +unsigned int boot_device(void); + #endif /* __SAMSUNG_MISC_COMMON_H__ */

Dear Minkyu,

On 06/27/2014 11:40 AM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,

On 26/06/14 23:15, Przemyslaw Marczak wrote:

...

It is possible to boot from a few media devices, especially using a micro SD or eMMC slots. In this situation depends on a boot device - some setup can be changeg.

This change adds function: boot_device() - which returns an OM[1:5] bits value

This allows checking if boot device is SD(0x2).

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

---

Changes v3:

• new commit after separate one into two

---

board/samsung/common/board.c | 10 +++++++++- include/samsung/misc.h | 7 +++++++ 2 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..ecf3f76 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -41,6 +41,13 @@ int __exynos_power_init(void) int exynos_power_init(void) __attribute__((weak, alias("__exynos_power_init")));

+unsigned int boot_device(void) +{

• unsigned int om_stat = samsung_get_base_power();
• return BOOT_DEVICE(readl(om_stat));

+}

• #if defined CONFIG_EXYNOS_TMU /* Boot Time Thermal Analysis for SoC temperature threshold breach */ static void boot_temp_check(void)

@@ -243,19 +250,20 @@ int board_eth_init(bd_t *bis) int board_mmc_init(bd_t *bis) { int ret;

• #ifdef CONFIG_DWMMC /* dwmmc initializattion for available channels */ ret = exynos_dwmmc_init(gd->fdt_blob); if (ret) debug("dwmmc init failed\n"); #endif

• #ifdef CONFIG_SDHCI /* mmc initializattion for available channels */ ret = exynos_mmc_init(gd->fdt_blob); if (ret) debug("mmc init failed\n"); #endif

• return ret; } #endif

diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 10653a1..57bac7d 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -28,4 +28,11 @@ void check_boot_mode(void); void draw_logo(void); #endif

+#define BOOT_DEVICE_SDMMC 0x2 +#define BOOT_DEVICE_MASK 0x1f +#define BOOT_DEVICE_SHIFT 0x1 +#define BOOT_DEVICE(x) (((x) >> BOOT_DEVICE_SHIFT) & BOOT_DEVICE_MASK)

+unsigned int boot_device(void);

Hm, do we need to make this function to non-static? If so, it should be placed in power.c - get_om_stat()?

Thanks, Minkyu Kang.

It is non-static because it is called also outside this file, so I will move it to power.c.

Thank you,

Dear Przemyslaw Marczak,

On 26/06/14 23:15, Przemyslaw Marczak wrote:

It is possible to boot device using a micro SD or eMMC slots. In this situation, boot device should be registered as a block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

Changes V3:

• separate two changes into two commits

---

board/samsung/common/board.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index ecf3f76..f07a900 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -251,18 +251,28 @@ int board_mmc_init(bd_t *bis) { int ret;

• if (boot_device() == BOOT_DEVICE_SDMMC) {

+#ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif #ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
• ret = exynos_dwmmc_init(gd->fdt_blob);
• if (ret)

• debug("dwmmc init failed\n");
  

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

+#endif

• } else {

+#ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

#endif #ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
• ret = exynos_mmc_init(gd->fdt_blob);

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif

• }

It looks little confused. Could you please re-arrange this code like this?

#ifdef CONFIG_SDHCI if (boot....) {

} else {

} #endif

#ifdef CONFIG_DWMMC if (boot....) {

} else {

} #endif

Thanks, Minkyu Kang.

hello Jaehoon,

On 06/27/2014 11:45 AM, Jaehoon Chung wrote:

On 06/27/2014 06:40 PM, Minkyu Kang wrote:

...

Dear Przemyslaw Marczak,

On 26/06/14 23:15, Przemyslaw Marczak wrote:

...

It is possible to boot device using a micro SD or eMMC slots. In this situation, boot device should be registered as a block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

Changes V3:

• separate two changes into two commits

---

board/samsung/common/board.c | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index ecf3f76..f07a900 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -251,18 +251,28 @@ int board_mmc_init(bd_t *bis) { int ret;

• if (boot_device() == BOOT_DEVICE_SDMMC) {

+#ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif #ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
• ret = exynos_dwmmc_init(gd->fdt_blob);
• if (ret)

• debug("dwmmc init failed\n");
  

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

+#endif

• } else {

+#ifdef CONFIG_DWMMC

• /* dwmmc initializattion for available channels */
  

• ret = exynos_dwmmc_init(gd->fdt_blob);
  

  #endif #ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
• ret = exynos_mmc_init(gd->fdt_blob);

• /* mmc initializattion for available channels */
  

• ret = exynos_mmc_init(gd->fdt_blob);
  

+#endif

• }

It looks little confused. Could you please re-arrange this code like this?

If re-arrange the below code, i want to call the dwmmc-init function at first. Is there a special reason for sequence(sdhci->dwmmc)?

Best Regards, Jaehoon Chung

Please look at my proposed solution in the reply to Minkyu email.

Thanks,

This change introduces new common function: - set_dfu_alt_info() - put dfu system and bootloader setting into $dfu_alt_info. functions declaration: - char *get_dfu_alt_system(void) - char *get_dfu_alt_boot(void) - void set_dfu_alt_info(void) and new config: - CONFIG_SET_DFU_ALT_INFO

This function can be used for auto setting dfu configuration on boot. Such feature is useful for multi board support by one u-boot binary. Each board should define two functions: - get_dfu_alt_system() - get_dfu_alt_boot()

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

--- Changes v2: - change config names: CONFIG_SET_DFU_BOOT_ALT to CONFIG_DFU_ALT_BOOTLOADER and CONFIG_DFU_BOOT_ALT_* to CONFIG_DFU_ALT_BOOT_* - change function name: set_dfu_boot_alt() to set_dfu_alt_boot() - remove superfluous ifdefs

Changes v3: - set $dfu_alt_info at every boot - new config: CONFIG_SET_DFU_ALT_INFO - update commit msg --- board/samsung/common/misc.c | 36 ++++++++++++++++++++++++++++++++++++ include/samsung/misc.h | 6 ++++++ 2 files changed, 42 insertions(+)

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index a453a82..166ea83 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -11,6 +11,7 @@ #include <samsung/misc.h> #include <errno.h> #include <version.h> +#include <malloc.h> #include <linux/sizes.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> @@ -21,6 +22,41 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SET_DFU_ALT_INFO +void set_dfu_alt_info(void) +{ + char *alt_boot = NULL; + char *alt_system = NULL; + char *buf = NULL; + int buf_len; + + puts("DFU alt info setting: "); + + alt_boot = get_dfu_alt_boot(); + if (!alt_boot) + goto error; + + alt_system = get_dfu_alt_system(); + if (!alt_system) + goto error; + + buf_len = strlen(alt_boot) + strlen(alt_system) + 2; + buf = malloc(buf_len); + + sprintf(buf, "%s;%s", alt_boot, alt_system); + setenv("dfu_alt_info", buf); + + free(buf); + + puts("done\n"); + + return; +error: + puts("error\n"); + setenv("dfu_alt_info", "Settings not found!"); +} +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG void set_board_info(void) { diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 57bac7d..c3fcc29 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -35,4 +35,10 @@ void draw_logo(void);

unsigned int boot_device(void);

+#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void); +char *get_dfu_alt_boot(void); +void set_dfu_alt_info(void); +#endif + #endif /* __SAMSUNG_MISC_COMMON_H__ */

On an Odroid U3 board, the SOC is unable to reset the eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com --- arch/arm/lib/reset.c | 7 +++++++ include/common.h | 1 + 2 files changed, 8 insertions(+)

diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a03580..3b39466 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,11 @@

#include <common.h>

+void __reset_misc(void) {} + +void reset_misc(void) + __attribute((weak, alias("__reset_misc"))); + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { puts ("resetting ...\n"); @@ -30,6 +35,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) udelay (50000); /* wait 50 ms */

disable_interrupts(); + + reset_misc(); reset_cpu(0);

/*NOTREACHED*/ diff --git a/include/common.h b/include/common.h index 232136c..04bab78 100644 --- a/include/common.h +++ b/include/common.h @@ -629,6 +629,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_misc (void); void reset_cpu (ulong addr); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd);

On 06/27/2014 11:40 AM, Minkyu Kang wrote:

Dear Przemyslaw Marczak,

On 26/06/14 23:15, Przemyslaw Marczak wrote:

...

On an Odroid U3 board, the SOC is unable to reset the eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com

---

arch/arm/lib/reset.c | 7 +++++++ include/common.h | 1 + 2 files changed, 8 insertions(+)

diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a03580..3b39466 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,11 @@

#include <common.h>

+void __reset_misc(void) {}

+void reset_misc(void)

• __attribute((weak, alias("__reset_misc")));
• int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { puts ("resetting ...\n");

@@ -30,6 +35,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) udelay (50000); /* wait 50 ms */

disable_interrupts();

• reset_misc(); reset_cpu(0);

  /*NOTREACHED*/

diff --git a/include/common.h b/include/common.h index 232136c..04bab78 100644 --- a/include/common.h +++ b/include/common.h @@ -629,6 +629,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_misc (void); void reset_cpu (ulong addr); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd);

I'm not sure that we really need to add this function to arm common. We can do this in reset_cpu (arch/arm/cpu/armv7/exynos/soc.c). But if other SoCs also need to add such things then, it can be added as arm common.

Thanks, Minkyu Kang.

No one used this before, so probably better is to move it into exynos soc.c code.

Thank you,

Hello Jeroen,

On 06/27/2014 10:20 PM, Jeroen Hofstee wrote:

Hello Przemyslaw,

On 27-06-14 13:34, Przemyslaw Marczak wrote:

...

On 06/27/2014 11:40 AM, Minkyu Kang wrote:

...

Dear Przemyslaw Marczak,

On 26/06/14 23:15, Przemyslaw Marczak wrote:

...

On an Odroid U3 board, the SOC is unable to reset the eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com

---

arch/arm/lib/reset.c | 7 +++++++ include/common.h | 1 + 2 files changed, 8 insertions(+)

diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a03580..3b39466 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,11 @@

#include <common.h>

+void __reset_misc(void) {}

+void reset_misc(void)

• __attribute((weak, alias("__reset_misc")));

can you please use __weak here and provide a prototype, wherever it ends up in the end. It prevents 3 warnings and makes it type safe..

Regards, Jeroen

Thanks, I will add the __weak prefix there.

The prototype of this new function is in file common.h, so this is type safe.

I checked the compilation with options: -W and -pedantic on two configs: trats and odroid, and there was no warnings about the function reset_misc.

Thank you,

This change adds declaration of functions: - set_board_type() - called at checkboard() - get_board_type() - called at checkboard() - get_board_name()

For supporting multiple board types in a one config - it is welcome to display the current board model. This is what get_board_type() should return.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

--- Changes v3: - change the commit order - include/samsung/misc.h: add new functions declaration - update a commit message --- board/samsung/common/board.c | 7 +++++++ include/samsung/misc.h | 5 +++++ 2 files changed, 12 insertions(+)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index fd5f21f..f2dbfa0 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -96,6 +96,7 @@ int board_init(void) #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif + return exynos_init(); }

@@ -285,7 +286,13 @@ int checkboard(void)

board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); printf("Board: %s\n", board_name ? board_name : "unknown"); +#ifdef CONFIG_BOARD_TYPES + set_board_type(); + + const char *board_type = get_board_type();

+ printf("Model: %s\n", board_type ? board_type : "unknown"); +#endif return 0; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index c3fcc29..fcec5ea 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -40,5 +40,10 @@ char *get_dfu_alt_system(void); char *get_dfu_alt_boot(void); void set_dfu_alt_info(void); #endif +#ifdef CONFIG_BOARD_TYPES +void set_board_type(void); +const char *get_board_type(void); +const char *get_board_name(void); +#endif

#endif /* __SAMSUNG_MISC_COMMON_H__ */

On 06/27/2014 11:40 AM, Minkyu Kang wrote:

On 26/06/14 23:15, Przemyslaw Marczak wrote:

...

This change adds declaration of functions:

• set_board_type() - called at checkboard()
• get_board_type() - called at checkboard()
• get_board_name()

For supporting multiple board types in a one config - it is welcome to display the current board model. This is what get_board_type() should return.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

---

Changes v3:

• change the commit order
• include/samsung/misc.h: add new functions declaration
• update a commit message

---

board/samsung/common/board.c | 7 +++++++ include/samsung/misc.h | 5 +++++ 2 files changed, 12 insertions(+)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index fd5f21f..f2dbfa0 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -96,6 +96,7 @@ int board_init(void) #ifdef CONFIG_EXYNOS_SPI spi_init(); #endif

• return exynos_init(); }

@@ -285,7 +286,13 @@ int checkboard(void)

board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL); printf("Board: %s\n", board_name ? board_name : "unknown"); +#ifdef CONFIG_BOARD_TYPES

• set_board_type();
• const char *board_type = get_board_type();

please don't declare local variable at middle of function.

ok, I will fix this.

...

• printf("Model: %s\n", board_type ? board_type : "unknown");

+#endif return 0; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index c3fcc29..fcec5ea 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -40,5 +40,10 @@ char *get_dfu_alt_system(void); char *get_dfu_alt_boot(void); void set_dfu_alt_info(void); #endif +#ifdef CONFIG_BOARD_TYPES +void set_board_type(void); +const char *get_board_type(void); +const char *get_board_name(void); +#endif

#endif /* __SAMSUNG_MISC_COMMON_H__ */

Thank you for review.

Regards,

This board file supports standard features of Odroid X2 and U3 boards: - Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz, - MAX77686 power regulator, - USB PHY, - enable XCL205 - power for board peripherials - check board type: U3 or X2. - enable Odroid U3 FAN cooler

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com

--- Changes v2: - enable fan on odroid U3

Changes v3: - odroid.c: clean up board name related code - odroid.c: remove static from set_board_type() - odroid.c: add implementation of functions: get_dfu_alt_* - odroid.c: include misc.h --- board/samsung/odroid/Makefile | 8 + board/samsung/odroid/odroid.c | 466 ++++++++++++++++++++++++++++++++++++++++++ board/samsung/odroid/setup.h | 227 ++++++++++++++++++++ 3 files changed, 701 insertions(+) create mode 100644 board/samsung/odroid/Makefile create mode 100644 board/samsung/odroid/odroid.c create mode 100644 board/samsung/odroid/setup.h

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile new file mode 100644 index 0000000..b98aaeb --- /dev/null +++ b/board/samsung/odroid/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# Przemyslaw Marczak p.marczak@samsung.com +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := odroid.o diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c new file mode 100644 index 0000000..a85f2f6 --- /dev/null +++ b/board/samsung/odroid/odroid.c @@ -0,0 +1,466 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak p.marczak@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/cpu.h> +#include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <errno.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <samsung/misc.h> +#include "setup.h" + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_TYPES +/* Odroid board types */ +enum { + ODROID_TYPE_U3, + ODROID_TYPE_X2, +}; + +void set_board_type(void) +{ + int val; + + /* Check GPC1 pin 2 */ + gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE); + gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X); + gpio_direction_input(EXYNOS4X12_GPIO_C12); + + /* XCL205 - needs some latch time */ + mdelay(10); + + /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */ + val = gpio_get_value(EXYNOS4X12_GPIO_C12); + if (val) + gd->board_type = ODROID_TYPE_X2; + else + gd->board_type = ODROID_TYPE_U3; +} + +const char *get_board_name(void) +{ + const char *board_name = "odroid"; + + return board_name; +} + +const char *get_board_type(void) +{ + const char *board_type[] = {"u3", "x2"}; + + return board_type[gd->board_type]; +} +#endif + +#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void) +{ + return getenv("dfu_alt_system"); +} + +char *get_dfu_alt_boot(void) +{ + char *alt_boot = NULL; + + switch (boot_device()) { + case BOOT_DEVICE_SDMMC: + alt_boot = CONFIG_DFU_ALT_BOOT_SD; + break; + default: + alt_boot = CONFIG_DFU_ALT_BOOT_EMMC; + break; + } + + if (!alt_boot) + return NULL; + + setenv("dfu_alt_boot", alt_boot); + + return alt_boot; +} +#endif + +static void board_clock_init(void) +{ + unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; + struct exynos4x12_clock *clk = (struct exynos4x12_clock *) + samsung_get_base_clock(); + + /* + * CMU_CPU clocks src to MPLL + * Bit values: 0 ; 1 + * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL + * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL + * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C + * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL + */ + clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) | + MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1); + set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | + MUX_MPLL_USER_SEL_C(1); + + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) + continue; + + /* Set APLL to 1000MHz */ + clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1); + set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); + + clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); + + /* Wait for PLL to be locked */ + while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Set CMU_CPU clocks src to APLL */ + set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | + MUX_MPLL_USER_SEL_C(1); + clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) + continue; + + set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | + PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | + APLL_RATIO(0) | CORE2_RATIO(0); + /* + * Set dividers for MOUTcore = 1000 MHz + * coreout = MOUT / (ratio + 1) = 1000 MHz (0) + * corem0 = armclk / (ratio + 1) = 333 MHz (2) + * corem1 = armclk / (ratio + 1) = 166 MHz (5) + * periph = armclk / (ratio + 1) = 1000 MHz (0) + * atbout = MOUT / (ratio + 1) = 200 MHz (4) + * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) + * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) + * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) + */ + clr = CORE_RATIO(0x7) | COREM0_RATIO(0x7) | COREM1_RATIO(0x7) | + PERIPH_RATIO(0x7) | ATB_RATIO(0x7) | PCLK_DBG_RATIO(0x7) | + APLL_RATIO(0x7) | CORE2_RATIO(0x7); + + clrsetbits_le32(&clk->div_cpu0, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) + continue; + + /* + * For MOUThpm = 1000 MHz (MOUTapll) + * doutcopy = MOUThpm / (ratio + 1) = 200 (4) + * sclkhpm = doutcopy / (ratio + 1) = 200 (4) + * cores_out = armclk / (ratio + 1) = 1000 (0) + */ + clr = COPY_RATIO(0x7) | HPM_RATIO(0x7) | CORES_RATIO(0x7); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0); + + clrsetbits_le32(&clk->div_cpu1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) + continue; + + /* + * Set CMU_DMC clocks src to APLL + * Bit values: 0 ; 1 + * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL + * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL + * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL + * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT + * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) + * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL + * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL + * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 + */ + clr_src_dmc = MUX_C2C_SEL(0x1) | MUX_DMC_BUS_SEL(0x1) | + MUX_DPHY_SEL(0x1) | MUX_MPLL_SEL(0x1) | + MUX_PWI_SEL(0xf) | MUX_G2D_ACP0_SEL(0x1) | + MUX_G2D_ACP1_SEL(0x1) | MUX_G2D_ACP_SEL(0x1); + set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | + MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | + MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); + + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) + continue; + + /* Set MPLL to 800MHz */ + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); + + clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); + + /* Wait for PLL to be locked */ + while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) + continue; + + /* Switch back CMU_DMC mux */ + set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | + MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | + MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); + + clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); + + /* Wait for mux change */ + while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) + continue; + + /* CLK_DIV_DMC0 */ + clr = ACP_RATIO(0x7) | ACP_PCLK_RATIO(0x7) | DPHY_RATIO(0x7) | + DMC_RATIO(0x7) | DMCD_RATIO(0x7) | DMCP_RATIO(0x7); + /* + * For: + * MOUTdmc = 800 MHz + * MOUTdphy = 800 MHz + * + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) + */ + set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | + DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); + + clrsetbits_le32(&clk->div_dmc0, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) + continue; + + /* CLK_DIV_DMC1 */ + clr = G2D_ACP_RATIO(0xf) | C2C_RATIO(0x7) | PWI_RATIO(0xf) | + C2C_ACLK_RATIO(0x7) | DVSEM_RATIO(0x7f) | DPM_RATIO(0x7f); + /* + * For: + * MOUTg2d = 800 MHz + * MOUTc2c = 800 Mhz + * MOUTpwi = 108 MHz + * + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) + * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) + */ + set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); + + clrsetbits_le32(&clk->div_dmc1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) + continue; + + /* CLK_SRC_PERIL0 */ + clr = UART0_SEL(0xf) | UART1_SEL(0xf) | UART2_SEL(0xf) | + UART3_SEL(0xf) | UART4_SEL(0xf); + /* + * Set CLK_SRC_PERIL0 clocks src to MPLL + * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); + * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); + * 8(SCLK_VPLL) + * + * Set all to SCLK_MPLL_USER_T + */ + set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | + UART4_SEL(6); + + clrsetbits_le32(&clk->src_peril0, clr, set); + + /* CLK_DIV_PERIL0 */ + clr = UART0_RATIO(0xf) | UART1_RATIO(0xf) | UART2_RATIO(0xf) | + UART3_RATIO(0xf) | UART4_RATIO(0xf); + /* + * For MOUTuart0-4: 800MHz + * + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) + */ + set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | + UART3_RATIO(7) | UART4_RATIO(7); + + clrsetbits_le32(&clk->div_peril0, clr, set); + + while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) + continue; + + /* CLK_DIV_FSYS1 */ + clr = MMC0_RATIO(0xf) | MMC0_PRE_RATIO(0xff) | MMC1_RATIO(0xf) | + MMC1_PRE_RATIO(0xff); + /* + * For MOUTmmc0-3 = 800 MHz (MPLL) + * + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) + */ + set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | + MMC1_PRE_RATIO(1); + + clrsetbits_le32(&clk->div_fsys1, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) + continue; + + /* CLK_DIV_FSYS2 */ + clr = MMC2_RATIO(0xf) | MMC2_PRE_RATIO(0xff) | MMC3_RATIO(0xf) | + MMC3_PRE_RATIO(0xff); + /* + * For MOUTmmc0-3 = 800 MHz (MPLL) + * + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) + */ + set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | + MMC3_PRE_RATIO(1); + + clrsetbits_le32(&clk->div_fsys2, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) + continue; + + /* CLK_DIV_FSYS3 */ + clr = MMC4_RATIO(0xf) | MMC4_PRE_RATIO(0xff); + /* + * For MOUTmmc4 = 800 MHz (MPLL) + * + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) + */ + set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); + + clrsetbits_le32(&clk->div_fsys3, clr, set); + + /* Wait for divider ready status */ + while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) + continue; + + return; +} + +static void board_gpio_init(void) +{ + /* Set GPA1 pin 1 to HI - enable XCL205 output */ + gpio_set_pull(EXYNOS4X12_GPIO_A11, S5P_GPIO_PULL_UP); + gpio_set_drv(EXYNOS4X12_GPIO_A11, S5P_GPIO_DRV_4X); + gpio_direction_output(EXYNOS4X12_GPIO_A11, 1); + + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); + gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); + gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); + + /* Enable FAN (Odroid U3) */ + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); + gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); + gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); +} + +static int pmic_init_max77686(void) +{ + struct pmic *p = pmic_get("MAX77686_PMIC"); + + if (pmic_probe(p)) + return -ENODEV; + + /* Set LDO Voltage */ + max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */ + max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */ + max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */ + + return 0; +} + +#ifdef CONFIG_SYS_I2C_INIT_BOARD +static void board_init_i2c(void) +{ + /* I2C_0 */ + if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE)) + debug("I2C%d not configured\n", (I2C_0)); +} +#endif + +int exynos_early_init_f(void) +{ + board_clock_init(); + board_gpio_init(); + + return 0; +} + +int exynos_init(void) +{ + return 0; +} + +int exynos_power_init(void) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD + board_init_i2c(); +#endif + pmic_init(I2C_0); + pmic_init_max77686(); + + return 0; +} + +#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{ + struct pmic *p_pmic; + + p_pmic = pmic_get("MAX77686_PMIC"); + if (!p_pmic) + return -ENODEV; + + if (pmic_probe(p_pmic)) + return -1; + + if (on) + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON); + else + return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM); +} + +struct s3c_plat_otg_data s5pc210_otg_data = { + .phy_control = s5pc210_phy_control, + .regs_phy = EXYNOS4X12_USBPHY_BASE, + .regs_otg = EXYNOS4X12_USBOTG_BASE, + .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL, + .usb_flags = PHY0_SLEEP, +}; + +int board_usb_init(int index, enum usb_init_type init) +{ + debug("USB_udc_probe\n"); + return s3c_udc_probe(&s5pc210_otg_data); +} +#endif + +void reset_misc(void) +{ + /* Reset eMMC*/ + gpio_set_value(EXYNOS4X12_GPIO_K12, 0); + mdelay(10); + gpio_set_value(EXYNOS4X12_GPIO_K12, 1); +} diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h new file mode 100644 index 0000000..982d676 --- /dev/null +++ b/board/samsung/odroid/setup.h @@ -0,0 +1,227 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Przemyslaw Marczak p.marczak@samsung.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ODROIDU3_SETUP__ +#define __ODROIDU3_SETUP__ + +/* A/M PLL_CON0 */ +#define SDIV(x) (x & 0x7) +#define PDIV(x) ((x & 0x3f) << 8) +#define MDIV(x) ((x & 0x3ff) << 16) +#define FSEL(x) ((x & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) ((x & 0x1) << 31) + +/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) (x & 0x1) +#define MUX_CORE_SEL(x) ((x & 0x1) << 16) +#define MUX_HPM_SEL(x) ((x & 0x1) << 20) +#define MUX_MPLL_USER_SEL_C(x) ((x & 0x1) << 24) + +#define MUX_STAT_CHANGING 0x100 + +/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) (x & 0x7) +#define CORE_SEL(x) ((x & 0x7) << 16) +#define HPM_SEL(x) ((x & 0x7) << 20) +#define MPLL_USER_SEL_C(x) ((x & 0x7) << 24) +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \ + CORE_SEL(MUX_STAT_CHANGING) | \ + HPM_SEL(MUX_STAT_CHANGING) | \ + MPLL_USER_SEL_C(MUX_STAT_CHANGING)) + +/* CLK_DIV_CPU0 */ +#define CORE_RATIO(x) (x & 0x7) +#define COREM0_RATIO(x) ((x & 0x7) << 4) +#define COREM1_RATIO(x) ((x & 0x7) << 8) +#define PERIPH_RATIO(x) ((x & 0x7) << 12) +#define ATB_RATIO(x) ((x & 0x7) << 16) +#define PCLK_DBG_RATIO(x) ((x & 0x7) << 20) +#define APLL_RATIO(x) ((x & 0x7) << 24) +#define CORE2_RATIO(x) ((x & 0x7) << 28) + +/* CLK_DIV_STAT_CPU0 */ +#define DIV_CORE(x) (x & 0x1) +#define DIV_COREM0(x) ((x & 0x1) << 4) +#define DIV_COREM1(x) ((x & 0x1) << 8) +#define DIV_PERIPH(x) ((x & 0x1) << 12) +#define DIV_ATB(x) ((x & 0x1) << 16) +#define DIV_PCLK_DBG(x) ((x & 0x1) << 20) +#define DIV_APLL(x) ((x & 0x1) << 24) +#define DIV_CORE2(x) ((x & 0x1) << 28) + +#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \ + DIV_COREM0(DIV_STAT_CHANGING) | \ + DIV_COREM1(DIV_STAT_CHANGING) | \ + DIV_PERIPH(DIV_STAT_CHANGING) | \ + DIV_ATB(DIV_STAT_CHANGING) | \ + DIV_PCLK_DBG(DIV_STAT_CHANGING) | \ + DIV_APLL(DIV_STAT_CHANGING) | \ + DIV_CORE2(DIV_STAT_CHANGING)) + +/* CLK_DIV_CPU1 */ +#define COPY_RATIO(x) (x & 0x7) +#define HPM_RATIO(x) ((x & 0x7) << 4) +#define CORES_RATIO(x) ((x & 0x7) << 8) + +/* CLK_DIV_STAT_CPU1 */ +#define DIV_COPY(x) (x & 0x7) +#define DIV_HPM(x) ((x & 0x1) << 4) +#define DIV_CORES(x) ((x & 0x1) << 8) + +#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \ + DIV_HPM(DIV_STAT_CHANGING) | \ + DIV_CORES(DIV_STAT_CHANGING)) + +/* CLK_SRC_DMC */ +#define MUX_C2C_SEL(x) (x & 0x1) +#define MUX_DMC_BUS_SEL(x) ((x & 0x1) << 4) +#define MUX_DPHY_SEL(x) ((x & 0x1) << 8) +#define MUX_MPLL_SEL(x) ((x & 0x1) << 12) +#define MUX_PWI_SEL(x) ((x & 0xf) << 16) +#define MUX_G2D_ACP0_SEL(x) ((x & 0x1) << 20) +#define MUX_G2D_ACP1_SEL(x) ((x & 0x1) << 24) +#define MUX_G2D_ACP_SEL(x) ((x & 0x1) << 28) + +/* CLK_MUX_STAT_DMC */ +#define C2C_SEL(x) ((x) & 0x7) +#define DMC_BUS_SEL(x) ((x & 0x7) << 4) +#define DPHY_SEL(x) ((x & 0x7) << 8) +#define MPLL_SEL(x) ((x & 0x7) << 12) +/* #define PWI_SEL(x) ((x & 0xf) << 16) - Reserved */ +#define G2D_ACP0_SEL(x) ((x & 0x7) << 20) +#define G2D_ACP1_SEL(x) ((x & 0x7) << 24) +#define G2D_ACP_SEL(x) ((x & 0x7) << 28) + +#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \ + DMC_BUS_SEL(MUX_STAT_CHANGING) | \ + DPHY_SEL(MUX_STAT_CHANGING) | \ + MPLL_SEL(MUX_STAT_CHANGING) |\ + G2D_ACP0_SEL(MUX_STAT_CHANGING) | \ + G2D_ACP1_SEL(MUX_STAT_CHANGING) | \ + G2D_ACP_SEL(MUX_STAT_CHANGING)) + +/* CLK_DIV_DMC0 */ +#define ACP_RATIO(x) (x & 0x7) +#define ACP_PCLK_RATIO(x) ((x & 0x7) << 4) +#define DPHY_RATIO(x) ((x & 0x7) << 8) +#define DMC_RATIO(x) ((x & 0x7) << 12) +#define DMCD_RATIO(x) ((x & 0x7) << 16) +#define DMCP_RATIO(x) ((x & 0x7) << 20) + +/* CLK_DIV_STAT_DMC0 */ +#define DIV_ACP(x) (x & 0x1) +#define DIV_ACP_PCLK(x) ((x & 0x1) << 4) +#define DIV_DPHY(x) ((x & 0x1) << 8) +#define DIV_DMC(x) ((x & 0x1) << 12) +#define DIV_DMCD(x) ((x & 0x1) << 16) +#define DIV_DMCP(x) ((x & 0x1) << 20) + +#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \ + DIV_ACP_PCLK(DIV_STAT_CHANGING) | \ + DIV_DPHY(DIV_STAT_CHANGING) | \ + DIV_DMC(DIV_STAT_CHANGING) | \ + DIV_DMCD(DIV_STAT_CHANGING) | \ + DIV_DMCP(DIV_STAT_CHANGING)) + +/* CLK_DIV_DMC1 */ +#define G2D_ACP_RATIO(x) (x & 0xf) +#define C2C_RATIO(x) ((x & 0x7) << 4) +#define PWI_RATIO(x) ((x & 0xf) << 8) +#define C2C_ACLK_RATIO(x) ((x & 0x7) << 12) +#define DVSEM_RATIO(x) ((x & 0x7f) << 16) +#define DPM_RATIO(x) ((x & 0x7f) << 24) + +/* CLK_DIV_STAT_DMC1 */ +#define DIV_G2D_ACP(x) (x & 0x1) +#define DIV_C2C(x) ((x & 0x1) << 4) +#define DIV_PWI(x) ((x & 0x1) << 8) +#define DIV_C2C_ACLK(x) ((x & 0x1) << 12) +#define DIV_DVSEM(x) ((x & 0x1) << 16) +#define DIV_DPM(x) ((x & 0x1) << 24) + +#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \ + DIV_C2C(DIV_STAT_CHANGING) | \ + DIV_PWI(DIV_STAT_CHANGING) | \ + DIV_C2C_ACLK(DIV_STAT_CHANGING) | \ + DIV_DVSEM(DIV_STAT_CHANGING) | \ + DIV_DPM(DIV_STAT_CHANGING)) + +/* Set CLK_SRC_PERIL0 */ +#define UART4_SEL(x) ((x & 0xf) << 16) +#define UART3_SEL(x) ((x & 0xf) << 12) +#define UART2_SEL(x) ((x & 0xf) << 8) +#define UART1_SEL(x) ((x & 0xf) << 4) +#define UART0_SEL(x) ((x) & 0xf) + +/* Set CLK_DIV_PERIL0 */ +#define UART4_RATIO(x) ((x & 0xf) << 16) +#define UART3_RATIO(x) ((x & 0xf) << 12) +#define UART2_RATIO(x) ((x & 0xf) << 8) +#define UART1_RATIO(x) ((x & 0xf) << 4) +#define UART0_RATIO(x) ((x) & 0xf) + +/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART4(x) ((x & 0x1) << 16) +#define DIV_UART3(x) ((x & 0x1) << 12) +#define DIV_UART2(x) ((x & 0x1) << 8) +#define DIV_UART1(x) ((x & 0x1) << 4) +#define DIV_UART0(x) ((x) & 0x1) + +#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \ + DIV_UART3(DIV_STAT_CHANGING) | \ + DIV_UART2(DIV_STAT_CHANGING) | \ + DIV_UART1(DIV_STAT_CHANGING) | \ + DIV_UART0(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0xf) +#define MMC0_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC1_RATIO(x) ((x & 0xf) << 16) +#define MMC1_PRE_RATIO(x) ((x & 0xff) << 24) + +/* CLK_DIV_STAT_FSYS1 */ +#define DIV_MMC0(x) ((x) & 1) +#define DIV_MMC0_PRE(x) ((x & 1) << 8) +#define DIV_MMC1(x) ((x & 1) << 16) +#define DIV_MMC1_PRE(x) ((x & 1) << 24) + +#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \ + DIV_MMC0_PRE(DIV_STAT_CHANGING) | \ + DIV_MMC1(DIV_STAT_CHANGING) | \ + DIV_MMC1_PRE(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO(x) (x & 0xf) +#define MMC2_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC3_RATIO(x) ((x & 0xf) << 16) +#define MMC3_PRE_RATIO(x) ((x & 0xff) << 24) + +/* CLK_DIV_STAT_FSYS2 */ +#define DIV_MMC2(x) (x & 0x1) +#define DIV_MMC2_PRE(x) ((x & 0x1) << 8) +#define DIV_MMC3(x) ((x & 0x1) << 16) +#define DIV_MMC3_PRE(x) ((x & 0x1) << 24) + +#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \ + DIV_MMC2_PRE(DIV_STAT_CHANGING) | \ + DIV_MMC3(DIV_STAT_CHANGING) | \ + DIV_MMC3_PRE(DIV_STAT_CHANGING)) + +/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO(x) (x & 0x7) +#define MMC4_PRE_RATIO(x) ((x & 0xff) << 8) + +/* CLK_DIV_STAT_FSYS3 */ +#define DIV_MMC4(x) (x & 0x1) +#define DIV_MMC4_PRE(x) ((x & 0x1) << 8) + +#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \ + DIV_MMC4_PRE(DIV_STAT_CHANGING)) + +#endif /*__ODROIDU3_SETUP__ */

This config is valid for two devices: - Odroid X2, - Odroid U3.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com

--- Changes v2: - odroid config: add CONFIG_DFU_ALT_BOOTLOADER - odroid config: change name of CONFIG_DFU_BOOT_ALT_* to CONFIG_DFU_ALT_BOOT_*

Changes v3: - odroid.h: update CONFIG_DFU_ALT_BOOT_** with required bootloader binaries - odroid.h: add multi image support (CONFIG_FIT) - odroid.h: add "autoboot" script for multi boot options - odroid.h: change env name: dfu_alt_info -> dfu_alt_system - odroid.h: update config name: CONFIG_SET_DFU_ALT_INFO - odroid.h: reduce boot delay to 0 seconds - update: doc/README.odroid --- boards.cfg | 1 + doc/README.odroid | 144 +++++++++++++++++++++++++++++ include/configs/odroid.h | 232 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 377 insertions(+) create mode 100644 doc/README.odroid create mode 100644 include/configs/odroid.h

diff --git a/boards.cfg b/boards.cfg index 1527ebe..8e8bcb3 100644 --- a/boards.cfg +++ b/boards.cfg @@ -297,6 +297,7 @@ Active arm armv7 exynos samsung smdk5420 Active arm armv7 exynos samsung smdkv310 smdkv310 - Chander Kashyap k.chander@samsung.com Active arm armv7 exynos samsung trats trats - Lukasz Majewski l.majewski@samsung.com Active arm armv7 exynos samsung trats2 trats2 - Piotr Wilczek p.wilczek@samsung.com +Active arm armv7 exynos samsung odroid odroid - Przemyslaw Marczak p.marczak@samsung.com Active arm armv7 exynos samsung universal_c210 s5pc210_universal - Przemyslaw Marczak p.marczak@samsung.com Active arm armv7 highbank - highbank highbank - Rob Herring robh@kernel.org Active arm armv7 keystone ti k2hk_evm k2hk_evm - Vitaly Andrianov vitalya@ti.com diff --git a/doc/README.odroid b/doc/README.odroid new file mode 100644 index 0000000..15aba10 --- /dev/null +++ b/doc/README.odroid @@ -0,0 +1,144 @@ + U-boot for Odroid X2/U3 +======================== + +1. Summary +========== +This is a quick instruction for setup Odroid boards based on Exynos4412. +Board config: odroid_config + +2. Supported devices +==================== +This U-BOOT config can be used on two boards: +- Odroid U3 +- Odroid X2 +with CPU Exynos 4412 rev 2.0 and 2GB of RAM + +3. Boot sequence +================ +iROM->BL1->(BL2 + TrustZone)->U-BOOT + +This version of U-BOOT doesn't implement SPL but it is required(BL2) +and can be found in "boot.tar.gz" from here: +http://dev.odroid.com/projects/4412boot/wiki/FrontPage?action=download&v... + +4. Boot media layout +==================== +The table below shows SD/eMMC cards layout for U-boot. +The block offset is starting from 0 and the block size is 512B. + ------------------------------------- +| Binary | Block offset| part type | +| name | SD | eMMC |(eMMC only)| + ------------------------------------- +| Bl1 | 1 | 0 | 1 (boot) | +| Bl2 | 31 | 30 | 1 (boot) | +| U-boot | 63 | 62 | 1 (boot) | +| Tzsw | 2111 | 2110 | 1 (boot) | +| Uboot Env | 2500 | 2500 | 0 (user) | + ------------------------------------- + +5. Prepare the SD boot card - with SD card reader +================================================= +To prepare bootable media you need boot binaries provided by hardkernel. +File "boot.tar.gz" (link in point 3.) contains: +- E4412_S.bl1.HardKernel.bin +- E4412_S.tzsw.signed.bin +- bl2.signed.bin +- sd_fusing.sh +- u-boot.bin + +This is all you need to boot this board. But if you want to use your custom +u-boot then you need to change u-boot.bin with your own u-boot binary* +and run the script "sd_fusing.sh" - this script is valid only for SD card. + +*note: +The proper binary file of current U-boot is u-boot-dtb.bin. + +quick steps for Linux: +- extract boot.tar.gz +- put any SD card into the SD reader +- check the device with "dmesg" +- run ./sd_fusing.sh /dev/sdX - where X is SD card device (but not a partition) +Check if Hardkernel U-boot is booting, and next do the same with your U-boot. + +6. Prepare the eMMC boot card + with a eMMC card reader (boot from eMMC card slot) +===================================================== +To boot the device from the eMMC slot you should use a special card reader +which supports eMMC partiion switch. All of the boot binaries are stored +on the eMMC boot partition which is normally hidden. + +The "sd_fusing.sh" script can be used after updating offsets of binaries +according to the table from point 4. Be sure that you are working on the right +eMMC partition - its size is usually very small, about 1-4 MiB. + +7. Prepare the eMMC boot card + with a SD card reader (boot from SD card slot) +================================================= +If you have an eMMC->microSD adapter you can prepare the card as in point 5. +But then the device can boot only from the SD card slot. + +8. Prepare the boot media using Hardkernel U-boot +================================================= +You can update the U-boot to the custom one if you have an working bootloader +delivered with the board on a eMMC/SD card. Then follow the steps: +- install the android fastboot tool +- connect a micro usb cable to the board +- on the U-boot prompt, run command: fastboot (as a root) +- on the host, run command: "fastboot flash bootloader u-boot-dtb.bin" +- the custom U-boot should start after the board resets. + +9. Partition layout +==================== +Default U-boot environment is setup for fixed partiion layout. + +Partition table: MSDOS. Disk layout and files as listed in the table below. + ----- ------ ------ ------ -------- --------------------------------- +| Num | Name | FS | Size | Offset | Reguired files | +| | | Type | MiB | MiB | | + ----- ------ ------ ------ -------- --------------------------------- +| 1 | BOOT | fat | 100 | 2 | uImage, exynos4412-odroid**.dtb | +| 2 | ROOT | ext4 | 3072 | | any Linux system | +| 3 | DATA | any | 3072 | | | +| 4 | UMS | any | any | | | + ----- ------ ------ ------ -------- --------------------------------- + +**note: +Supported fdt files are: +- exynos4412-odroidx2.dtb +- exynos4412-odroidu3.dtb + +Supported kernel files are: +- Image.itb +- zImage +- uImage + +The default environmental variable "dfu_alt_info" is set* for above layout. +Each partition size is just an example, dfu_alt_info tries init four partitions. +The size of each is not important. + +*note: +$dfu_alt_info is set on a boot time and it is concatenated using two variables: +- $dfu_alt_boot(set dynamically) +- $dfu_alt_system(from current env). + +To add any changes to dfu_alt_info - please modify $dfu_alt_system only. +Changes are visible after board reset. + +10. The environment and booting the kernel +========================================== +There are three macros defined in config for various boot options: +Two for both, kernel with device tree support and also without it: +- boot_uimg - load uImage +- boot_zimg - load zImage +The device tree support can be enabled by setting the env variable: +- "setenv kernel_usefdt 1" (enabled by default) +- "setenv kernel_usefdt 0" (for old kernel types) + +The third boot option for multi image support (more info: doc/uImage.FIT/) +- boot_fit - for binary file: "Image.itb" + +Default boot command: "autoboot" +And the boot sequence is: +- boot_fit - if "Image.itb" exists +- boot_zimg - if "zImage" exists +- boot_uimg - if "uImage" exists diff --git a/include/configs/odroid.h b/include/configs/odroid.h new file mode 100644 index 0000000..4a4f171 --- /dev/null +++ b/include/configs/odroid.h @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Sanghee Kim sh0130.kim@samsung.com + * Piotr Wilczek p.wilczek@samsung.com + * Przemyslaw Marczak p.marczak@samsung.com + * + * Configuation settings for the Odroid-U3 (EXYNOS4412) board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_ODROID_U3_H +#define __CONFIG_ODROID_U3_H + +#include <configs/exynos4-dt.h> + +#define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */ + +#undef CONFIG_DEFAULT_DEVICE_TREE +#define CONFIG_DEFAULT_DEVICE_TREE exynos4412-odroid + +#define CONFIG_SYS_L2CACHE_OFF +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 +#define CONFIG_SYS_PL310_BASE 0x10502000 +#endif + +#define CONFIG_MACH_TYPE 4289 + +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE + +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) +#define CONFIG_SYS_TEXT_BASE 0x43e00000 + +#include <linux/sizes.h> +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) + +/* select serial console configuration */ +#define CONFIG_SERIAL1 +#define CONFIG_BAUDRATE 115200 + +/* Console configuration */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_CMD_BOOTZ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE +#define CONFIG_BOOTARGS "Please use defined boot" +#define CONFIG_BOOTCOMMAND "run autoboot" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ + - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_MEM_TOP_HIDE (SZ_1M) /* ram console */ + +#define CONFIG_SYS_MONITOR_BASE 0x00000000 + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_ENV_OFFSET (SZ_1K * 1280) /* 1.25 MiB offset */ +#define CONFIG_ENV_OVERWRITE + +/* Partitions name */ +#define PARTS_BOOT "boot" +#define PARTS_ROOT "platform" +#define PARTS_DATA "data" +#define PARTS_UMS "ums" + +#define CONFIG_DFU_ALT \ + "uImage fat 0 1;" \ + "zImage fat 0 1;" \ + "Image.itb fat 0 1;" \ + "exynos4412-odroidu3.dtb fat 0 1;" \ + "exynos4412-odroidx2.dtb fat 0 1;" \ + ""PARTS_BOOT" part 0 1;" \ + ""PARTS_ROOT" part 0 2;" \ + ""PARTS_DATA" part 0 3;" \ + ""PARTS_UMS" part 0 4\0" + +#define CONFIG_SET_DFU_ALT_INFO + +#define CONFIG_DFU_ALT_BOOT_EMMC \ + "u-boot raw 0x3e 0x800 mmcpart 1;" \ + "bl1 raw 0x0 0x1e mmcpart 1;" \ + "bl2 raw 0x1e 0x1d mmcpart 1;" \ + "tzsw raw 0x83e 0x138 mmcpart 1\0" + +#define CONFIG_DFU_ALT_BOOT_SD \ + "u-boot raw 0x3f 0x800;" \ + "bl1 raw 0x1 0x1e;" \ + "bl2 raw 0x1f 0x1d;" \ + "tzsw raw 0x83f 0x138\0" + +/* + * Bootable media layout: + * dev: SD eMMC(part boot) + * BL1 1 0 + * BL2 31 30 + * UBOOT 63 62 + * TZSW 2111 2110 + * ENV 2560 2560(part user) + * + * MBR Primary partiions: + * Num Name Size Offset + * 1. BOOT: 100MiB 2MiB + * 2. ROOT: 3GiB + * 3. DATA: 3GiB + * 4. UMS: - +*/ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadkernel=fatload mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ + "${kernelname}\0" \ + "loaddtb=fatload mmc ${mmcbootdev}:${mmcbootpart} ${fdtaddr} "\ + "${fdtfile}\0" \ + "kernel_args=" \ + "setenv bootargs root=/dev/mmcblk${mmcrootdev}p${mmcrootpart} "\ + "${rootopts} ${lpj} ${console} ${meminfo} ${opts} ${lcdinfo}\0"\ + "boot_fit=" \ + "setenv kerneladdr 0x42000000;" \ + "setenv kernelname Image.itb;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "bootm ${kerneladdr}#${boardname}\0" \ + "boot_uimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname uImage;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "if test $kernel_usefdt = 1; then " \ + "if run loaddtb; then " \ + "bootm ${kerneladdr} - ${fdtaddr};" \ + "fi;" \ + "fi;" \ + "bootm ${kerneladdr};\0" \ + "boot_zimg=" \ + "setenv kerneladdr 0x40007FC0;" \ + "setenv kernelname zImage;" \ + "run loadkernel;" \ + "run kernel_args;" \ + "if test $kernel_usefdt = 1; then " \ + "if run loaddtb; then " \ + "bootz ${kerneladdr} - ${fdtaddr};" \ + "fi;" \ + "fi;" \ + "bootz ${kerneladdr};\0" \ + "autoboot=" \ + "if test -e mmc 0 Image.itb; then; " \ + "run boot_fit;" \ + "elif test -e mmc 0 zImage; then; " \ + "run boot_zimg;" \ + "elif test -e mmc 0 uImage; then; " \ + "run boot_uimg;" \ + "fi;\0" \ + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ + "console=" CONFIG_DEFAULT_CONSOLE \ + "kernelname=uImage\0" \ + "kernel_usefdt=1\0" \ + "mmcbootdev=0\0" \ + "mmcbootpart=1\0" \ + "mmcrootdev=0\0" \ + "mmcrootpart=2\0" \ + "bootdelay=0\0" \ + "boardname=\0" \ + "rootopts=rootwait\0" \ + "opts=always_resume=1\0" \ + "dfu_alt_system="CONFIG_DFU_ALT \ + "dfu_alt_info=Please reset the board\0" \ + "consoleon=set console console=ttySAC1,115200n8; save; reset\0" \ + "consoleoff=set console console=ram; save; reset\0" \ + "fdtaddr=40800000\0" + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_S3C24X0 +#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 +#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 +#define CONFIG_MAX_I2C_NUM 8 +#define CONFIG_SYS_I2C_INIT_BOARD + +/* POWER */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_MAX77686 + +/* GPT */ +#define CONFIG_RANDOM_UUID + +/* Security subsystem - enable hw_rand() */ +#define CONFIG_EXYNOS_ACE_SHA +#define CONFIG_LIB_HW_RAND + +#define CONFIG_CMD_GPIO + +/* + * Supported Odroid boards: X3, U3 + * TODO: Add Odroid X support + */ +#define CONFIG_MISC_COMMON +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG +#define CONFIG_BOARD_TYPES +#define CONFIG_MISC_INIT_R + +#undef CONFIG_REVISION_TAG + +#endif /* __CONFIG_H */

The byte order of soc revision was inverted, now it is fixed.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com --- board/samsung/common/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 03106fd..a453a82 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -26,8 +26,8 @@ void set_board_info(void) { char info[64];

- snprintf(info, ARRAY_SIZE(info), "%d.%d", s5p_cpu_rev & 0x0f, - (s5p_cpu_rev & 0xf0) >> 0x04); + snprintf(info, ARRAY_SIZE(info), "%u.%u", (s5p_cpu_rev & 0xf0) >> 4, + s5p_cpu_rev & 0xf); setenv("soc_rev", info);

snprintf(info, ARRAY_SIZE(info), "%x", s5p_cpu_id);

It's reasonable, looks good to me.

Acked-by: Jaehoon Chung jh80.chung@samsung.com

On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:

This change fixes the bad gpio configuration for the exynos dwmmc.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Beomho Seo beomho.seo@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jaehoon Chung jh80.chung@samsung.com

---

arch/arm/cpu/armv7/exynos/pinmux.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 86a0c75..b929486 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -704,8 +704,8 @@ static int exynos4x12_mmc_config(int peripheral, int flags) ext_func = S5P_GPIO_FUNC(0x3); break; case PERIPH_ID_SDMMC4:

• start = EXYNOS4_GPIO_K00;
  

• start_ext = EXYNOS4_GPIO_K13;
  

• start = EXYNOS4X12_GPIO_K00;
  

• start_ext = EXYNOS4X12_GPIO_K13;
  

  func = S5P_GPIO_FUNC(0x3); ext_func = S5P_GPIO_FUNC(0x4); break;

It is possible to boot device using a micro SD or eMMC slots. In this situation, boot device should be registered as a block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com --- Changes V3: - separate two changes into two commits

Changes V4: - board.c: add functions: init_mmc() and init_dwmmc() - board_mmc_init(): call get_boot_mode() --- board/samsung/common/board.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..4d3f216 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis) }

#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) +static int init_mmc(void) +{ +#ifdef CONFIG_SDHCI + return exynos_mmc_init(gd->fdt_blob); +#else + return 0; +#endif +} + +static int init_dwmmc(void) { - int ret; #ifdef CONFIG_DWMMC - /* dwmmc initializattion for available channels */ - ret = exynos_dwmmc_init(gd->fdt_blob); - if (ret) - debug("dwmmc init failed\n"); + return exynos_dwmmc_init(gd->fdt_blob); +#else + return 0; #endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + if (get_boot_mode() == BOOT_MODE_MMC) { + ret = init_mmc(); + ret |= init_dwmmc(); + } else { + ret = init_dwmmc(); + ret |= init_mmc(); + }

-#ifdef CONFIG_SDHCI - /* mmc initializattion for available channels */ - ret = exynos_mmc_init(gd->fdt_blob); if (ret) debug("mmc init failed\n"); -#endif + return ret; } #endif

Hello Jaehoon,

On 07/04/2014 07:45 AM, Jaehoon Chung wrote:

Hi, Przemyslaw.

On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:

...

It is possible to boot device using a micro SD or eMMC slots. In this situation, boot device should be registered as a block device 0 in the MMC framework, because CONFIG_SYS_MMC_ENV_DEV is usually set to "0" in the most config cases.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com

Changes V3:

• separate two changes into two commits

Changes V4:

• board.c: add functions: init_mmc() and init_dwmmc()
• board_mmc_init(): call get_boot_mode()

---

board/samsung/common/board.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 9dc7c83..4d3f216 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -240,22 +240,39 @@ int board_eth_init(bd_t *bis) }

#ifdef CONFIG_GENERIC_MMC -int board_mmc_init(bd_t *bis) +static int init_mmc(void) +{ +#ifdef CONFIG_SDHCI

• return exynos_mmc_init(gd->fdt_blob);

+#else

• return 0;

+#endif +}

+static int init_dwmmc(void) {

• int ret; #ifdef CONFIG_DWMMC
• /* dwmmc initializattion for available channels */
• ret = exynos_dwmmc_init(gd->fdt_blob);
• if (ret)

• debug("dwmmc init failed\n");
  

• return exynos_dwmmc_init(gd->fdt_blob);

+#else

• return 0; #endif

+}

+int board_mmc_init(bd_t *bis) +{

• int ret;
• if (get_boot_mode() == BOOT_MODE_MMC) {

• ret = init_mmc();
  

• ret |= init_dwmmc();
  

• } else {

• ret = init_dwmmc();
  

• ret |= init_mmc();
  

• }

Well, i have some confusion for this. Did you consider the case like init_dwmmc() is succeed and init_mmc() is failed? it's hard to control the error for both.

Best Regards, Jaehoon Chung

In our vendor init code, the value returned by this function has no significant meaning since there is no implementation of function "cpu_mmc_init()".

So checking this error is just for a debug purposes: # if (ret) # debug("mmc init failed\n");

and the returned value: mmc | dwmmc -> ret 0 | 1 -> 1 1 | 0 -> 1 1 | 1 -> 1 0 | 0 -> 0

So we have an error message on any error.

...

-#ifdef CONFIG_SDHCI

• /* mmc initializattion for available channels */
• ret = exynos_mmc_init(gd->fdt_blob); if (ret) debug("mmc init failed\n");

-#endif

• return ret; } #endif

Thank you,

This change introduces new common function: - set_dfu_alt_info() - put dfu system and bootloader setting into $dfu_alt_info. functions declaration: - char *get_dfu_alt_system(void) - char *get_dfu_alt_boot(void) - void set_dfu_alt_info(void) and new config: - CONFIG_SET_DFU_ALT_INFO

This function can be used for auto setting dfu configuration on boot. Such feature is useful for multi board support by one u-boot binary. Each board should define two functions: - get_dfu_alt_system() - get_dfu_alt_boot()

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

--- Changes v2: - change config names: CONFIG_SET_DFU_BOOT_ALT to CONFIG_DFU_ALT_BOOTLOADER and CONFIG_DFU_BOOT_ALT_* to CONFIG_DFU_ALT_BOOT_* - change function name: set_dfu_boot_alt() to set_dfu_alt_boot() - remove superfluous ifdefs

Changes v3: - set $dfu_alt_info at every boot - new config: CONFIG_SET_DFU_ALT_INFO - update commit msg

Changes v4: - set_dfu_alt_info(): add checking the pointer returned by malloc --- board/samsung/common/misc.c | 38 ++++++++++++++++++++++++++++++++++++++ include/samsung/misc.h | 6 ++++++ 2 files changed, 44 insertions(+)

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index a453a82..5a3eb93 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -11,6 +11,7 @@ #include <samsung/misc.h> #include <errno.h> #include <version.h> +#include <malloc.h> #include <linux/sizes.h> #include <asm/arch/cpu.h> #include <asm/arch/gpio.h> @@ -21,6 +22,43 @@

DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_SET_DFU_ALT_INFO +void set_dfu_alt_info(void) +{ + char *alt_boot = NULL; + char *alt_system = NULL; + char *buf = NULL; + int buf_len; + + puts("DFU alt info setting: "); + + alt_boot = get_dfu_alt_boot(); + if (!alt_boot) + goto error; + + alt_system = get_dfu_alt_system(); + if (!alt_system) + goto error; + + buf_len = strlen(alt_boot) + strlen(alt_system) + 2; + buf = malloc(buf_len); + if (!buf) + goto error; + + sprintf(buf, "%s;%s", alt_boot, alt_system); + setenv("dfu_alt_info", buf); + + free(buf); + + puts("done\n"); + + return; +error: + puts("error\n"); + setenv("dfu_alt_info", "Settings not found!"); +} +#endif + #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG void set_board_info(void) { diff --git a/include/samsung/misc.h b/include/samsung/misc.h index 10653a1..e82bf32 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -28,4 +28,10 @@ void check_boot_mode(void); void draw_logo(void); #endif

+#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void); +char *get_dfu_alt_boot(void); +void set_dfu_alt_info(void); +#endif + #endif /* __SAMSUNG_MISC_COMMON_H__ */

On an Odroid U3 board, the SOC is unable to reset the eMMC card in the DWMMC mode by the cpu software reset. Manual reset of the card by switching proper gpio pin - fixes this issue.

Such solution needs to add a call to pre reset function. This is done by the reset_misc() function, which is called before reset_cpu(). The function reset_misc() is a weak function.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Jean-Christophe PLAGNIOL-VILLARD plagnioj@jcrosoft.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net Cc: Tom Rini trini@ti.com

Changes v4: - arch/arm/reset: fix weak function attribute to proper style --- arch/arm/lib/reset.c | 6 ++++++ include/common.h | 1 + 2 files changed, 7 insertions(+)

diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a03580..9a95f08 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -23,6 +23,10 @@

#include <common.h>

+__weak void reset_misc(void) +{ +} + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { puts ("resetting ...\n"); @@ -30,6 +34,8 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) udelay (50000); /* wait 50 ms */

disable_interrupts(); + + reset_misc(); reset_cpu(0);

/*NOTREACHED*/ diff --git a/include/common.h b/include/common.h index 232136c..04bab78 100644 --- a/include/common.h +++ b/include/common.h @@ -629,6 +629,7 @@ int checkicache (void); int checkdcache (void); void upmconfig (unsigned int, unsigned int *, unsigned int); ulong get_tbclk (void); +void reset_misc (void); void reset_cpu (ulong addr); #if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP) void ft_cpu_setup(void *blob, bd_t *bd);

On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:

This change adds declaration of functions:

• set_board_type() - called at checkboard()
• get_board_type() - called at checkboard()
• get_board_name()

For supporting multiple board types in a one config - it is welcome to display the current board model. This is what get_board_type() should return.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

---

Changes v3:

• change the commit order
• include/samsung/misc.h: add new functions declaration
• update a commit message

Changes v4:

• checkboard(): remove redundant variable

---

board/samsung/common/board.c | 12 +++++++++--- include/samsung/misc.h | 5 +++++ 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index a46e87b..3e27130 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -280,11 +280,17 @@ int board_mmc_init(bd_t *bis) #ifdef CONFIG_DISPLAY_BOARDINFO int checkboard(void) {

• const char *board_name;

• const char *board_info;

Is there a reason that it's renaming?

Best Regards, Jaehoon Chung

• board_name = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
• printf("Board: %s\n", board_name ? board_name : "unknown");

• board_info = fdt_getprop(gd->fdt_blob, 0, "model", NULL);
• printf("Board: %s\n", board_info ? board_info : "unknown");

+#ifdef CONFIG_BOARD_TYPES

• set_board_type();

• board_info = get_board_type();

• printf("Model: %s\n", board_info ? board_info : "unknown");

+#endif return 0; } #endif diff --git a/include/samsung/misc.h b/include/samsung/misc.h index e82bf32..cc41997 100644 --- a/include/samsung/misc.h +++ b/include/samsung/misc.h @@ -33,5 +33,10 @@ char *get_dfu_alt_system(void); char *get_dfu_alt_boot(void); void set_dfu_alt_info(void); #endif +#ifdef CONFIG_BOARD_TYPES +void set_board_type(void); +const char *get_board_type(void); +const char *get_board_name(void); +#endif

#endif /* __SAMSUNG_MISC_COMMON_H__ */

This change adds setup of environmental board info using get_board_name() and get_board_type() functions for config CONFIG_BOARD_TYPES.

This is useful in case of running many boards with just one config.

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Piotr Wilczek p.wilczek@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com

--- Changes v2: - set_board_info: move the bdtype pointer to avoid unused pointer compilation warning

Changes v3: - samsung: misc: change get_board_type_fdt() to get_board_type() - samsung: misc: set env $boardname using get_board_* functions for CONFIG_BOARD_TYPES - update commit msg --- board/samsung/common/misc.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/board/samsung/common/misc.c b/board/samsung/common/misc.c index 5a3eb93..ec864bf 100644 --- a/board/samsung/common/misc.c +++ b/board/samsung/common/misc.c @@ -76,8 +76,17 @@ void set_board_info(void) setenv("board_rev", info); #endif #ifdef CONFIG_OF_LIBFDT - snprintf(info, ARRAY_SIZE(info), "%s%x-%s.dtb", - CONFIG_SYS_SOC, s5p_cpu_id, CONFIG_SYS_BOARD); + const char *bdtype = ""; + const char *bdname = CONFIG_SYS_BOARD; + +#ifdef CONFIG_BOARD_TYPES + bdtype = get_board_type(); + bdname = get_board_name(); + sprintf(info, "%s%s", bdname, bdtype); + setenv("boardname", info); +#endif + snprintf(info, ARRAY_SIZE(info), "%s%x-%s%s.dtb", + CONFIG_SYS_SOC, s5p_cpu_id, bdname, bdtype); setenv("fdtfile", info); #endif }

On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:

This board file supports standard features of Odroid X2 and U3 boards:

• Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
• MAX77686 power regulator,
• USB PHY,
• enable XCL205 - power for board peripherials
• check board type: U3 or X2.
• enable Odroid U3 FAN cooler

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com

---

Changes v2:

• enable fan on odroid U3

Changes v3:

• odroid.c: clean up board name related code
• odroid.c: remove static from set_board_type()
• odroid.c: add implementation of functions: get_dfu_alt_*
• odroid.c: include misc.h

Changes v4: odroid.c: dfu_get_alt_boot: add call get_boot_mode()

---

board/samsung/odroid/Makefile | 8 + board/samsung/odroid/odroid.c | 466 ++++++++++++++++++++++++++++++++++++++++++ board/samsung/odroid/setup.h | 227 ++++++++++++++++++++ 3 files changed, 701 insertions(+) create mode 100644 board/samsung/odroid/Makefile create mode 100644 board/samsung/odroid/odroid.c create mode 100644 board/samsung/odroid/setup.h

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile new file mode 100644 index 0000000..b98aaeb --- /dev/null +++ b/board/samsung/odroid/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# Przemyslaw Marczak p.marczak@samsung.com +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := odroid.o diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c new file mode 100644 index 0000000..28706af --- /dev/null +++ b/board/samsung/odroid/odroid.c @@ -0,0 +1,466 @@ +/*

• • Copyright (C) 2014 Samsung Electronics
• • Przemyslaw Marczak p.marczak@samsung.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/cpu.h> +#include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <errno.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <samsung/misc.h> +#include "setup.h"

+DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_BOARD_TYPES +/* Odroid board types */ +enum {

• ODROID_TYPE_U3,
• ODROID_TYPE_X2,

+};

+void set_board_type(void) +{

• int val;
• /* Check GPC1 pin 2 */
• gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
• gpio_direction_input(EXYNOS4X12_GPIO_C12);
• /* XCL205 - needs some latch time */
• mdelay(10);
• /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
• val = gpio_get_value(EXYNOS4X12_GPIO_C12);
• if (val)

val is unnecessary. "int val" can be removed. if (gpio_get_value(EXYNS4x12_GPIO_C12)) ....

• gd->board_type = ODROID_TYPE_X2;
  

• else

• gd->board_type = ODROID_TYPE_U3;
  

+}

+const char *get_board_name(void) +{

• const char *board_name = "odroid";

Is there other approach or general method for getting board name?

• return board_name;

+}

+const char *get_board_type(void) +{

• const char *board_type[] = {"u3", "x2"};
• return board_type[gd->board_type];

+} +#endif

+#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void) +{

• return getenv("dfu_alt_system");

+}

+char *get_dfu_alt_boot(void) +{

• char *alt_boot = NULL;
• switch (get_boot_mode()) {
• case BOOT_MODE_MMC:

• alt_boot = CONFIG_DFU_ALT_BOOT_SD;
  

• break;
  

• default:

• alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
  

• break;
  

• }
• if (!alt_boot)

• return NULL;
  

Is it need? alt_boot is set to CONFIG_DFU_ALT_BOOT_EMMC by default, isn't? CONFIG_DFU_ALT_BOOT_EMMC is 0?

• setenv("dfu_alt_boot", alt_boot);
• return alt_boot;

+} +#endif

+static void board_clock_init(void) +{

• unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
• struct exynos4x12_clock *clk = (struct exynos4x12_clock *)

• 				samsung_get_base_clock();
  

• /*

• * CMU_CPU clocks src to MPLL
  

• * Bit values:                 0  ; 1
  

• * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
  

• * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
  

• * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
  

• * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
  

• */
• clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |

•       MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
  

• set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |

•      MUX_MPLL_USER_SEL_C(1);
  

0x1 or 1? you can use it consistency. MUX_APLL_SEL(1) or MUX_APLL_SEL(0x1).

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

• continue;
  

• /* Set APLL to 1000MHz */
• clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1);
• set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
• clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))

• continue;
  

• /* Set CMU_CPU clocks src to APLL */
• set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |

•      MUX_MPLL_USER_SEL_C(1);
  

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

• continue;
  

• set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |

•      PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  

•      APLL_RATIO(0) | CORE2_RATIO(0);
  

• /*

• * Set dividers for MOUTcore = 1000 MHz
  

• * coreout =      MOUT / (ratio + 1) = 1000 MHz (0)
  

• * corem0 =     armclk / (ratio + 1) = 333 MHz (2)
  

• * corem1 =     armclk / (ratio + 1) = 166 MHz (5)
  

• * periph =     armclk / (ratio + 1) = 1000 MHz (0)
  

• * atbout =       MOUT / (ratio + 1) = 200 MHz (4)
  

• * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  

• * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  

• * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  

• */
• clr = CORE_RATIO(0x7) | COREM0_RATIO(0x7) | COREM1_RATIO(0x7) |

•      PERIPH_RATIO(0x7) | ATB_RATIO(0x7) | PCLK_DBG_RATIO(0x7) |
  

•      APLL_RATIO(0x7) | CORE2_RATIO(0x7);
  

• clrsetbits_le32(&clk->div_cpu0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)

• continue;
  

• /*

• * For MOUThpm = 1000 MHz (MOUTapll)
  

• * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  

• * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  

• * cores_out = armclk / (ratio + 1) = 1000 (0)
  

• */
  

• clr = COPY_RATIO(0x7) | HPM_RATIO(0x7) | CORES_RATIO(0x7);
• set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
• clrsetbits_le32(&clk->div_cpu1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)

• continue;
  

• /*

• * Set CMU_DMC clocks src to APLL
  

• * Bit values:             0  ; 1
  

• * MUX_C2C_SEL:      SCLKMPLL ; SCLKAPLL
  

• * MUX_DMC_BUS_SEL:  SCLKMPLL ; SCLKAPLL
  

• * MUX_DPHY_SEL:     SCLKMPLL ; SCLKAPLL
  

• * MUX_MPLL_SEL:     FINPLL   ; MOUT_MPLL_FOUT
  

• * MUX_PWI_SEL:      0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  

• * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  

• * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  

• * MUX_G2D_ACP_SEL:  OUT_ACP0 ; OUT_ACP1
  

• */
• clr_src_dmc = MUX_C2C_SEL(0x1) | MUX_DMC_BUS_SEL(0x1) |

•       MUX_DPHY_SEL(0x1) | MUX_MPLL_SEL(0x1) |
  

•       MUX_PWI_SEL(0xf) | MUX_G2D_ACP0_SEL(0x1) |
  

•       MUX_G2D_ACP1_SEL(0x1) | MUX_G2D_ACP_SEL(0x1);
  

• set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |

•      MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  

•      MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

• continue;
  

• /* Set MPLL to 800MHz */
• set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
• clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))

• continue;
  

• /* Switch back CMU_DMC mux */
• set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |

•      MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  

•      MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

• continue;
  

• /* CLK_DIV_DMC0 */
• clr = ACP_RATIO(0x7) | ACP_PCLK_RATIO(0x7) | DPHY_RATIO(0x7) |

•      DMC_RATIO(0x7) | DMCD_RATIO(0x7) | DMCP_RATIO(0x7);
  

• /*

• * For:
  

• * MOUTdmc = 800 MHz
  

• * MOUTdphy = 800 MHz
  

• *
  

• * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  

• * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  

• * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  

• * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  

• * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  

• * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
  

• */
  

• set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |

•      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)

• continue;
  

• /* CLK_DIV_DMC1 */
• clr = G2D_ACP_RATIO(0xf) | C2C_RATIO(0x7) | PWI_RATIO(0xf) |

•      C2C_ACLK_RATIO(0x7) | DVSEM_RATIO(0x7f) | DPM_RATIO(0x7f);
  

• /*

• * For:
  

• * MOUTg2d = 800 MHz
  

• * MOUTc2c = 800 Mhz
  

• * MOUTpwi = 108 MHz
  

• *
  

• * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
  

• * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  

• * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
  

• * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  

• */
  

• set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |

•      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)

• continue;
  

• /* CLK_SRC_PERIL0 */
• clr = UART0_SEL(0xf) | UART1_SEL(0xf) | UART2_SEL(0xf) |

•      UART3_SEL(0xf) | UART4_SEL(0xf);
  

• /*

• * Set CLK_SRC_PERIL0 clocks src to MPLL
  

• * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  

• *             5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  

• *             8(SCLK_VPLL)
  

• *
  

• * Set all to SCLK_MPLL_USER_T
  

• */
  

• set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |

•      UART4_SEL(6);
  

• clrsetbits_le32(&clk->src_peril0, clr, set);
• /* CLK_DIV_PERIL0 */
• clr = UART0_RATIO(0xf) | UART1_RATIO(0xf) | UART2_RATIO(0xf) |

•      UART3_RATIO(0xf) | UART4_RATIO(0xf);
  

• /*

• * For MOUTuart0-4: 800MHz
  

• *
  

• * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
  

• */
• set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |

•      UART3_RATIO(7) | UART4_RATIO(7);
  

• clrsetbits_le32(&clk->div_peril0, clr, set);
• while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS1 */
• clr = MMC0_RATIO(0xf) | MMC0_PRE_RATIO(0xff) | MMC1_RATIO(0xf) |

•      MMC1_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  

• * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  

• * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  

• * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
  

• */
• set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |

•      MMC1_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS2 */
• clr = MMC2_RATIO(0xf) | MMC2_PRE_RATIO(0xff) | MMC3_RATIO(0xf) |

•      MMC3_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  

• * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  

• * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  

• * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
  

• */
• set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |

•      MMC3_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys2, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)

• continue;
  

• /* CLK_DIV_FSYS3 */
• clr = MMC4_RATIO(0xf) | MMC4_PRE_RATIO(0xff);
• /*

• * For MOUTmmc4 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  

• * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
  

• */
• set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
• clrsetbits_le32(&clk->div_fsys3, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)

• continue;
  

• return;

+}

+static void board_gpio_init(void) +{

• /* Set GPA1 pin 1 to HI - enable XCL205 output */
• gpio_set_pull(EXYNOS4X12_GPIO_A11, S5P_GPIO_PULL_UP);
• gpio_set_drv(EXYNOS4X12_GPIO_A11, S5P_GPIO_DRV_4X);
• gpio_direction_output(EXYNOS4X12_GPIO_A11, 1);
• gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
• gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
• /* Enable FAN (Odroid U3) */
• gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
• gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
• gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);

+}

+static int pmic_init_max77686(void) +{

• struct pmic *p = pmic_get("MAX77686_PMIC");
• if (pmic_probe(p))

• return -ENODEV;
  

• /* Set LDO Voltage */
• max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
• max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
• max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */

LDO20/22 are used the eMMC? VDD/VDD-IO power?

• return 0;

+}

+#ifdef CONFIG_SYS_I2C_INIT_BOARD +static void board_init_i2c(void) +{

• /* I2C_0 */
• if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE))

• debug("I2C%d not configured\n", (I2C_0));
  

+} +#endif

+int exynos_early_init_f(void) +{

• board_clock_init();
• board_gpio_init();
• return 0;

+}

+int exynos_init(void) +{

• return 0;

+}

+int exynos_power_init(void) +{ +#ifdef CONFIG_SYS_I2C_INIT_BOARD

• board_init_i2c();

+#endif

• pmic_init(I2C_0);
• pmic_init_max77686();
• return 0;

+}

+#ifdef CONFIG_USB_GADGET +static int s5pc210_phy_control(int on) +{

• struct pmic *p_pmic;
• p_pmic = pmic_get("MAX77686_PMIC");
• if (!p_pmic)

• return -ENODEV;
  

• if (pmic_probe(p_pmic))

• return -1;
  

• if (on)

• return max77686_set_ldo_mode(p_pmic, 12, OPMODE_ON);
  

• else

• return max77686_set_ldo_mode(p_pmic, 12, OPMODE_LPM);
  

+}

+struct s3c_plat_otg_data s5pc210_otg_data = {

• .phy_control = s5pc210_phy_control,
• .regs_phy = EXYNOS4X12_USBPHY_BASE,
• .regs_otg = EXYNOS4X12_USBOTG_BASE,
• .usb_phy_ctrl = EXYNOS4X12_USBPHY_CONTROL,
• .usb_flags = PHY0_SLEEP,

+};

+int board_usb_init(int index, enum usb_init_type init) +{

• debug("USB_udc_probe\n");
• return s3c_udc_probe(&s5pc210_otg_data);

+} +#endif

+void reset_misc(void) +{

• /* Reset eMMC*/
• gpio_set_value(EXYNOS4X12_GPIO_K12, 0);
• mdelay(10);
• gpio_set_value(EXYNOS4X12_GPIO_K12, 1);

+} diff --git a/board/samsung/odroid/setup.h b/board/samsung/odroid/setup.h new file mode 100644 index 0000000..982d676 --- /dev/null +++ b/board/samsung/odroid/setup.h @@ -0,0 +1,227 @@ +/*

• • Copyright (C) 2014 Samsung Electronics
• • Przemyslaw Marczak p.marczak@samsung.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#ifndef __ODROIDU3_SETUP__ +#define __ODROIDU3_SETUP__

+/* A/M PLL_CON0 */ +#define SDIV(x) (x & 0x7) +#define PDIV(x) ((x & 0x3f) << 8) +#define MDIV(x) ((x & 0x3ff) << 16) +#define FSEL(x) ((x & 0x1) << 27) +#define PLL_LOCKED_BIT (0x1 << 29) +#define PLL_ENABLE(x) ((x & 0x1) << 31)

+/* CLK_SRC_CPU */ +#define MUX_APLL_SEL(x) (x & 0x1) +#define MUX_CORE_SEL(x) ((x & 0x1) << 16) +#define MUX_HPM_SEL(x) ((x & 0x1) << 20) +#define MUX_MPLL_USER_SEL_C(x) ((x & 0x1) << 24)

+#define MUX_STAT_CHANGING 0x100

+/* CLK_MUX_STAT_CPU */ +#define APLL_SEL(x) (x & 0x7) +#define CORE_SEL(x) ((x & 0x7) << 16) +#define HPM_SEL(x) ((x & 0x7) << 20) +#define MPLL_USER_SEL_C(x) ((x & 0x7) << 24) +#define MUX_STAT_CPU_CHANGING (APLL_SEL(MUX_STAT_CHANGING) | \

• 		CORE_SEL(MUX_STAT_CHANGING) | \
  

• 		HPM_SEL(MUX_STAT_CHANGING) | \
  

• 		MPLL_USER_SEL_C(MUX_STAT_CHANGING))
  

+/* CLK_DIV_CPU0 */ +#define CORE_RATIO(x) (x & 0x7) +#define COREM0_RATIO(x) ((x & 0x7) << 4) +#define COREM1_RATIO(x) ((x & 0x7) << 8) +#define PERIPH_RATIO(x) ((x & 0x7) << 12) +#define ATB_RATIO(x) ((x & 0x7) << 16) +#define PCLK_DBG_RATIO(x) ((x & 0x7) << 20) +#define APLL_RATIO(x) ((x & 0x7) << 24) +#define CORE2_RATIO(x) ((x & 0x7) << 28)

+/* CLK_DIV_STAT_CPU0 */ +#define DIV_CORE(x) (x & 0x1) +#define DIV_COREM0(x) ((x & 0x1) << 4) +#define DIV_COREM1(x) ((x & 0x1) << 8) +#define DIV_PERIPH(x) ((x & 0x1) << 12) +#define DIV_ATB(x) ((x & 0x1) << 16) +#define DIV_PCLK_DBG(x) ((x & 0x1) << 20) +#define DIV_APLL(x) ((x & 0x1) << 24) +#define DIV_CORE2(x) ((x & 0x1) << 28)

+#define DIV_STAT_CHANGING 0x1 +#define DIV_STAT_CPU0_CHANGING (DIV_CORE(DIV_STAT_CHANGING) | \

• 		DIV_COREM0(DIV_STAT_CHANGING) | \
  

• 		DIV_COREM1(DIV_STAT_CHANGING) | \
  

• 		DIV_PERIPH(DIV_STAT_CHANGING) | \
  

• 		DIV_ATB(DIV_STAT_CHANGING) | \
  

• 		DIV_PCLK_DBG(DIV_STAT_CHANGING) | \
  

• 		DIV_APLL(DIV_STAT_CHANGING) | \
  

• 		DIV_CORE2(DIV_STAT_CHANGING))
  

+/* CLK_DIV_CPU1 */ +#define COPY_RATIO(x) (x & 0x7) +#define HPM_RATIO(x) ((x & 0x7) << 4) +#define CORES_RATIO(x) ((x & 0x7) << 8)

+/* CLK_DIV_STAT_CPU1 */ +#define DIV_COPY(x) (x & 0x7) +#define DIV_HPM(x) ((x & 0x1) << 4) +#define DIV_CORES(x) ((x & 0x1) << 8)

+#define DIV_STAT_CPU1_CHANGING (DIV_COPY(DIV_STAT_CHANGING) | \

• 		DIV_HPM(DIV_STAT_CHANGING) | \
  

• 		DIV_CORES(DIV_STAT_CHANGING))
  

+/* CLK_SRC_DMC */ +#define MUX_C2C_SEL(x) (x & 0x1) +#define MUX_DMC_BUS_SEL(x) ((x & 0x1) << 4) +#define MUX_DPHY_SEL(x) ((x & 0x1) << 8) +#define MUX_MPLL_SEL(x) ((x & 0x1) << 12) +#define MUX_PWI_SEL(x) ((x & 0xf) << 16) +#define MUX_G2D_ACP0_SEL(x) ((x & 0x1) << 20) +#define MUX_G2D_ACP1_SEL(x) ((x & 0x1) << 24) +#define MUX_G2D_ACP_SEL(x) ((x & 0x1) << 28)

+/* CLK_MUX_STAT_DMC */ +#define C2C_SEL(x) ((x) & 0x7) +#define DMC_BUS_SEL(x) ((x & 0x7) << 4) +#define DPHY_SEL(x) ((x & 0x7) << 8) +#define MPLL_SEL(x) ((x & 0x7) << 12) +/* #define PWI_SEL(x) ((x & 0xf) << 16) - Reserved */ +#define G2D_ACP0_SEL(x) ((x & 0x7) << 20) +#define G2D_ACP1_SEL(x) ((x & 0x7) << 24) +#define G2D_ACP_SEL(x) ((x & 0x7) << 28)

+#define MUX_STAT_DMC_CHANGING (C2C_SEL(MUX_STAT_CHANGING) | \

• 		DMC_BUS_SEL(MUX_STAT_CHANGING) | \
  

• 		DPHY_SEL(MUX_STAT_CHANGING) | \
  

• 		MPLL_SEL(MUX_STAT_CHANGING) |\
  

• 		G2D_ACP0_SEL(MUX_STAT_CHANGING) | \
  

• 		G2D_ACP1_SEL(MUX_STAT_CHANGING) | \
  

• 		G2D_ACP_SEL(MUX_STAT_CHANGING))
  

+/* CLK_DIV_DMC0 */ +#define ACP_RATIO(x) (x & 0x7) +#define ACP_PCLK_RATIO(x) ((x & 0x7) << 4) +#define DPHY_RATIO(x) ((x & 0x7) << 8) +#define DMC_RATIO(x) ((x & 0x7) << 12) +#define DMCD_RATIO(x) ((x & 0x7) << 16) +#define DMCP_RATIO(x) ((x & 0x7) << 20)

+/* CLK_DIV_STAT_DMC0 */ +#define DIV_ACP(x) (x & 0x1) +#define DIV_ACP_PCLK(x) ((x & 0x1) << 4) +#define DIV_DPHY(x) ((x & 0x1) << 8) +#define DIV_DMC(x) ((x & 0x1) << 12) +#define DIV_DMCD(x) ((x & 0x1) << 16) +#define DIV_DMCP(x) ((x & 0x1) << 20)

+#define DIV_STAT_DMC0_CHANGING (DIV_ACP(DIV_STAT_CHANGING) | \

• 		DIV_ACP_PCLK(DIV_STAT_CHANGING) | \
  

• 		DIV_DPHY(DIV_STAT_CHANGING) | \
  

• 		DIV_DMC(DIV_STAT_CHANGING) | \
  

• 		DIV_DMCD(DIV_STAT_CHANGING) | \
  

• 		DIV_DMCP(DIV_STAT_CHANGING))
  

+/* CLK_DIV_DMC1 */ +#define G2D_ACP_RATIO(x) (x & 0xf) +#define C2C_RATIO(x) ((x & 0x7) << 4) +#define PWI_RATIO(x) ((x & 0xf) << 8) +#define C2C_ACLK_RATIO(x) ((x & 0x7) << 12) +#define DVSEM_RATIO(x) ((x & 0x7f) << 16) +#define DPM_RATIO(x) ((x & 0x7f) << 24)

+/* CLK_DIV_STAT_DMC1 */ +#define DIV_G2D_ACP(x) (x & 0x1) +#define DIV_C2C(x) ((x & 0x1) << 4) +#define DIV_PWI(x) ((x & 0x1) << 8) +#define DIV_C2C_ACLK(x) ((x & 0x1) << 12) +#define DIV_DVSEM(x) ((x & 0x1) << 16) +#define DIV_DPM(x) ((x & 0x1) << 24)

+#define DIV_STAT_DMC1_CHANGING (DIV_G2D_ACP(DIV_STAT_CHANGING) | \

• 		DIV_C2C(DIV_STAT_CHANGING) | \
  

• 		DIV_PWI(DIV_STAT_CHANGING) | \
  

• 		DIV_C2C_ACLK(DIV_STAT_CHANGING) | \
  

• 		DIV_DVSEM(DIV_STAT_CHANGING) | \
  

• 		DIV_DPM(DIV_STAT_CHANGING))
  

+/* Set CLK_SRC_PERIL0 */ +#define UART4_SEL(x) ((x & 0xf) << 16) +#define UART3_SEL(x) ((x & 0xf) << 12) +#define UART2_SEL(x) ((x & 0xf) << 8) +#define UART1_SEL(x) ((x & 0xf) << 4) +#define UART0_SEL(x) ((x) & 0xf)

+/* Set CLK_DIV_PERIL0 */ +#define UART4_RATIO(x) ((x & 0xf) << 16) +#define UART3_RATIO(x) ((x & 0xf) << 12) +#define UART2_RATIO(x) ((x & 0xf) << 8) +#define UART1_RATIO(x) ((x & 0xf) << 4) +#define UART0_RATIO(x) ((x) & 0xf)

+/* Set CLK_DIV_STAT_PERIL0 */ +#define DIV_UART4(x) ((x & 0x1) << 16) +#define DIV_UART3(x) ((x & 0x1) << 12) +#define DIV_UART2(x) ((x & 0x1) << 8) +#define DIV_UART1(x) ((x & 0x1) << 4) +#define DIV_UART0(x) ((x) & 0x1)

+#define DIV_STAT_PERIL0_CHANGING (DIV_UART4(DIV_STAT_CHANGING) | \

• 			DIV_UART3(DIV_STAT_CHANGING) | \
  

• 			DIV_UART2(DIV_STAT_CHANGING) | \
  

• 			DIV_UART1(DIV_STAT_CHANGING) | \
  

• 			DIV_UART0(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS1 */ +#define MMC0_RATIO(x) ((x) & 0xf) +#define MMC0_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC1_RATIO(x) ((x & 0xf) << 16) +#define MMC1_PRE_RATIO(x) ((x & 0xff) << 24)

+/* CLK_DIV_STAT_FSYS1 */ +#define DIV_MMC0(x) ((x) & 1) +#define DIV_MMC0_PRE(x) ((x & 1) << 8) +#define DIV_MMC1(x) ((x & 1) << 16) +#define DIV_MMC1_PRE(x) ((x & 1) << 24)

+#define DIV_STAT_FSYS1_CHANGING (DIV_MMC0(DIV_STAT_CHANGING) | \

• 			DIV_MMC0_PRE(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC1(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC1_PRE(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS2 */ +#define MMC2_RATIO(x) (x & 0xf) +#define MMC2_PRE_RATIO(x) ((x & 0xff) << 8) +#define MMC3_RATIO(x) ((x & 0xf) << 16) +#define MMC3_PRE_RATIO(x) ((x & 0xff) << 24)

+/* CLK_DIV_STAT_FSYS2 */ +#define DIV_MMC2(x) (x & 0x1) +#define DIV_MMC2_PRE(x) ((x & 0x1) << 8) +#define DIV_MMC3(x) ((x & 0x1) << 16) +#define DIV_MMC3_PRE(x) ((x & 0x1) << 24)

+#define DIV_STAT_FSYS2_CHANGING (DIV_MMC2(DIV_STAT_CHANGING) | \

• 			DIV_MMC2_PRE(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC3(DIV_STAT_CHANGING) | \
  

• 			DIV_MMC3_PRE(DIV_STAT_CHANGING))
  

+/* CLK_DIV_FSYS3 */ +#define MMC4_RATIO(x) (x & 0x7) +#define MMC4_PRE_RATIO(x) ((x & 0xff) << 8)

+/* CLK_DIV_STAT_FSYS3 */ +#define DIV_MMC4(x) (x & 0x1) +#define DIV_MMC4_PRE(x) ((x & 0x1) << 8)

+#define DIV_STAT_FSYS3_CHANGING (DIV_MMC4(DIV_STAT_CHANGING) | \

• 			DIV_MMC4_PRE(DIV_STAT_CHANGING))
  

+#endif /*__ODROIDU3_SETUP__ */

On 07/04/2014 05:08 PM, Przemyslaw Marczak wrote:

On 07/04/2014 08:07 AM, Jaehoon Chung wrote:

...

On 07/02/2014 08:50 PM, Przemyslaw Marczak wrote:

...

This board file supports standard features of Odroid X2 and U3 boards:

• Exynos4412 core clock set to 1000MHz and MPLL peripherial clock set to 800MHz,
• MAX77686 power regulator,
• USB PHY,
• enable XCL205 - power for board peripherials
• check board type: U3 or X2.
• enable Odroid U3 FAN cooler

Signed-off-by: Przemyslaw Marczak p.marczak@samsung.com Cc: Minkyu Kang mk7.kang@samsung.com Cc: Tom Rini trini@ti.com

---

Changes v2:

• enable fan on odroid U3

Changes v3:

• odroid.c: clean up board name related code
• odroid.c: remove static from set_board_type()
• odroid.c: add implementation of functions: get_dfu_alt_*
• odroid.c: include misc.h

Changes v4: odroid.c: dfu_get_alt_boot: add call get_boot_mode()

---

board/samsung/odroid/Makefile | 8 + board/samsung/odroid/odroid.c | 466 ++++++++++++++++++++++++++++++++++++++++++ board/samsung/odroid/setup.h | 227 ++++++++++++++++++++ 3 files changed, 701 insertions(+) create mode 100644 board/samsung/odroid/Makefile create mode 100644 board/samsung/odroid/odroid.c create mode 100644 board/samsung/odroid/setup.h

diff --git a/board/samsung/odroid/Makefile b/board/samsung/odroid/Makefile new file mode 100644 index 0000000..b98aaeb --- /dev/null +++ b/board/samsung/odroid/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2014 Samsung Electronics Co., Ltd. All rights reserved. +# Przemyslaw Marczak p.marczak@samsung.com +# +# SPDX-License-Identifier: GPL-2.0+ +#

+obj-y := odroid.o diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c new file mode 100644 index 0000000..28706af --- /dev/null +++ b/board/samsung/odroid/odroid.c @@ -0,0 +1,466 @@ +/*

• • Copyright (C) 2014 Samsung Electronics
• • Przemyslaw Marczak p.marczak@samsung.com
• • SPDX-License-Identifier: GPL-2.0+
• */

+#include <common.h> +#include <asm/arch/pinmux.h> +#include <asm/arch/power.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/gpio.h> +#include <asm/arch/cpu.h> +#include <power/pmic.h> +#include <power/max77686_pmic.h> +#include <errno.h> +#include <usb.h> +#include <usb/s3c_udc.h> +#include <samsung/misc.h> +#include "setup.h"

+DECLARE_GLOBAL_DATA_PTR;

+#ifdef CONFIG_BOARD_TYPES +/* Odroid board types */ +enum {

• ODROID_TYPE_U3,
• ODROID_TYPE_X2,

+};

+void set_board_type(void) +{

• int val;
• /* Check GPC1 pin 2 */
• gpio_set_pull(EXYNOS4X12_GPIO_C12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_C12, S5P_GPIO_DRV_4X);
• gpio_direction_input(EXYNOS4X12_GPIO_C12);
• /* XCL205 - needs some latch time */
• mdelay(10);
• /* Check GPC1 pin2 - LED supplied by XCL205 - X2 only */
• val = gpio_get_value(EXYNOS4X12_GPIO_C12);
• if (val)

val is unnecessary. "int val" can be removed. if (gpio_get_value(EXYNS4x12_GPIO_C12)) ....

ok

...

...

•    gd->board_type = ODROID_TYPE_X2;
  

• else

•    gd->board_type = ODROID_TYPE_U3;
  

+}

+const char *get_board_name(void) +{

• const char *board_name = "odroid";

Is there other approach or general method for getting board name?

Actually, the board name is the same as CONFIG_SYS_BOARD, but we are going to have only one binary for Exynos 4 boards in the future - so such function is welcome. We can also put this into the dts file.

In future...Then using dt-file would be better than this. :)

Best Regards, Jaehoon Chung

...

...

• return board_name;

+}

+const char *get_board_type(void) +{

• const char *board_type[] = {"u3", "x2"};
• return board_type[gd->board_type];

+} +#endif

+#ifdef CONFIG_SET_DFU_ALT_INFO +char *get_dfu_alt_system(void) +{

• return getenv("dfu_alt_system");

+}

+char *get_dfu_alt_boot(void) +{

• char *alt_boot = NULL;
• switch (get_boot_mode()) {
• case BOOT_MODE_MMC:

•    alt_boot = CONFIG_DFU_ALT_BOOT_SD;
  

•    break;
  

• default:

•    alt_boot = CONFIG_DFU_ALT_BOOT_EMMC;
  

•    break;
  

• }
• if (!alt_boot)

•    return NULL;
  

Is it need? alt_boot is set to CONFIG_DFU_ALT_BOOT_EMMC by default, isn't? CONFIG_DFU_ALT_BOOT_EMMC is 0?

Oops, right. I must fix that.

...

...

• setenv("dfu_alt_boot", alt_boot);
• return alt_boot;

+} +#endif

+static void board_clock_init(void) +{

• unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc;
• struct exynos4x12_clock *clk = (struct exynos4x12_clock *)

•                    samsung_get_base_clock();
  

• /*

• * CMU_CPU clocks src to MPLL
  

• * Bit values:                 0  ; 1
  

• * MUX_APLL_SEL:        FIN_PLL   ; FOUT_APLL
  

• * MUX_CORE_SEL:        MOUT_APLL ; SCLK_MPLL
  

• * MUX_HPM_SEL:         MOUT_APLL ; SCLK_MPLL_USER_C
  

• * MUX_MPLL_USER_SEL_C: FIN_PLL   ; SCLK_MPLL
  

• */
• clr_src_cpu = MUX_APLL_SEL(0x1) | MUX_CORE_SEL(0x1) |

•          MUX_HPM_SEL(0x1) | MUX_MPLL_USER_SEL_C(0x1);
  

• set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) |

•      MUX_MPLL_USER_SEL_C(1);
  

0x1 or 1? you can use it consistency. MUX_APLL_SEL(1) or MUX_APLL_SEL(0x1).

ok, will be fixed.

...

...

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

•    continue;
  

• /* Set APLL to 1000MHz */
• clr_pll_con0 = SDIV(0x7) | PDIV(0x3f) | MDIV(0x3ff) | FSEL(0x1);
• set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1);
• clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT))

•    continue;
  

• /* Set CMU_CPU clocks src to APLL */
• set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) |

•      MUX_MPLL_USER_SEL_C(1);
  

• clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING)

•    continue;
  

• set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) |

•      PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) |
  

•      APLL_RATIO(0) | CORE2_RATIO(0);
  

• /*

• * Set dividers for MOUTcore = 1000 MHz
  

• * coreout =      MOUT / (ratio + 1) = 1000 MHz (0)
  

• * corem0 =     armclk / (ratio + 1) = 333 MHz (2)
  

• * corem1 =     armclk / (ratio + 1) = 166 MHz (5)
  

• * periph =     armclk / (ratio + 1) = 1000 MHz (0)
  

• * atbout =       MOUT / (ratio + 1) = 200 MHz (4)
  

• * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)
  

• * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)
  

• * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)
  

• */
• clr = CORE_RATIO(0x7) | COREM0_RATIO(0x7) | COREM1_RATIO(0x7) |

•      PERIPH_RATIO(0x7) | ATB_RATIO(0x7) | PCLK_DBG_RATIO(0x7) |
  

•      APLL_RATIO(0x7) | CORE2_RATIO(0x7);
  

• clrsetbits_le32(&clk->div_cpu0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING)

•    continue;
  

• /*

• * For MOUThpm = 1000 MHz (MOUTapll)
  

• * doutcopy = MOUThpm / (ratio + 1) = 200 (4)
  

• * sclkhpm = doutcopy / (ratio + 1) = 200 (4)
  

• * cores_out = armclk / (ratio + 1) = 1000 (0)
  

• */
  

• clr = COPY_RATIO(0x7) | HPM_RATIO(0x7) | CORES_RATIO(0x7);
• set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0);
• clrsetbits_le32(&clk->div_cpu1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING)

•    continue;
  

• /*

• * Set CMU_DMC clocks src to APLL
  

• * Bit values:             0  ; 1
  

• * MUX_C2C_SEL:      SCLKMPLL ; SCLKAPLL
  

• * MUX_DMC_BUS_SEL:  SCLKMPLL ; SCLKAPLL
  

• * MUX_DPHY_SEL:     SCLKMPLL ; SCLKAPLL
  

• * MUX_MPLL_SEL:     FINPLL   ; MOUT_MPLL_FOUT
  

• * MUX_PWI_SEL:      0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI)
  

• * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL
  

• * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL
  

• * MUX_G2D_ACP_SEL:  OUT_ACP0 ; OUT_ACP1
  

• */
• clr_src_dmc = MUX_C2C_SEL(0x1) | MUX_DMC_BUS_SEL(0x1) |

•          MUX_DPHY_SEL(0x1) | MUX_MPLL_SEL(0x1) |
  

•          MUX_PWI_SEL(0xf) | MUX_G2D_ACP0_SEL(0x1) |
  

•          MUX_G2D_ACP1_SEL(0x1) | MUX_G2D_ACP_SEL(0x1);
  

• set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) |

•      MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) |
  

•      MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

•    continue;
  

• /* Set MPLL to 800MHz */
• set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1);
• clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set);
• /* Wait for PLL to be locked */
• while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT))

•    continue;
  

• /* Switch back CMU_DMC mux */
• set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) |

•      MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) |
  

•      MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0);
  

• clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set);
• /* Wait for mux change */
• while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING)

•    continue;
  

• /* CLK_DIV_DMC0 */
• clr = ACP_RATIO(0x7) | ACP_PCLK_RATIO(0x7) | DPHY_RATIO(0x7) |

•      DMC_RATIO(0x7) | DMCD_RATIO(0x7) | DMCP_RATIO(0x7);
  

• /*

• * For:
  

• * MOUTdmc = 800 MHz
  

• * MOUTdphy = 800 MHz
  

• *
  

• * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3)
  

• * pclk_acp = aclk_acp / (ratio + 1) = 100 (1)
  

• * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1)
  

• * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1)
  

• * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1)
  

• * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1)
  

• */
  

• set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) |

•      DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc0, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING)

•    continue;
  

• /* CLK_DIV_DMC1 */
• clr = G2D_ACP_RATIO(0xf) | C2C_RATIO(0x7) | PWI_RATIO(0xf) |

•      C2C_ACLK_RATIO(0x7) | DVSEM_RATIO(0x7f) | DPM_RATIO(0x7f);
  

• /*

• * For:
  

• * MOUTg2d = 800 MHz
  

• * MOUTc2c = 800 Mhz
  

• * MOUTpwi = 108 MHz
  

• *
  

• * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1)
  

• * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1)
  

• * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1)
  

• * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5)
  

• */
  

• set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) |

•      C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1);
  

• clrsetbits_le32(&clk->div_dmc1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING)

•    continue;
  

• /* CLK_SRC_PERIL0 */
• clr = UART0_SEL(0xf) | UART1_SEL(0xf) | UART2_SEL(0xf) |

•      UART3_SEL(0xf) | UART4_SEL(0xf);
  

• /*

• * Set CLK_SRC_PERIL0 clocks src to MPLL
  

• * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0);
  

• *             5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL);
  

• *             8(SCLK_VPLL)
  

• *
  

• * Set all to SCLK_MPLL_USER_T
  

• */
  

• set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) |

•      UART4_SEL(6);
  

• clrsetbits_le32(&clk->src_peril0, clr, set);
• /* CLK_DIV_PERIL0 */
• clr = UART0_RATIO(0xf) | UART1_RATIO(0xf) | UART2_RATIO(0xf) |

•      UART3_RATIO(0xf) | UART4_RATIO(0xf);
  

• /*

• * For MOUTuart0-4: 800MHz
  

• *
  

• * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7)
  

• */
• set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) |

•      UART3_RATIO(7) | UART4_RATIO(7);
  

• clrsetbits_le32(&clk->div_peril0, clr, set);
• while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING)

•    continue;
  

• /* CLK_DIV_FSYS1 */
• clr = MMC0_RATIO(0xf) | MMC0_PRE_RATIO(0xff) | MMC1_RATIO(0xf) |

•      MMC1_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7)
  

• * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)
  

• * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7)
  

• * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)
  

• */
• set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) |

•      MMC1_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys1, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING)

•    continue;
  

• /* CLK_DIV_FSYS2 */
• clr = MMC2_RATIO(0xf) | MMC2_PRE_RATIO(0xff) | MMC3_RATIO(0xf) |

•      MMC3_PRE_RATIO(0xff);
  

• /*

• * For MOUTmmc0-3 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7)
  

• * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)
  

• * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7)
  

• * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)
  

• */
• set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) |

•      MMC3_PRE_RATIO(1);
  

• clrsetbits_le32(&clk->div_fsys2, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING)

•    continue;
  

• /* CLK_DIV_FSYS3 */
• clr = MMC4_RATIO(0xf) | MMC4_PRE_RATIO(0xff);
• /*

• * For MOUTmmc4 = 800 MHz (MPLL)
  

• *
  

• * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7)
  

• * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0)
  

• */
• set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0);
• clrsetbits_le32(&clk->div_fsys3, clr, set);
• /* Wait for divider ready status */
• while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING)

•    continue;
  

• return;

+}

+static void board_gpio_init(void) +{

• /* Set GPA1 pin 1 to HI - enable XCL205 output */
• gpio_set_pull(EXYNOS4X12_GPIO_A11, S5P_GPIO_PULL_UP);
• gpio_set_drv(EXYNOS4X12_GPIO_A11, S5P_GPIO_DRV_4X);
• gpio_direction_output(EXYNOS4X12_GPIO_A11, 1);
• gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1));
• gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE);
• gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X);
• /* Enable FAN (Odroid U3) */
• gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP);
• gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X);
• gpio_direction_output(EXYNOS4X12_GPIO_D00, 1);

+}

+static int pmic_init_max77686(void) +{

• struct pmic *p = pmic_get("MAX77686_PMIC");
• if (pmic_probe(p))

•    return -ENODEV;
  

• /* Set LDO Voltage */
• max77686_set_ldo_voltage(p, 20, 1800000); /* LDO20 eMMC */
• max77686_set_ldo_voltage(p, 21, 2800000); /* LDO21 SD */
• max77686_set_ldo_voltage(p, 22, 2800000); /* LDO22 eMMC */

LDO20/22 are used the eMMC? VDD/VDD-IO power?

Yes, those are the pull-up voltage sources for eMMC and SD.

Thank you,