[PATCH 0/3] Unify K3 initial memory map
Hello all,
This was an RFC as it might still break remoteproc loading, but posted now for merge as worst case this would expose the issue in remoteproc loading better and force someone to go fix it. :)
Changes for non-RFC: - Included dependency patch from here[0] into this series - Add Tested-bys - Rebase on latest -next
Thanks, Andrew
[0] https://lore.kernel.org/all/20231122211218.607757-1-afd@ti.com/
Andrew Davis (3): arm: mach-k3: Let the compiler size the mem_map lists arm: mach-k3: Remove non-cached memory map areas arm: mach-k3: Merge initial memory maps
arch/arm/mach-k3/arm64-mmu.c | 275 +---------------------------------- 1 file changed, 2 insertions(+), 273 deletions(-)
NR_MMU_REGIONS is a copy/paste from another platform that extends this list later. We do not do that, so let the list be the size of the initializer list.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 35 ++++++----------------------------- 1 file changed, 6 insertions(+), 29 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index e8db5332ae0..d872ed714c4 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -13,11 +13,7 @@ #include <asm/armv8/mmu.h>
#ifdef CONFIG_SOC_K3_AM654 -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region am654_mem_map[NR_MMU_REGIONS] = { +struct mm_region am654_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -68,10 +64,7 @@ struct mm_region *mem_map = am654_mem_map; #ifdef CONFIG_SOC_K3_J721E
#ifdef CONFIG_SOC_K3_J721E_J7200 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 5) - -/* ToDo: Add 64bit IO */ -struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { +struct mm_region j7200_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -119,12 +112,7 @@ struct mm_region j7200_mem_map[NR_MMU_REGIONS] = { struct mm_region *mem_map = j7200_mem_map;
#else /* CONFIG_SOC_K3_J721E_J7200 */ - -/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 6) - -/* ToDo: Add 64bit IO */ -struct mm_region j721e_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721e_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -181,10 +169,7 @@ struct mm_region *mem_map = j721e_mem_map; #endif /* CONFIG_SOC_K3_J721E */
#ifdef CONFIG_SOC_K3_J721S2 -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) - -/* ToDo: Add 64bit IO */ -struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = { +struct mm_region j721s2_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -223,11 +208,7 @@ struct mm_region *mem_map = j721s2_mem_map;
#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7)
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am62_mem_map[NR_MMU_REGIONS] = { +struct mm_region am62_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -272,11 +253,7 @@ struct mm_region *mem_map = am62_mem_map;
#ifdef CONFIG_SOC_K3_AM642
-/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) - -/* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { +struct mm_region am64_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL,
All normal memory areas should be mapped as such.
We added these un-cached holes in our memory map to hack around the remoteproc driver missing the proper cache maintenance operations.
The problem is having these non-cached memory map areas causes stability issues later in system operation due to the nature of the K3 coherency architecture. Plus these are board specific carveouts and instead should have been added at the board level, not here in the SoC common code area.
Remove these non-cached memory map areas.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 65 +++--------------------------------- 1 file changed, 5 insertions(+), 60 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index d872ed714c4..97a029af13f 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -24,19 +24,7 @@ struct mm_region am654_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x02100000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa2100000UL, - .phys = 0xa2100000UL, - .size = 0x5df00000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -75,19 +63,7 @@ struct mm_region j7200_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x04800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xa4800000UL, - .phys = 0xa4800000UL, - .size = 0x5b800000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -123,19 +99,7 @@ struct mm_region j721e_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x20000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xa0000000UL, - .phys = 0xa0000000UL, - .size = 0x1bc00000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_NON_SHARE - }, { - .virt = 0xbbc00000UL, - .phys = 0xbbc00000UL, - .size = 0x44400000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { @@ -151,12 +115,6 @@ struct mm_region j721e_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x4d80000000UL, - .phys = 0x4d80000000UL, - .size = 0x0002000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | - PTE_BLOCK_INNER_SHARE }, { /* List terminator */ 0, @@ -219,16 +177,9 @@ struct mm_region am62_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x1E780000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { .virt = 0x880000000UL, .phys = 0x880000000UL, @@ -264,13 +215,7 @@ struct mm_region am64_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, - .size = 0x1E800000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0xA0000000UL, - .phys = 0xA0000000UL, - .size = 0x60000000UL, + .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, {
On 11/23/2023 10:52 PM, Andrew Davis wrote:
@@ -219,16 +177,9 @@ struct mm_region am62_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x1E780000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE- }, {
.virt = 0xA0000000UL,.phys = 0xA0000000UL,.size = 0x60000000UL,
.size = 0x80000000UL,
- }, { .virt = 0x880000000UL, .phys = 0x880000000UL,
This causes issues when TF-A region @0x9e780000 is firewalled off from non-secure world. A53 does speculative accesses to this region from EL1 leading to FW exceptions being reported on TIFS log (although A53 itself doesn't seem to abort)
On 23:04-20231123, Vignesh Raghavendra wrote:
On 11/23/2023 10:52 PM, Andrew Davis wrote:
@@ -219,16 +177,9 @@ struct mm_region am62_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x1E780000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE- }, {
.virt = 0xA0000000UL,.phys = 0xA0000000UL,.size = 0x60000000UL,
.size = 0x80000000UL,
- }, { .virt = 0x880000000UL, .phys = 0x880000000UL,
This causes issues when TF-A region @0x9e780000 is firewalled off from non-secure world. A53 does speculative accesses to this region from EL1 leading to FW exceptions being reported on TIFS log (although A53 itself doesn't seem to abort)
Hmm... Why not just manage the ones that use TFA in DDR seperately? I suppose OPTEE will come in the way?
Looks like the no-map is not honored well.. as you were mentioning, a zephyr style generating the map from dts might be much better, but then we do support multiple dtbs as well..
OK - I guess we need to leave this cleanup for now.
On 11/27/23 9:47 AM, Nishanth Menon wrote:
On 23:04-20231123, Vignesh Raghavendra wrote:
On 11/23/2023 10:52 PM, Andrew Davis wrote:
@@ -219,16 +177,9 @@ struct mm_region am62_mem_map[] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL,
.size = 0x1E780000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |PTE_BLOCK_INNER_SHARE- }, {
.virt = 0xA0000000UL,.phys = 0xA0000000UL,.size = 0x60000000UL,
.size = 0x80000000UL,
- }, { .virt = 0x880000000UL, .phys = 0x880000000UL,
This causes issues when TF-A region @0x9e780000 is firewalled off from non-secure world. A53 does speculative accesses to this region from EL1 leading to FW exceptions being reported on TIFS log (although A53 itself doesn't seem to abort)
Hmm... Why not just manage the ones that use TFA in DDR seperately? I suppose OPTEE will come in the way?
Looks like the no-map is not honored well.. as you were mentioning, a zephyr style generating the map from dts might be much better, but then we do support multiple dtbs as well..
OK - I guess we need to leave this cleanup for now.
We can make the same cleanup while leaving the firewall hole in place (it is in the same spot for all SoCs today so no problem here). I'll send a v2 with that.
Andrew
The Device vs Normal memory map is the same for all K3 SoCs. Merge the SoC specific maps into one.
Signed-off-by: Andrew Davis afd@ti.com Reviewed-by: Nishanth Menon nm@ti.com Tested-by: Nishanth Menon nm@ti.com --- arch/arm/mach-k3/arm64-mmu.c | 197 +---------------------------------- 1 file changed, 2 insertions(+), 195 deletions(-)
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 97a029af13f..ccc4161be99 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -12,8 +12,7 @@ #include <asm/system.h> #include <asm/armv8/mmu.h>
-#ifdef CONFIG_SOC_K3_AM654 -struct mm_region am654_mem_map[] = { +struct mm_region k3_mem_map[] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -46,196 +45,4 @@ struct mm_region am654_mem_map[] = { } };
-struct mm_region *mem_map = am654_mem_map; -#endif /* CONFIG_SOC_K3_AM654 */ - -#ifdef CONFIG_SOC_K3_J721E - -#ifdef CONFIG_SOC_K3_J721E_J7200 -struct mm_region j7200_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j7200_mem_map; - -#else /* CONFIG_SOC_K3_J721E_J7200 */ -struct mm_region j721e_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721e_mem_map; -#endif /* CONFIG_SOC_K3_J721E_J7200 */ - -#endif /* CONFIG_SOC_K3_J721E */ - -#ifdef CONFIG_SOC_K3_J721S2 -struct mm_region j721s2_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = j721s2_mem_map; - -#endif /* CONFIG_SOC_K3_J721S2 */ - -#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) - -struct mm_region am62_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am62_mem_map; -#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ - -#ifdef CONFIG_SOC_K3_AM642 - -struct mm_region am64_mem_map[] = { - { - .virt = 0x0UL, - .phys = 0x0UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - .virt = 0x80000000UL, - .phys = 0x80000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x880000000UL, - .phys = 0x880000000UL, - .size = 0x80000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | - PTE_BLOCK_INNER_SHARE - }, { - .virt = 0x500000000UL, - .phys = 0x500000000UL, - .size = 0x400000000UL, - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { - /* List terminator */ - 0, - } -}; - -struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 */ +struct mm_region *mem_map = k3_mem_map;
participants (3)
-
Andrew Davis -
Nishanth Menon -
Raghavendra, Vignesh