[U-Boot] [PATCH] driver/fsl_pci: Added fsl_pci_init_port function to initialize a single PCIe port.

* Added a generic function fsl_pci_init_port in drivers/pci/fsl_pci.c to initialize a PCIe port. * fsl_pci_init_port can be called from board specific pcie initialization routine, per-port. * This will reduce the code redundancy in the most of the Freescale board specific PCIe inits.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org --- - applies on git.denx.de/u-boot-mpc85xx.git branch->next drivers/pci/fsl_pci_init.c | 41 +++++++++++++++++++++++++++++++++++++++++ include/asm-ppc/fsl_pci.h | 26 ++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 0 deletions(-)
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c index ee89aaa..9e9e1b7 100644 --- a/drivers/pci/fsl_pci_init.c +++ b/drivers/pci/fsl_pci_init.c @@ -412,6 +412,47 @@ void fsl_pci_init(struct pci_controller *hose, u32 cfg_addr, u32 cfg_data) } }
+int fsl_pci_init_port(struct fsl_pci_info *pci_info, + struct pci_controller *hose, int busno) +{ + volatile ccsr_fsl_pci_t *pci; + struct pci_region *r; + + pci = (ccsr_fsl_pci_t *) pci_info->regs; + + if (in_be32(&pci->pme_msg_det)) { + out_be32(&pci->pme_msg_det, 0xffffffff); + debug (" with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + + r = hose->regions + hose->region_count; + + /* outbound memory */ + pci_set_region(r++, + pci_info->mem_bus, + pci_info->mem_phys, + pci_info->mem_size, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region(r++, + pci_info->io_bus, + pci_info->io_phys, + pci_info->io_size, + PCI_REGION_IO); + + hose->region_count = r - hose->regions; + hose->first_busno = busno; + + fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); + + printf("\n PCIE%x on bus %02x - %02x\n", pci_info->pci_num, + hose->first_busno, hose->last_busno); + + return(hose->last_busno + 1); +} + /* Enable inbound PCI config cycles for agent/endpoint interface */ void fsl_pci_config_unlock(struct pci_controller *hose) { diff --git a/include/asm-ppc/fsl_pci.h b/include/asm-ppc/fsl_pci.h index b2ff0e9..2b6421a 100644 --- a/include/asm-ppc/fsl_pci.h +++ b/include/asm-ppc/fsl_pci.h @@ -154,4 +154,30 @@ typedef struct ccsr_pci { char res24[252]; } ccsr_fsl_pci_t;
+struct fsl_pci_info { + phys_size_t regs; + pci_addr_t mem_bus; + phys_size_t mem_phys; + pci_size_t mem_size; + pci_addr_t io_bus; + phys_size_t io_phys; + pci_size_t io_size; + int pci_num; +}; + +int fsl_pci_init_port(struct fsl_pci_info *pci_info, + struct pci_controller *hose, int busno); + +#define SET_STD_PCIE_INFO(x, num) \ +{ \ + x.regs = CONFIG_SYS_PCIE##num##_ADDR; \ + x.mem_bus = CONFIG_SYS_PCIE##num##_MEM_BUS; \ + x.mem_phys = CONFIG_SYS_PCIE##num##_MEM_PHYS; \ + x.mem_size = CONFIG_SYS_PCIE##num##_MEM_SIZE; \ + x.io_bus = CONFIG_SYS_PCIE##num##_IO_BUS; \ + x.io_phys = CONFIG_SYS_PCIE##num##_IO_PHYS; \ + x.io_size = CONFIG_SYS_PCIE##num##_IO_SIZE; \ + x.pci_num = num; \ +} + #endif

Dear Poonam Aggrwal,
In message 1250775038-20372-1-git-send-email-poonam.aggrwal@freescale.com you wrote:
- Added a generic function fsl_pci_init_port in drivers/pci/fsl_pci.c to initialize a PCIe port.
- fsl_pci_init_port can be called from board specific pcie initialization routine, per-port.
- This will reduce the code redundancy in the most of the Freescale board specific PCIe inits.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
NAK.
I see just dead code added, without any users.
If this gets used somewhere, this should be visible in the patch, and lead to code removed somewhere?
Best regards,
Wolfgang Denk

On Aug 20, 2009, at 10:12 AM, Wolfgang Denk wrote:
Dear Poonam Aggrwal,
In message <1250775038-20372-1-git-send-email-poonam.aggrwal@freescale.com
you wrote:
- Added a generic function fsl_pci_init_port in drivers/pci/
fsl_pci.c to initialize a PCIe port.
- fsl_pci_init_port can be called from board specific pcie
initialization routine, per-port.
- This will reduce the code redundancy in the most of the
Freescale board specific PCIe inits.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
NAK.
I see just dead code added, without any users.
If this gets used somewhere, this should be visible in the patch, and lead to code removed somewhere?
It gets used in the patch 'Added PCIe support for P1 P2 RDB'. I also will look at using it on other boards to remove code.
However I don't think we need one patch that adds the interface and does the board code changes or additions (unless you have to do them to keep compiling sane).
I agree this should have been label'd 1/2 and the 'Added PCIe support for P1/P2 RDB' as 2/2.
- k

-----Original Message----- From: Kumar Gala [mailto:galak@kernel.crashing.org] Sent: Thursday, August 20, 2009 8:54 PM To: Wolfgang Denk Cc: Aggrwal Poonam-B10812; u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] driver/fsl_pci: Added fsl_pci_init_port function to initialize a single PCIe port.
On Aug 20, 2009, at 10:12 AM, Wolfgang Denk wrote:
Dear Poonam Aggrwal,
In message <1250775038-20372-1-git-send-email-poonam.aggrwal@freescale.com
you wrote:
- Added a generic function fsl_pci_init_port in drivers/pci/
fsl_pci.c to initialize a PCIe port.
- fsl_pci_init_port can be called from board specific pcie
initialization routine, per-port.
- This will reduce the code redundancy in the most of the
Freescale
board specific PCIe inits.
Signed-off-by: Poonam Aggrwal poonam.aggrwal@freescale.com Signed-off-by: Kumar Gala galak@kernel.crashing.org
NAK.
I see just dead code added, without any users.
If this gets used somewhere, this should be visible in the
patch, and
lead to code removed somewhere?
It gets used in the patch 'Added PCIe support for P1 P2 RDB'. I also will look at using it on other boards to remove code.
However I don't think we need one patch that adds the interface and does the board code changes or additions (unless you have to do them to keep compiling sane).
I agree this should have been label'd 1/2 and the 'Added PCIe support for P1/P2 RDB' as 2/2.
Yes my mistake here, I should have shown the patch dependancy.
- k
participants (4)
-
Aggrwal Poonam-B10812
-
Kumar Gala
-
Poonam Aggrwal
-
Wolfgang Denk