[PATCH 1/2] spi: ich: Limit slave->max_read_size

Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode.
ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number.
Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
drivers/spi/ich.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 3d49c22a9d..08d54e86f4 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -918,12 +918,14 @@ static int ich_spi_child_pre_probe(struct udevice *dev) struct spi_slave *slave = dev_get_parent_priv(dev);
/* - * Yes this controller can only write a small number of bytes at + * Yes this controller can only transfer a small number of bytes at * once! The limit is typically 64 bytes. For hardware sequencing a * a loop is used to get around this. */ - if (!plat->hwseq) + if (!plat->hwseq) { + slave->max_read_size = priv->databytes; slave->max_write_size = priv->databytes; + } /* * ICH 7 SPI controller only supports array read command * and byte program command for SST flash

Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to the spi-nor core.
Signed-off-by: Bin Meng bmeng.cn@gmail.com ---
configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/crownbay_defconfig b/configs/crownbay_defconfig index af8fb0d805..1208aad42f 100644 --- a/configs/crownbay_defconfig +++ b/configs/crownbay_defconfig @@ -47,6 +47,7 @@ CONFIG_TFTP_TSIZE=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CPU=y +# CONFIG_SPI_FLASH_SMART_HWCAPS is not set CONFIG_E1000=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y

On Wed, 28 Jul 2021 at 04:29, Bin Meng bmeng.cn@gmail.com wrote:
Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to the spi-nor core.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org

On Thu, Jul 29, 2021 at 9:45 AM Simon Glass sjg@chromium.org wrote:
On Wed, 28 Jul 2021 at 04:29, Bin Meng bmeng.cn@gmail.com wrote:
Since commit 71025f013ccb ("mtd: spi-nor-core: Rework hwcaps selection") SPI flash on Intel Crown Bay board does not work anymore.
Disable CONFIG_SPI_FLASH_SMART_HWCAPS until a proper fix is made to the spi-nor core.
Signed-off-by: Bin Meng bmeng.cn@gmail.com
configs/crownbay_defconfig | 1 + 1 file changed, 1 insertion(+)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!

On Wed, 28 Jul 2021 at 04:29, Bin Meng bmeng.cn@gmail.com wrote:
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode.
ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number.
Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/spi/ich.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org

On Thu, Jul 29, 2021 at 9:32 AM Simon Glass sjg@chromium.org wrote:
On Wed, 28 Jul 2021 at 04:29, Bin Meng bmeng.cn@gmail.com wrote:
Since commit 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") (in v2020.04-rc1), SPI flash read no longer works with ICH SPI controller in software sequencer mode.
ICH controller can only transfer a small number of bytes at once. Before commit 43c145b8b3ee, the logic happens to make sure data.nbytes is limited to slave->max_write_size but after commit 43c145b8b3ee data.nbytes is no longer limited because slave->max_read_size is not initialized with a valid number.
Fixes: 43c145b8b3ee ("spi: ich: Correct max-size bug in ich_spi_adjust_size()") Signed-off-by: Bin Meng bmeng.cn@gmail.com
drivers/spi/ich.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
applied to u-boot-x86, thanks!
participants (2)
-
Bin Meng
-
Simon Glass