Am 08.12.2017 um 14:52 schrieb Anatolij Gustschin:

Hi,

On Wed, 6 Dec 2017 17:02:07 +0000 Siegmund, Jan jan.siegmund0@hm.edu wrote:

...

Hi all, does anybody have an idea for the following problem.

• FPGA is programmed using an overlay
• FPGA writes to SDRAM via the FPGA2SDRAM-bridge
• Linux hangs and the watchdog resets the board (the FPGA stays programmed)
• After the reset and boot the FPGA is reprogrammed using the same overlay
• Now, the FPGA can write to the SDRAM without a problem

Probably because configuration of the FPGA2SDRAM-bridge is different than other bridges. There is an important step needed, setting APPLYCFG bit in the STATICCFG register [1]. But this must be done when the DDR interface is idle (no DRAM transfer from ARM-core or DMA) which is not the case when Linux is running. Therefore, if you have designs that use fpga2sdram, you have to program the FPGA under U-Boot. U-Boot fpga command runs APPLYCFG setting code from OCRAM.

Thanks, this has helped me a lot. But there was still something missing. First, the FPGA needs to be programmed in U-Boot using the 'fpga' command. Then 'bridge enable' has to be called. This command does not only get the lwHPS2FPGA, HPS2FPGA and FPGA2HPS bridges out of reset, but also applies the SDRAM config, like you described. Now, my SDRAM-to-FPGA interface works fine.

Regards, Jan

Anatolij

[1] https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/Important...