[U-Boot] [PATCH 1/7] ARM: at91: Add the chip ID for SAMA5D2 LPDDR2 SiP
From: Nicolas Ferre nicolas.ferre@microchip.com
The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC identification.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com --- arch/arm/mach-at91/armv7/sama5d2_devices.c | 8 ++++++++ arch/arm/mach-at91/include/mach/sama5d2.h | 4 ++++ 2 files changed, 12 insertions(+)
diff --git a/arch/arm/mach-at91/armv7/sama5d2_devices.c b/arch/arm/mach-at91/armv7/sama5d2_devices.c index 59a0c44..9e9d026 100644 --- a/arch/arm/mach-at91/armv7/sama5d2_devices.c +++ b/arch/arm/mach-at91/armv7/sama5d2_devices.c @@ -57,8 +57,16 @@ char *get_cpu_name(void) return "SAMA5D27 512M bits DDR2 SDRAM"; case ARCH_EXID_SAMA5D27C_D1G: return "SAMA5D27 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD1G: + return "SAMA5D27 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D27C_LD2G: + return "SAMA5D27 2G bits LPDDR2 SDRAM"; case ARCH_EXID_SAMA5D28C_D1G: return "SAMA5D28 1G bits DDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD1G: + return "SAMA5D28 1G bits LPDDR2 SDRAM"; + case ARCH_EXID_SAMA5D28C_LD2G: + return "SAMA5D28 2G bits LPDDR2 SDRAM"; } }
diff --git a/arch/arm/mach-at91/include/mach/sama5d2.h b/arch/arm/mach-at91/include/mach/sama5d2.h index c7d9bb5..d1b2e01 100644 --- a/arch/arm/mach-at91/include/mach/sama5d2.h +++ b/arch/arm/mach-at91/include/mach/sama5d2.h @@ -220,7 +220,11 @@ #define ARCH_EXID_SAMA5D225C_D1M 0x00000053 #define ARCH_EXID_SAMA5D27C_D5M 0x00000032 #define ARCH_EXID_SAMA5D27C_D1G 0x00000033 +#define ARCH_EXID_SAMA5D27C_LD1G 0x00000061 +#define ARCH_EXID_SAMA5D27C_LD2G 0x00000062 #define ARCH_EXID_SAMA5D28C_D1G 0x00000013 +#define ARCH_EXID_SAMA5D28C_LD1G 0x00000071 +#define ARCH_EXID_SAMA5D28C_LD2G 0x00000072
/* Checked if defined in ethernet driver macb */ #define cpu_is_sama5d2 _cpu_is_sama5d2
From: Nicolas Ferre nicolas.ferre@microchip.com
Add support for the SAMA5D27-WLSOM1-EK. It's based on the Microchip WireLess SoM which contains the SAMa5D27 LPDDR2 2Gbits SiP.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com [eugen.hristev@microchip.com]: added u-boot specific dtsi and ported to 2019.10 Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/dts/Makefile | 3 + arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi | 38 ++++++++++ arch/arm/dts/at91-sama5d27_wlsom1_ek.dts | 84 ++++++++++++++++++++++ arch/arm/dts/sama5d27_wlsom1.dtsi | 56 +++++++++++++++ arch/arm/mach-at91/Kconfig | 15 ++++ board/atmel/sama5d27_wlsom1_ek/Kconfig | 15 ++++ board/atmel/sama5d27_wlsom1_ek/MAINTAINERS | 7 ++ board/atmel/sama5d27_wlsom1_ek/Makefile | 7 ++ .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 80 +++++++++++++++++++++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 72 +++++++++++++++++++ include/configs/sama5d27_wlsom1_ek.h | 34 +++++++++ 11 files changed, 411 insertions(+) create mode 100644 arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi create mode 100644 arch/arm/dts/at91-sama5d27_wlsom1_ek.dts create mode 100644 arch/arm/dts/sama5d27_wlsom1.dtsi create mode 040000 board/atmel/sama5d27_wlsom1_ek create mode 100644 board/atmel/sama5d27_wlsom1_ek/Kconfig create mode 100644 board/atmel/sama5d27_wlsom1_ek/MAINTAINERS create mode 100644 board/atmel/sama5d27_wlsom1_ek/Makefile create mode 100644 board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c create mode 100644 configs/sama5d27_wlsom1_ek_mmc_defconfig create mode 100644 include/configs/sama5d27_wlsom1_ek.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b437f75..6ab2366 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -717,6 +717,9 @@ dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \ dtb-$(CONFIG_TARGET_SAMA5D27_SOM1_EK) += \ at91-sama5d27_som1_ek.dtb
+dtb-$(CONFIG_TARGET_SAMA5D27_WLSOM1_EK) += \ + at91-sama5d27_wlsom1_ek.dtb + dtb-$(CONFIG_TARGET_SAMA5D2_ICP) += \ at91-sama5d2_icp.dtb
diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi new file mode 100644 index 0000000..48ab217 --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek-u-boot.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1_ek-u-boot.dts - Device Tree file for SAMA5D27 WLSOM1 EK + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Eugen Hristev eugen.hristev@microchip.com + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + }; +}; + +&sdmmc0 { + u-boot,dm-pre-reloc; +}; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&sfr { + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_cmd_dat_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_sdmmc0_ck_cd_default { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart0_default { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts new file mode 100644 index 0000000..21986ec --- /dev/null +++ b/arch/arm/dts/at91-sama5d27_wlsom1_ek.dts @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre nicolas.ferre@microcihp.com + */ +/dts-v1/; +#include "sama5d27_wlsom1.dtsi" + +/ { + model = "Microchip SAMA5D27 WLSOM1 EK"; + compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5"; + + chosen { + stdout-path = &uart0; + }; + + onewire_tm: onewire { + gpios = <&pioA PIN_PC9 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_onewire_tm_default>; + status = "okay"; + + w1_eeprom: w1_eeprom@0 { + compatible = "maxim,ds24b33"; + status = "okay"; + }; + }; + + ahb { + sdmmc0: sdio-host@a0000000 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>; + status = "okay"; + }; + + apb { + macb0: ethernet@f8008000 { + status = "okay"; + }; + + uart0: serial@f801c000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0_default>; + status = "okay"; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default { + pinmux = <PIN_PA1__SDMMC0_CMD>, + <PIN_PA2__SDMMC0_DAT0>, + <PIN_PA3__SDMMC0_DAT1>, + <PIN_PA4__SDMMC0_DAT2>, + <PIN_PA5__SDMMC0_DAT3>; + bias-disable; + }; + + pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default { + pinmux = <PIN_PA0__SDMMC0_CK>, + <PIN_PA11__SDMMC0_VDDSEL>, + <PIN_PA12__SDMMC0_WP>, + <PIN_PA13__SDMMC0_CD>; + bias-disable; + }; + + pinctrl_uart0_default: uart0_default { + pinmux = <PIN_PB26__URXD0>, + <PIN_PB27__UTXD0>; + bias-disable; + }; + + pinctrl_onewire_tm_default: onewire_tm_default { + pinmux = <PIN_PC9__GPIO>; + bias-pull-up; + }; + }; + }; + }; + }; +}; diff --git a/arch/arm/dts/sama5d27_wlsom1.dtsi b/arch/arm/dts/sama5d27_wlsom1.dtsi new file mode 100644 index 0000000..3d27570 --- /dev/null +++ b/arch/arm/dts/sama5d27_wlsom1.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * sama5d27_wlsom1.dtsi - Device Tree file for SAMA5D27 WLSOM1 + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre nicolas.ferre@microcihp.com + */ +#include "sama5d2.dtsi" +#include "sama5d2-pinfunc.h" +/ { + model = "Microchip SAMA5D27 WLSOM1"; + compatible = "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5"; + + memory { + reg = <0x20000000 0x10000000>; + }; + + ahb { + apb { + macb0: ethernet@f8008000 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>; + phy-mode = "rmii"; + + ethernet-phy@0 { + reg = <0x0>; + }; + }; + + pioA: gpio@fc038000 { + pinctrl { + pinctrl_macb0_phy_irq: macb0_phy_irq { + pinmux = <PIN_PB24__GPIO>; + bias-disable; + }; + + pinctrl_macb0_rmii: macb0_rmii { + pinmux = <PIN_PB14__GTXCK>, + <PIN_PB15__GTXEN>, + <PIN_PB16__GRXDV>, + <PIN_PB17__GRXER>, + <PIN_PB18__GRX0>, + <PIN_PB19__GRX1>, + <PIN_PB20__GTX0>, + <PIN_PB21__GTX1>, + <PIN_PB22__GMDC>, + <PIN_PB23__GMDIO>; + bias-disable; + }; + + }; + }; + }; + }; +}; diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index c3b21b7..24994d4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -180,6 +180,20 @@ config TARGET_SAMA5D27_SOM1_EK processor-based SAMA5D2 MPU with up to 1 Gbit DDR2-SDRAM in a single package.
+config TARGET_SAMA5D27_WLSOM1_EK + bool "SAMA5D27 WLSOM1 EK board" + select SAMA5D2 + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + help + The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package), + a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless + module providing bluetooth and wifi is also embedded. + The SAMA5D2 SiP integrates the ARM Cortex-A5 + processor-based SAMA5D2 MPU with 2 Gbit LPDDR2-SDRAM + in a single package. + config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" select CPU_V7A @@ -292,6 +306,7 @@ source "board/atmel/at91sam9x5ek/Kconfig" source "board/atmel/sama5d2_ptc_ek/Kconfig" source "board/atmel/sama5d2_xplained/Kconfig" source "board/atmel/sama5d27_som1_ek/Kconfig" +source "board/atmel/sama5d27_wlsom1_ek/Kconfig" source "board/atmel/sama5d2_icp/Kconfig" source "board/atmel/sama5d3_xplained/Kconfig" source "board/atmel/sama5d3xek/Kconfig" diff --git a/board/atmel/sama5d27_wlsom1_ek/Kconfig b/board/atmel/sama5d27_wlsom1_ek/Kconfig new file mode 100644 index 0000000..4b192b0 --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/Kconfig @@ -0,0 +1,15 @@ +if TARGET_SAMA5D27_WLSOM1_EK + +config SYS_BOARD + default "sama5d27_wlsom1_ek" + +config SYS_VENDOR + default "atmel" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "sama5d27_wlsom1_ek" + +endif diff --git a/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS new file mode 100644 index 0000000..59671ac --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/MAINTAINERS @@ -0,0 +1,7 @@ +SAMA5D27 WLSOM1 EK BOARD +M: Nicolas Ferre nicolas.ferre@microchip.com +M: Eugen Hristev eugen.hristev@microchip.com +S: Maintained +F: board/atmel/sama5d27_wlsom1_ek/ +F: include/configs/sama5d27_wlsom1_ek.h +F: configs/sama5d27_wlsom1_ek_mmc_defconfig diff --git a/board/atmel/sama5d27_wlsom1_ek/Makefile b/board/atmel/sama5d27_wlsom1_ek/Makefile new file mode 100644 index 0000000..cf827ae --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries +# +# Author: Nicolas Ferre nicolas.ferre@microcihp.com + +obj-y += sama5d27_wlsom1_ek.o diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c new file mode 100644 index 0000000..483ec82 --- /dev/null +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre nicolas.ferre@microcihp.com + */ + +#include <common.h> +#include <debug_uart.h> +#include <asm/io.h> +#include <asm/arch/at91_common.h> +#include <asm/arch/atmel_pio4.h> +#include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/atmel_sdhci.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sama5d2.h> + +extern void at91_pda_detect(void); + +DECLARE_GLOBAL_DATA_PTR; + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_DM_VIDEO + at91_video_show_board_info(); +#endif + at91_pda_detect(); + return 0; +} +#endif + +#ifdef CONFIG_DEBUG_UART_BOARD_INIT +static void board_uart0_hw_init(void) +{ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */ + atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */ + + at91_periph_clk_enable(ATMEL_ID_UART0); +} + +void board_debug_uart_init(void) +{ + board_uart0_hw_init(); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ +#ifdef CONFIG_DEBUG_UART + debug_uart_init(); +#endif + + return 0; +} +#endif + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + return 0; +} + +#ifdef CONFIG_MISC_INIT_R +int misc_init_r(void) +{ + return 0; +} +#endif + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig new file mode 100644 index 0000000..6b11fcb --- /dev/null +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -0,0 +1,72 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f00000 +CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf801c000 +CONFIG_DEBUG_UART_CLOCK=82000000 +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_IS_IN_FAT=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h new file mode 100644 index 0000000..cc41560 --- /dev/null +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration file for the SAMA5D27 WLSOM1 EK Board. + * + * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries + * + * Author: Nicolas Ferre nicolas.ferre@microcihp.com + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include "at91-sama5_common.h" + +#undef CONFIG_SYS_AT91_MAIN_CLOCK +#define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE 0x20000000 +#define CONFIG_SYS_SDRAM_SIZE 0x10000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ + +/* NAND flash */ +#undef CONFIG_CMD_NAND + +#ifdef CONFIG_SD_BOOT +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#endif + +#endif
From: Eugen Hristev eugen.hristev@microchip.com
This converts the at91 sfr to Kconfig
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/Kconfig | 9 ++++++++- arch/arm/mach-at91/Makefile | 5 +++-- arch/arm/mach-at91/atmel_sfr.c | 3 +++ 3 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index 24994d4..ad09731 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -46,6 +46,7 @@ config AT91SAM9X5 config SAMA5D2 bool select CPU_V7A + select ATMEL_SFR
config SAMA5D3 bool @@ -54,6 +55,7 @@ config SAMA5D3 config SAMA5D4 bool select CPU_V7A + select ATMEL_SFR
choice prompt "Atmel AT91 board select" @@ -173,6 +175,7 @@ config TARGET_SAMA5D27_SOM1_EK select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL + select ATMEL_SFR help The SAMA5D27 SOM1 embeds SAMA5D2 SiP(System in Package), a 64Mbit QSPI flash, KSZ8081 Phy and a Mac-address EEPROM @@ -196,7 +199,7 @@ config TARGET_SAMA5D27_WLSOM1_EK
config TARGET_SAMA5D2_ICP bool "SAMA5D2 Industrial Connectivity Platform (ICP)" - select CPU_V7A + select SAMA5D2 select SUPPORT_SPL select BOARD_EARLY_INIT_F select BOARD_LATE_INIT @@ -292,6 +295,10 @@ config TARGET_WB50N
endchoice
+config ATMEL_SFR + bool + default n + config SYS_SOC default "at91"
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile index 045ac88..cbd0ed6 100644 --- a/arch/arm/mach-at91/Makefile +++ b/arch/arm/mach-at91/Makefile @@ -7,10 +7,11 @@ obj-$(CONFIG_AT91SAM9G20) += sdram.o spl_at91.o obj-$(CONFIG_AT91SAM9M10G45) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9N12) += mpddrc.o spl_at91.o obj-$(CONFIG_AT91SAM9X5) += mpddrc.o spl_at91.o -obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D2) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o obj-$(CONFIG_SAMA5D3) += bootparams_atmel.o mpddrc.o spl_atmel.o -obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o atmel_sfr.o +obj-$(CONFIG_SAMA5D4) += bootparams_atmel.o mpddrc.o spl_atmel.o matrix.o obj-y += spl.o +obj-$(CONFIG_ATMEL_SFR) += atmel_sfr.o endif
obj-y += clock.o diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 2225115..07bd8ab 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/arch/sama5_sfr.h>
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4) void redirect_int_from_saic_to_aic(void) { struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; @@ -26,3 +27,5 @@ void configure_2nd_sram_as_l2_cache(void)
writel(1, &sfr->l2cc_hramc); } +#endif +
From: Eugen Hristev eugen.hristev@microchip.com
Add a function in SFR implementation that will open the DDR input buffers. This can be called at DRAM initialization time.
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/atmel_sfr.c | 11 +++++++++++ arch/arm/mach-at91/include/mach/at91_common.h | 3 +++ 2 files changed, 14 insertions(+)
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c index 07bd8ab..13cfba0 100644 --- a/arch/arm/mach-at91/atmel_sfr.c +++ b/arch/arm/mach-at91/atmel_sfr.c @@ -29,3 +29,14 @@ void configure_2nd_sram_as_l2_cache(void) } #endif
+void configure_ddrcfg_input_buffers(bool open) +{ + struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; + + if (open) + writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, + &sfr->ddrcfg); + else + writel(0, &sfr->ddrcfg); +} + diff --git a/arch/arm/mach-at91/include/mach/at91_common.h b/arch/arm/mach-at91/include/mach/at91_common.h index df7d0e7..e929b5e 100644 --- a/arch/arm/mach-at91/include/mach/at91_common.h +++ b/arch/arm/mach-at91/include/mach/at91_common.h @@ -35,6 +35,9 @@ void at91_disable_wdt(void); void matrix_init(void); void redirect_int_from_saic_to_aic(void); void configure_2nd_sram_as_l2_cache(void); +#ifdef CONFIG_ATMEL_SFR +void configure_ddrcfg_input_buffers(bool open); +#endif
int at91_set_ethaddr(int offset); int at91_video_show_board_info(void);
From: Eugen Hristev eugen.hristev@microchip.com
Replace code with new function configure_ddrcfg_input_buffers from SFR mach driver.
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/Kconfig | 1 + board/laird/wb50n/wb50n.c | 4 +--- 2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index ad09731..ce0b1b4 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -292,6 +292,7 @@ config TARGET_WB50N select BOARD_LATE_INIT select CPU_V7A select SUPPORT_SPL + select ATMEL_SFR
endchoice
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c index 89d3795..1598e5c 100644 --- a/board/laird/wb50n/wb50n.c +++ b/board/laird/wb50n/wb50n.c @@ -172,13 +172,11 @@ static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
void mem_init(void) { - struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR; struct atmel_mpddrc_config ddr2;
ddr2_conf(&ddr2);
- writel(ATMEL_SFR_DDRCFG_FDQIEN | ATMEL_SFR_DDRCFG_FDQSIEN, - &sfr->ddrcfg); + configure_ddrcfg_input_buffers(true);
/* enable MPDDR clock */ at91_periph_clk_enable(ATMEL_ID_MPDDRC);
From: Eugen Hristev eugen.hristev@microchip.com
Implement the lpddr2 initialization procedure for at91 mpddrc multi-port ddram controller.
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/include/mach/atmel_mpddrc.h | 23 ++++ arch/arm/mach-at91/mpddrc.c | 162 +++++++++++++++++++++++++ 2 files changed, 185 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h index 45a76a6..40ec87e 100644 --- a/arch/arm/mach-at91/include/mach/atmel_mpddrc.h +++ b/arch/arm/mach-at91/include/mach/atmel_mpddrc.h @@ -18,6 +18,9 @@ struct atmel_mpddrc_config { u32 tpr1; u32 tpr2; u32 md; + u32 lpddr23_lpr; + u32 cal_mr4; + u32 tim_cal; };
/* @@ -61,6 +64,10 @@ int ddr2_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value);
+int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value); + int ddr3_init(const unsigned int base, const unsigned int ram_address, const struct atmel_mpddrc_config *mpddr_value); @@ -74,6 +81,11 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MR_MODE_EXT_LMR_CMD 0x5 #define ATMEL_MPDDRC_MR_MODE_DEEP_CMD 0x6 #define ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD 0x7 +#define ATMEL_MPDDRC_MR_MRS(v) (((v) & 0xFF) << 0x8) + +/* Bit field in refresh timer register */ +#define ATMEL_MPDDRC_RTR_ADJ_REF (0x1 << 16) +#define ATMEL_MPDDRC_RTR_MR4VALUE(v) (((v) & 0x7) << 20)
/* Bit field in configuration register */ #define ATMEL_MPDDRC_CR_NC_MASK 0x3 @@ -157,6 +169,7 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_MD_DDR3_SDRAM 0x4 #define ATMEL_MPDDRC_MD_LPDDR3_SDRAM 0x5 #define ATMEL_MPDDRC_MD_DDR2_SDRAM 0x6 +#define ATMEL_MPDDRC_MD_LPDDR2_SDRAM 0x7 #define ATMEL_MPDDRC_MD_DBW_MASK (0x1 << 4) #define ATMEL_MPDDRC_MD_DBW_32_BITS (0x0 << 4) #define ATMEL_MPDDRC_MD_DBW_16_BITS (0x1 << 4) @@ -206,4 +219,14 @@ int ddr3_init(const unsigned int base, #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE 0x2 #define ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_THREE_CYCLE 0x3
+/* Bit field in LPDDR2 - LPDDR3 Low Power Register */ +#define ATMEL_MPDDRC_LPDDR23_LPR_DS(x) (((x) & 0xf) << 24) + +/* Bit field in CAL_MR4 Calibration and MR4 Register */ +#define ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(x) (((x) & 0xffff) << 0) +#define ATMEL_MPDDRC_CAL_MR4_MR4R(x) (((x) & 0xffff) << 16) + +/* Bit field in TIM_CAL Timing Calibration Register */ +#define ATMEL_MPDDRC_CALR_ZQCS(x) (((x) & 0xff) << 0) + #endif diff --git a/arch/arm/mach-at91/mpddrc.c b/arch/arm/mach-at91/mpddrc.c index 81ccd6a..3df0ea7 100644 --- a/arch/arm/mach-at91/mpddrc.c +++ b/arch/arm/mach-at91/mpddrc.c @@ -10,6 +10,7 @@ #include <common.h> #include <asm/io.h> #include <asm/arch/atmel_mpddrc.h> +#include <asm/arch/at91_common.h>
#define SAMA5D3_MPDDRC_VERSION 0x140
@@ -18,6 +19,7 @@ static inline void atmel_mpddr_op(const struct atmel_mpddr *mpddr, u32 ram_address) { writel(mode, &mpddr->mr); + dmb(); writel(0, ram_address); }
@@ -227,3 +229,163 @@ int ddr3_init(const unsigned int base,
return 0; } + +int lpddr2_init(const unsigned int base, + const unsigned int ram_address, + const struct atmel_mpddrc_config *mpddr_value) +{ + struct atmel_mpddr *mpddr = (struct atmel_mpddr *)base; + u32 reg; + + writel(mpddr_value->lpddr23_lpr, &mpddr->lpddr23_lpr); + + writel(mpddr_value->tim_cal, &mpddr->tim_cal); + + /* 1. Program the memory device type */ + writel(mpddr_value->md, &mpddr->md); + + /* + * 2. Program features of the LPDDR2-SDRAM device and timing parameters + */ + writel(mpddr_value->cr, &mpddr->cr); + + writel(mpddr_value->tpr0, &mpddr->tpr0); + writel(mpddr_value->tpr1, &mpddr->tpr1); + writel(mpddr_value->tpr2, &mpddr->tpr2); + + /* 3. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 3bis. Add memory barrier then Perform a write access to + * any low-power DDR2-SDRAM address to acknowledge the command. + */ + + dmb(); + writel(0, ram_address); + + /* 4. A pause of at least 100 ns must be observed before a single toggle */ + udelay(1); + + /* 5. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* 6. A pause of at least 200 us must be observed before a Reset Command */ + udelay(200); + + /* 7. A Reset command is issued to the low-power DDR2-SDRAM. */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(63), ram_address); + + /* + * 8. A pause of at least tINIT5 must be observed before issuing + * any commands + */ + udelay(1); + + /* 9. A Calibration command is issued to the low-power DDR2-SDRAM. */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_RESET; + writel(reg, &mpddr->cr); + + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(10), ram_address); + + /* + * 9bis: The ZQ Calibration command is now issued. + * Program the type of calibration in the MPDDRC_CR: set the + * ZQ field to the SHORT value. + */ + reg = readl(&mpddr->cr); + reg &= ~ATMEL_MPDDRC_CR_ZQ_RESET; + reg |= ATMEL_MPDDRC_CR_ZQ_SHORT; + writel(reg, &mpddr->cr); + + /* + * 10: A Mode Register Write command with 1 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(1), ram_address); + + /* + * 11: A Mode Register Write command with 2 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(2), ram_address); + + /* + * 12: A Mode Register Write command with 3 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(3), ram_address); + + /* + * 13: A Mode Register Write command with 16 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(16), ram_address); + + /* + * 14: In the DDR Configuration Register, open the input buffers. + */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(true); +#endif + + /* 15. A NOP command is issued to the LPDDR2-SDRAM */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NOP_CMD, ram_address); + + /* + * 16: A Mode Register Write command with 5 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(5), ram_address); + + /* + * 17: A Mode Register Write command with 6 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(6), ram_address); + + /* + * 18: A Mode Register Write command with 8 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(8), ram_address); + + /* + * 19: A Mode Register Write command with 0 to the MRS field + * is issued to the low-power DDR2-SDRAM. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_LPDDR2_CMD | + ATMEL_MPDDRC_MR_MRS(0), ram_address); + + /* + * 20: A Normal Mode command is provided. + */ + atmel_mpddr_op(mpddr, ATMEL_MPDDRC_MR_MODE_NORMAL_CMD, ram_address); + + /* 21: In the DDR Configuration Register, close the input buffers. */ +#ifdef CONFIG_ATMEL_SFR + configure_ddrcfg_input_buffers(false); +#endif + + /* + * 22: Write the refresh rate into the COUNT field in the MPDDRC + * Refresh Timer Register. + */ + writel(mpddr_value->rtr, &mpddr->rtr); + + /* 23. Configre CAL MR4 register */ + writel(mpddr_value->cal_mr4, &mpddr->cal_mr4); + + return 0; +}
From: Eugen Hristev eugen.hristev@microchip.com
Add support for SPL for this board: DRAM initialization, PMC initialization, MMC boot.
Signed-off-by: Eugen Hristev eugen.hristev@microchip.com --- arch/arm/mach-at91/Kconfig | 1 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 147 +++++++++++++++++++++ configs/sama5d27_wlsom1_ek_mmc_defconfig | 25 +++- include/configs/sama5d27_wlsom1_ek.h | 16 ++- 4 files changed, 185 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index ce0b1b4..1434328 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -189,6 +189,7 @@ config TARGET_SAMA5D27_WLSOM1_EK select BOARD_EARLY_INIT_F select BOARD_LATE_INIT select CPU_V7A + select SUPPORT_SPL help The SAMA5D27 WLSOM1 embeds SAMA5D2 SiP (System in Package), a 64Mbit QSPI flash with Mac-address, KSZ8081 Phy. A wireless diff --git a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c index 483ec82..3663ae4 100644 --- a/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c +++ b/board/atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c @@ -78,3 +78,150 @@ int dram_init(void) CONFIG_SYS_SDRAM_SIZE); return 0; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD + +#ifdef CONFIG_SD_BOOT +void spl_mmc_init(void) +{ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0); /* CMD */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0); /* DAT0 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0); /* DAT1 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0); /* DAT2 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0); /* DAT3 */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0); /* CK */ + atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CD */ + + at91_periph_clk_enable(ATMEL_ID_SDMMC0); +} +#endif + +void spl_board_init(void) +{ +#ifdef CONFIG_SD_BOOT + spl_mmc_init(); +#endif +} + +void spl_display_print(void) +{ +} + +static void ddrc_conf(struct atmel_mpddrc_config *ddrc) +{ + ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM); + + ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_ZQ_SHORT | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3); + + /* + * The AD220032D average time between REFRESH commands (Trefi): 3.9us + * 3.9us * 164MHz = 639.6 = 0x27F. + */ + ddrc->rtr = 0x27f; + /* Enable Adjust Refresh Rate */ + ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF; + + ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) | + (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) | + (11 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) | + (4 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) | + (5 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET)); + + ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) | + (0 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) | + (23 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) | + (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET)); + + ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) | + (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) | + (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) | + (2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) | + (10 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET)); + + ddrc->tim_cal = ATMEL_MPDDRC_CALR_ZQCS(15); + + /* + * According to the sama5d2 datasheet and the following values: + * T Sens = 0.75%/C, V Sens = 0.2%/mV, T driftrate = 1C/sec and V driftrate = 15 mV/s + * Warning: note that the values T driftrate and V driftrate are dependent on + * the application environment. + * ZQCS period is 1.5 / ((0.75 x 1) + (0.2 x 15)) = 0.4s + * If Trefi is 3.9us, we have: 400000 / 3.9 = 102564: we can maximize + * this timer to 0xFFFE. + */ + ddrc->cal_mr4 = ATMEL_MPDDRC_CAL_MR4_COUNT_CAL(0xFFFE); + + /* + * MR4 Read interval is dependent on the application environment. + * Here, we want to maximize this value as temperature is supposed + * to vary slowly in the application chosen. + * If Trefi is 3.9us, we have: + * (0xFFFE) 65534 x 3.9 = 0.25s between MR4 reads. + */ + ddrc->cal_mr4 |= ATMEL_MPDDRC_CAL_MR4_MR4R(0xFFFE); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC; + struct atmel_mpddrc_config ddrc_config; + u32 reg; + + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(AT91_PMC_DDR, &pmc->scer); + + ddrc_conf(&ddrc_config); + + reg = readl(&mpddrc->io_calibr); + reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV; + reg |= ATMEL_MPDDRC_IO_CALIBR_LPDDR2_RZQ_48; + reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO; + reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100); + writel(reg, &mpddrc->io_calibr); + + writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE, + &mpddrc->rd_data_path); + + lpddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config); +} + +void at91_pmc_init(void) +{ + u32 tmp; + + /* + * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz + * so we need to slow down and configure MCKR accordingly. + * This is why we have a special flavor of the switching function. + */ + tmp = AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_MAIN; + at91_mck_init_down(tmp); + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(40) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 6b11fcb..d7329a2 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -2,12 +2,20 @@ CONFIG_ARM=y CONFIG_ARCH_AT91=y CONFIG_SYS_TEXT_BASE=0x26f00000 CONFIG_TARGET_SAMA5D27_WLSOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_ENV_SIZE=0x4000 +CONFIG_SPL=y CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_DEBUG_UART_BASE=0xf801c000 CONFIG_DEBUG_UART_CLOCK=82000000 -CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y @@ -15,9 +23,13 @@ CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_TEXT_BASE=0x200000 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_SPL_DISPLAY_PRINT=y +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -31,9 +43,15 @@ CONFIG_CMD_PING=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_wlsom1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" CONFIG_ENV_IS_IN_FAT=y CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_CLK_AT91=y CONFIG_AT91_UTMI=y CONFIG_AT91_H32MX=y @@ -56,6 +74,7 @@ CONFIG_PHY_MICREL=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y CONFIG_PINCTRL_AT91PIO4=y CONFIG_DM_SERIAL=y CONFIG_DEBUG_UART_ATMEL=y @@ -64,9 +83,11 @@ CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_TIMER=y +CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y CONFIG_W1=y CONFIG_W1_GPIO=y CONFIG_W1_EEPROM=y CONFIG_W1_EEPROM_DS24XXX=y CONFIG_OF_LIBFDT_OVERLAY=y +# CONFIG_EFI_LOADER_HII is not set diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index cc41560..6bcbc06 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -19,16 +19,28 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE 0x10000000
+#ifdef CONFIG_SPL_BUILD +#define CONFIG_SYS_INIT_SP_ADDR 0x218000 +#else #define CONFIG_SYS_INIT_SP_ADDR \ (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) +#endif
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
-/* NAND flash */ -#undef CONFIG_CMD_NAND +/* SPL */ +#define CONFIG_SPL_TEXT_BASE 0x200000 +#define CONFIG_SPL_MAX_SIZE 0x10000 +#define CONFIG_SPL_BSS_START_ADDR 0x20000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 +#define CONFIG_SYS_SPL_MALLOC_START 0x20080000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 + +#define CONFIG_SYS_MONITOR_LEN (512 << 10)
#ifdef CONFIG_SD_BOOT #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 +#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" #endif
#endif
On 08.08.2019 10:48, Eugen.Hristev@microchip.com wrote:
From: Nicolas Ferre nicolas.ferre@microchip.com
The SAMA5D2 LPDDR2 SiP (System in Package) is added for SoC identification.
Signed-off-by: Nicolas Ferre nicolas.ferre@microchip.com
Applied this series to u-boot-atmel/next to be queued for next merge window.
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Eugen.Hristev＠microchip.com