[U-Boot] [PATCH] Rename CONFIG_SYS_MDDRC memory constants for all mpc512x boards
From: Martha Marx mmarx@silicontkx.com
Signed-off-by: Martha Marx Stan mmarx@silicontkx.com --- cpu/mpc512x/fixed_sdram.c | 104 ++++++++++++------------ include/configs/aria.h | 190 +++++++++++++++++++++--------------------- include/configs/mecp5123.h | 78 +++++++++--------- include/configs/mpc5121ads.h | 86 ++++++++++---------- 4 files changed, 229 insertions(+), 229 deletions(-)
diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index d906903..5be02f7 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -46,68 +46,68 @@ long int fixed_sdram(void) sync_law(&im->sysconf.ddrlaw.ar);
/* Enable DDR */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
/* Initialize DDR Priority Manager */ - out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1); - out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2); - out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG); - out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU); - out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML); - out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU); - out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML); - out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU); - out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML); - out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU); - out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML); - out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU); - out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML); - out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU); - out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL); - out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU); - out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL); - out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU); - out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL); - out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU); - out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL); - out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU); - out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL); + out_be32(&im->mddrc.prioman_config1, MDDRCGRP_PM_CFG1); + out_be32(&im->mddrc.prioman_config2, MDDRCGRP_PM_CFG2); + out_be32(&im->mddrc.hiprio_config, MDDRCGRP_HIPRIO_CFG); + out_be32(&im->mddrc.lut_table0_main_upper, MDDRCGRP_LUT0_MU); + out_be32(&im->mddrc.lut_table0_main_lower, MDDRCGRP_LUT0_ML); + out_be32(&im->mddrc.lut_table1_main_upper, MDDRCGRP_LUT1_MU); + out_be32(&im->mddrc.lut_table1_main_lower, MDDRCGRP_LUT1_ML); + out_be32(&im->mddrc.lut_table2_main_upper, MDDRCGRP_LUT2_MU); + out_be32(&im->mddrc.lut_table2_main_lower, MDDRCGRP_LUT2_ML); + out_be32(&im->mddrc.lut_table3_main_upper, MDDRCGRP_LUT3_MU); + out_be32(&im->mddrc.lut_table3_main_lower, MDDRCGRP_LUT3_ML); + out_be32(&im->mddrc.lut_table4_main_upper, MDDRCGRP_LUT4_MU); + out_be32(&im->mddrc.lut_table4_main_lower, MDDRCGRP_LUT4_ML); + out_be32(&im->mddrc.lut_table0_alternate_upper, MDDRCGRP_LUT0_AU); + out_be32(&im->mddrc.lut_table0_alternate_lower, MDDRCGRP_LUT0_AL); + out_be32(&im->mddrc.lut_table1_alternate_upper, MDDRCGRP_LUT1_AU); + out_be32(&im->mddrc.lut_table1_alternate_lower, MDDRCGRP_LUT1_AL); + out_be32(&im->mddrc.lut_table2_alternate_upper, MDDRCGRP_LUT2_AU); + out_be32(&im->mddrc.lut_table2_alternate_lower, MDDRCGRP_LUT2_AL); + out_be32(&im->mddrc.lut_table3_alternate_upper, MDDRCGRP_LUT3_AU); + out_be32(&im->mddrc.lut_table3_alternate_lower, MDDRCGRP_LUT3_AL); + out_be32(&im->mddrc.lut_table4_alternate_upper, MDDRCGRP_LUT4_AU); + out_be32(&im->mddrc.lut_table4_alternate_lower, MDDRCGRP_LUT4_AL);
/* Initialize MDDRC */ - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG); - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0); - out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1); - out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0); + out_be32(&im->mddrc.ddr_time_config1, MDDRC_TIME_CFG1); + out_be32(&im->mddrc.ddr_time_config2, MDDRC_TIME_CFG2);
/* Initialize DDR */ for (i = 0; i < 10; i++) - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, DDR_NOP);
- out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); - out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_NOP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_EM2); + out_be32(&im->mddrc.ddr_command, DDR_EM3); + out_be32(&im->mddrc.ddr_command, DDR_EN_DLL); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_RFSH); + out_be32(&im->mddrc.ddr_command, DDR_MICRON_INIT_DEV_OP); + out_be32(&im->mddrc.ddr_command, DDR_OCD_DEFAULT); + out_be32(&im->mddrc.ddr_command, DDR_PCHG_ALL); + out_be32(&im->mddrc.ddr_command, DDR_NOP);
/* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN); - out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN); + out_be32(&im->mddrc.ddr_time_config0, MDDRC_TIME_CFG0_RUN); + out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_RUN);
return msize; } diff --git a/include/configs/aria.h b/include/configs/aria.h index 4211113..cafef9e 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -123,108 +123,108 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ - (1 << 30) | /* CKE */ \ - (1 << 29) | /* CLK_ON */ \ - (1 << 28) | /* CMD_MODE */ \ - (4 << 25) | /* DRAM_ROW_SELECT */ \ - (3 << 21) | /* DRAM_BANK_SELECT */ \ - (0 << 18) | /* SELF_REF_EN */ \ - (0 << 17) | /* 16BIT_MODE */ \ - (2 << 13) | /* RDLY */ \ - (0 << 12) | /* HALF_DQS_DLY */ \ - (1 << 11) | /* QUART_DQS_DLY */ \ - (2 << 8) | /* WDLY */ \ - (0 << 7) | /* EARLY_ODT */ \ - (1 << 6) | /* ON_DIE_TERMINATE */ \ - (0 << 5) | /* FIFO_OV_CLEAR */ \ - (0 << 4) | /* FIFO_UV_CLEAR */ \ - (0 << 1) | /* FIFO_OV_EN */ \ - (0 << 0) /* FIFO_UV_EN */ \ - ) - -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28)) -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 - -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (0 << 10) | /* A10->DQS# */ \ - (0 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (0 << 2) | /* Rtt0 */ \ - (1 << 1) | /* ODS */ \ - (0 << 0) /* DLL */ \ - ) -#define CONFIG_SYS_MICRON_EMR2 0x01020000 -#define CONFIG_SYS_MICRON_EMR3 0x01030000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ - (0 << 22) | /* DRAM_CS */ \ - (0 << 21) | /* DRAM_RAS */ \ - (0 << 20) | /* DRAM_CAS */ \ - (0 << 19) | /* DRAM_WEB */ \ - (1 << 16) | /* DRAM_BS[2:0] */ \ - (0 << 15) | /* */ \ - (0 << 12) | /* A12->out */ \ - (0 << 11) | /* A11->RDQS */ \ - (1 << 10) | /* A10->DQS# */ \ - (7 << 7) | /* OCD program */ \ - (0 << 6) | /* Rtt1 */ \ - (0 << 3) | /* posted CAS# */ \ - (1 << 2) | /* Rtt0 */ \ - (0 << 1) | /* ODS (Output Drive Strength) */ \ - (0 << 0) /* DLL */ \ - ) +#define MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ + (1 << 30) | /* CKE */ \ + (1 << 29) | /* CLK_ON */ \ + (1 << 28) | /* CMD_MODE */ \ + (4 << 25) | /* DRAM_ROW_SELECT */ \ + (3 << 21) | /* DRAM_BANK_SELECT */ \ + (0 << 18) | /* SELF_REF_EN */ \ + (0 << 17) | /* 16BIT_MODE */ \ + (2 << 13) | /* RDLY */ \ + (0 << 12) | /* HALF_DQS_DLY */ \ + (1 << 11) | /* QUART_DQS_DLY */ \ + (2 << 8) | /* WDLY */ \ + (0 << 7) | /* EARLY_ODT */ \ + (1 << 6) | /* ON_DIE_TERMINATE */ \ + (0 << 5) | /* FIFO_OV_CLEAR */ \ + (0 << 4) | /* FIFO_UV_CLEAR */ \ + (0 << 1) | /* FIFO_OV_EN */ \ + (0 << 0) /* FIFO_UV_EN */ \ + ) + +#define MDDRC_SYS_CFG_RUN (MDDRC_SYS_CFG & ~(1 << 28)) +#define MDDRC_TIME_CFG1 0x55D81189 +#define MDDRC_TIME_CFG2 0x34790863 + +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x030C3D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (0 << 10) | /* A10->DQS# */ \ + (0 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (0 << 2) | /* Rtt0 */ \ + (1 << 1) | /* ODS */ \ + (0 << 0) /* DLL */ \ + ) +#define DDR_MICRON_EMR2 0x01020000 +#define DDR_MICRON_EMR3 0x01030000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ + (0 << 22) | /* DRAM_CS */ \ + (0 << 21) | /* DRAM_RAS */ \ + (0 << 20) | /* DRAM_CAS */ \ + (0 << 19) | /* DRAM_WEB */ \ + (1 << 16) | /* DRAM_BS[2:0] */ \ + (0 << 15) | /* */ \ + (0 << 12) | /* A12->out */ \ + (0 << 11) | /* A11->RDQS */ \ + (1 << 10) | /* A10->DQS# */ \ + (7 << 7) | /* OCD program */ \ + (0 << 6) | /* Rtt1 */ \ + (0 << 3) | /* posted CAS# */ \ + (1 << 2) | /* Rtt0 */ \ + (0 << 1) | /* ODS (Output Drive Strength) */ \ + (0 << 0) /* DLL */ \ + )
/* * Backward compatible definitions, * so we do not have to change cpu/mpc512x/fixed_sdram.c */ -#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2) -#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3) -#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR) -#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) +#define DDR_EM2 (DDR_MICRON_EMR2) +#define DDR_EM3 (DDR_MICRON_EMR3) +#define DDR_EN_DLL (DDR_MICRON_EMR) +#define DDR_OCD_DEFAULT (DDR_MICRON_EMR_OCD)
/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111
/* * NOR FLASH on the Local Bus diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 1ecae00..cb8198b 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -111,47 +111,47 @@ * [09:05] DRAM tRP: * [04:00] DRAM tRPA */ -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define MDDRC_SYS_CFG 0xFA804A00 +#define MDDRC_SYS_CFG_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1 0x68EC1168 +#define MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111
/* * NOR FLASH on the Local Bus diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 76f174d..5df51e3 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -131,53 +131,53 @@ * [04:00] DRAM tRPA */ #ifdef CONFIG_MPC5121ADS_REV2 -#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864 +#define MDDRC_SYS_CFG 0xF8604A00 +#define MDDRC_SYS_CFG_RUN 0xE8604A00 +#define MDDRC_TIME_CFG1 0x54EC1168 +#define MDDRC_TIME_CFG2 0x35210864 #else -#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00 -#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00 -#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168 -#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864 +#define MDDRC_SYS_CFG 0xFA804A00 +#define MDDRC_SYS_CFG_RUN 0xEA804A00 +#define MDDRC_TIME_CFG1 0x68EC1168 +#define MDDRC_TIME_CFG2 0x34310864 #endif -#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000 -#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E -#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E - -#define CONFIG_SYS_MICRON_NOP 0x01380000 -#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400 -#define CONFIG_SYS_MICRON_EM2 0x01020000 -#define CONFIG_SYS_MICRON_EM3 0x01030000 -#define CONFIG_SYS_MICRON_EN_DLL 0x01010000 -#define CONFIG_SYS_MICRON_RFSH 0x01080000 -#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 -#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780 +#define MDDRC_SYS_CFG_EN 0xF0000000 +#define MDDRC_TIME_CFG0 0x00003D2E +#define MDDRC_TIME_CFG0_RUN 0x06183D2E + +#define DDR_NOP 0x01380000 +#define DDR_PCHG_ALL 0x01100400 +#define DDR_EM2 0x01020000 +#define DDR_EM3 0x01030000 +#define DDR_EN_DLL 0x01010000 +#define DDR_RFSH 0x01080000 +#define DDR_MICRON_INIT_DEV_OP 0x01000432 +#define DDR_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */ -#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 -#define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 -#define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 -#define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC -#define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA -#define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 -#define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 -#define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 -#define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 -#define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa -#define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 -#define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 -#define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 +#define MDDRCGRP_PM_CFG1 0x00077777 +#define MDDRCGRP_PM_CFG2 0x00000000 +#define MDDRCGRP_HIPRIO_CFG 0x00000001 +#define MDDRCGRP_LUT0_MU 0xFFEEDDCC +#define MDDRCGRP_LUT0_ML 0xBBAAAAAA +#define MDDRCGRP_LUT1_MU 0x66666666 +#define MDDRCGRP_LUT1_ML 0x55555555 +#define MDDRCGRP_LUT2_MU 0x44444444 +#define MDDRCGRP_LUT2_ML 0x44444444 +#define MDDRCGRP_LUT3_MU 0x55555555 +#define MDDRCGRP_LUT3_ML 0x55555558 +#define MDDRCGRP_LUT4_MU 0x11111111 +#define MDDRCGRP_LUT4_ML 0x11111122 +#define MDDRCGRP_LUT0_AU 0xaaaaaaaa +#define MDDRCGRP_LUT0_AL 0xaaaaaaaa +#define MDDRCGRP_LUT1_AU 0x66666666 +#define MDDRCGRP_LUT1_AL 0x66666666 +#define MDDRCGRP_LUT2_AU 0x11111111 +#define MDDRCGRP_LUT2_AL 0x11111111 +#define MDDRCGRP_LUT3_AU 0x11111111 +#define MDDRCGRP_LUT3_AL 0x11111111 +#define MDDRCGRP_LUT4_AU 0x11111111 +#define MDDRCGRP_LUT4_AL 0x11111111
/* * NOR FLASH on the Local Bus
Dear Martha M Stan,
In message 12525956202930-git-send-email-mmarx@silicontkx.com you wrote:
From: Martha Marx mmarx@silicontkx.com
May I ask what the purpose of such a rename is? I mean, which problem are you tryin to fix, and in which way is the new code supposed to be better than the old one?
Actually I think the new names are much worse. What's the purpose of omitting the "CONFIG_SYS_" part?
...
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, DDR_NOP);
For example this rename - using "DDR_NOP" for a configurable parameter in a global file, and having to #define this in the board config files makes no sense to me.
We have standard rule about naming of configration options. This here is clearly a case where "CONFIG_SYS_" applies.
All the other renames fall in the same category.
Unless you have a very good reason for this rename I tend to NAK this.
Best regards,
Wolfgang Denk
Hello Wolfgang,
I know this was a while ago ... but when I first posted the Elpida patch you asked me to FIX the my memory constant changes. At that time you said the following
While performing such a global rename, please let's get rid of the CONFIG_SYS_ names. These are NOT options that can be changed by the user in the board config file, so they should not look like such.
This is when I tried to change some constants because they had "MICRON" in there. I decided to take out MICRON since they are being shared by both ELPIDA and MICRON.
How bout I just make a whole new set of constants for ELPIDA ??? and Leave the "MICRON" ones the way they stand ?
Best Regards,
-Martha Stan
-----Original Message----- From: Wolfgang Denk [mailto:wd@denx.de] Sent: Thursday, September 10, 2009 2:49 PM To: Martha M Stan Cc: u-boot@lists.denx.de Subject: Re: [U-Boot] [PATCH] Rename CONFIG_SYS_MDDRC memory constants for all mpc512x boards
Dear Martha M Stan,
In message 12525956202930-git-send-email-mmarx@silicontkx.com you wrote:
From: Martha Marx mmarx@silicontkx.com
May I ask what the purpose of such a rename is? I mean, which problem are you tryin to fix, and in which way is the new code supposed to be better than the old one?
Actually I think the new names are much worse. What's the purpose of omitting the "CONFIG_SYS_" part?
...
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, DDR_NOP);For example this rename - using "DDR_NOP" for a configurable parameter in a global file, and having to #define this in the board config files makes no sense to me.
We have standard rule about naming of configration options. This here is clearly a case where "CONFIG_SYS_" applies.
All the other renames fall in the same category.
Unless you have a very good reason for this rename I tend to NAK this.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Drawing on my fine command of language, I said nothing.
Dear "Martha J Marx",
In message 200909101515289.SM07320@cw4mb41 you wrote:
I know this was a while ago ... but when I first posted the Elpida patch you asked me to FIX the my memory constant changes. At that time you said the following
While performing such a global rename, please let's get rid of the CONFIG_SYS_ names. These are NOT options that can be changed by the user in the board config file, so they should not look like such.
This is when I tried to change some constants because they had "MICRON" in there. I decided to take out MICRON since they are being shared by both ELPIDA and MICRON.
I remember. I was wrong. By then, the MPC5121ADS was the only MPC512x board, and the changes were to board/ads5121/ads5121.c (and include/configs/ads5121.h). We (well, especially I) assumed that this was strictly board-specific code.
But since then, a number of other MPC512x boards have been added, and in this process it turned out that this is actually common code, which can be used unchanged by all boards. So it was moved from "private" to "public". Also it became clear that the values to insert here are no magic constants, but board-specific configuration options, and for these the name should be CONFIG_SYS_*.
How bout I just make a whole new set of constants for ELPIDA ??? and Leave the "MICRON" ones the way they stand ?
I think all such renaming doesn't bring us forward.
Looking at the code it seems we have just a list of constants that need to get written all to the same mddrc.ddr_command register. To make this configurable, we should probably not try to add more such stuff, but separate code and data to simplify the design.
I think we should turn the existing code:
/* Initialize DDR */ for (i = 0; i < 10; i++) out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
into something like this:
u32 micron_table[] = { CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP,
CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_EM2, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_EM2, CONFIG_SYS_MICRON_EM3, CONFIG_SYS_MICRON_EN_DLL, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_OCD_DEFAULT, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_NOP, }; ...
long int fixed_sdram(u32 ram_table[], int table_size) { int i; ... for (i=0; i<table_size; ++i) out_be32(&im->mddrc.ddr_sys_config, ram_table[i]) ... }
The board specific code would then be changed from
fixed_sdram()
into for example
fixed_sdram(micron_table,sizeof(micron_table)/sizeof(u32))
In board/freescale/mpc5121ads/mpc5121ads.c, you could provide an additional set of data (elpida_table[]), and then pass either of these to fixed_sdram().
What do you think?
Best regards,
Wolfgang Denk
Very Elegant Wolfgang - I like it ... I'll take a stab and I'll try not to tarnish it!
-M
Looking at the code it seems we have just a list of constants that need to get written all to the same mddrc.ddr_command register. To make this configurable, we should probably not try to add more such stuff, but separate code and data to simplify the design.
I think we should turn the existing code:
/* Initialize DDR */ for (i = 0; i < 10; i++) out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL); out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
into something like this:
u32 micron_table[] = { CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_NOP,
CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_EM2, CONFIG_SYS_MICRON_NOP, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_EM2, CONFIG_SYS_MICRON_EM3, CONFIG_SYS_MICRON_EN_DLL, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_RFSH, CONFIG_SYS_MICRON_INIT_DEV_OP, CONFIG_SYS_MICRON_OCD_DEFAULT, CONFIG_SYS_MICRON_PCHG_ALL, CONFIG_SYS_MICRON_NOP, }; ...
long int fixed_sdram(u32 ram_table[], int table_size) { int i; ... for (i=0; i<table_size; ++i) out_be32(&im->mddrc.ddr_sys_config, ram_table[i]) ... }
The board specific code would then be changed from
fixed_sdram()
into for example
fixed_sdram(micron_table,sizeof(micron_table)/sizeof(u32))
In board/freescale/mpc5121ads/mpc5121ads.c, you could provide an additional set of data (elpida_table[]), and then pass either of these to fixed_sdram().
What do you think?
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de The optimum committee has no members. - Norman Augustine
participants (3)
-
Martha J Marx -
Martha M Stan
-
Wolfgang Denk