[PATCH 1/2] ARM: dts: am3517-evm: Sync DTS with Linux 5.17-rc5

Sync the am3517-evm device tree files with those from Linux 5.17-rc5 with some additional fixes for pinmuxing Ethernet and moving the pinmux references to the respective peripherals.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi index d5a4ce97d1..1a70630322 100644 --- a/arch/arm/dts/am3517-evm-u-boot.dtsi +++ b/arch/arm/dts/am3517-evm-u-boot.dtsi @@ -37,7 +37,18 @@ /delete-property/ u-boot,dm-spl; };
-/delete-node/ &uart1; -/delete-node/ &uart2; -/delete-node/ &mmc2; -/delete-node/ &mmc3; +&mmc2 { + /delete-property/ u-boot,dm-spl; +}; + +&mmc3 { + /delete-property/ u-boot,dm-spl; +}; + +&uart1 { + /delete-property/ u-boot,dm-spl; +}; + +&uart2 { + /delete-property/ u-boot,dm-spl; +}; diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi index 54aa2522aa..7d8f32bf70 100644 --- a/arch/arm/dts/am3517-evm-ui.dtsi +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/ */
#include <dt-bindings/input/input.h> diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index 935c471c97..a01f9cf047 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. + * Copyright (C) 2011 Texas Instruments Incorporated - https://www.ti.com/ */ /dts-v1/;
@@ -127,10 +124,11 @@ };
lcd0: display@0 { - compatible = "panel-dpi"; + /* This isn't the exact LCD, but the timings meet spec */ + /* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4 */ + compatible = "newhaven,nhd-4.3-480272ef-atxl"; label = "15"; - status = "okay"; - pinctrl-names = "default"; + backlight = <&bl>; enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /* gpio176, lcd INI */ vcc-supply = <&vdd_io_reg>;
@@ -139,22 +137,6 @@ remote-endpoint = <&dpi_out>; }; }; - - panel-timing { - clock-frequency = <9000000>; - hactive = <480>; - vactive = <272>; - hfront-porch = <3>; - hback-porch = <2>; - hsync-len = <42>; - vback-porch = <3>; - vfront-porch = <4>; - vsync-len = <11>; - hsync-active = <0>; - vsync-active = <0>; - de-active = <1>; - pixelclk-active = <1>; - }; };
bl: backlight { @@ -174,10 +156,13 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer11>; #pwm-cells = <3>; + ti,clock-source = <0x01>; };
/* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_rst_pins>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ #phy-cells = <0>; @@ -185,7 +170,9 @@ };
&davinci_emac { - status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <ðernet_pins>; + status = "okay"; };
&davinci_mdio { @@ -240,6 +227,8 @@ };
&usbhshost { + pinctrl-names = "default"; + pinctrl-0 = <&hsusb1_pins>; port1-mode = "ehci-phy"; };
@@ -248,8 +237,21 @@ };
&omap3_pmx_core { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_rst_pins>; + + ethernet_pins: pinmux_ethernet_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0) /* rmii_mdio_data */ + OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /* rmii_mdio_clk */ + OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd0 */ + OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_rxd1 */ + OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_crs_dv */ + OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_rxer */ + OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd0 */ + OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* rmii_txd1 */ + OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN |MUX_MODE0) /* rmii_txen */ + OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii_50mhz_clk */ + >; + };
leds_pins: pinmux_leds_pins { pinctrl-single,pins = < @@ -317,8 +319,6 @@ };
&omap3_pmx_core2 { - pinctrl-names = "default"; - pinctrl-0 = <&hsusb1_pins>;
hsusb1_pins: pinmux_hsusb1_pins { pinctrl-single,pins = < diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi index b1c988eed8..8b669e2eaf 100644 --- a/arch/arm/dts/am3517-som.dtsi +++ b/arch/arm/dts/am3517-som.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (C) 2016 Derald D. Woods woods.technical@gmail.com * * Based on am3517-evm.dts - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. */
/ {

With updated device trees now supporting pinmuxing for USB, ethernet, MMC, and other peripherals necessary to start MLO and U-Boot, the hard-coded pinmux options can be removed since they are now handed by DM and only muxed when the respective peripheral needs it.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index db2134bb9d..aec2b410c8 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -122,64 +122,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\ - /* - ETH_nRESET*/\ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \ - /* DSS */\ - MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \ - /* CAMERA */\ - MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4)) /*GPIO_98*/\ - /* - CAM_RESET*/\ - MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\ - MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ /* MMC */\ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ @@ -187,144 +130,15 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ - /* WriteProtect */\ - MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) /*CardDetect*/\ - MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ - MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ - \ - MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \ - /* McBSP */\ - MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \ - \ - MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_152*/\ - /* - LCD_INI*/\ - MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4)) /*GPIO_153*/\ - /* - LCD_ENVDD */\ - MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4)) /*GPIO_154*/\ - /* - LCD_QVGA/nVGA */\ - MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_155*/\ - /* - LCD_RESB */\ /* UART */\ - MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ - \ - MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ - MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ - \ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \ - /* I2C */\ - MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \ - /* McSPI */\ - MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ - MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4)) /*GPIO_175*/\ - MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4)) /*GPIO_176*/\ - /* - LAN_INTR*/\ - MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \ - \ - MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \ - MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \ - /* CCDC */\ - MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \ - MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \ - /* RMII */\ - MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ - MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ - MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ - MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ - MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ - MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \ - /* HECC */\ - MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \ - MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \ - /* HSUSB */\ - MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ - MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ - MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \ - /* HDQ */\ - MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ /* Control and debug */\ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \ - /*SYS_nRESWARM */\ - MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \ - /* - GPIO30 */\ - MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2*/\ - /* - PEN_IRQ */\ - MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\ - MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4*/\ - MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5*/\ - MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6*/\ - MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7*/\ - MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4)) /*GPIO_8*/\ - /* - VIO_1V8*/\ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ \ @@ -339,18 +153,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ /* ETK (ES2 onwards) */\ - MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3)) /*HSUSB1_STP*/\ - MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3)) /*HSUSB1_CLK*/\ - MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA0*/\ - MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA1*/\ - MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA2*/\ - MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA7*/\ - MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA4*/\ - MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA5*/\ - MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA6*/\ - MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DATA3*/\ - MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_DIR*/\ - MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3)) /*HSUSB1_NXT*/\ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \

On Sat, Feb 26, 2022 at 3:18 PM Adam Ford aford173@gmail.com wrote:
With updated device trees now supporting pinmuxing for USB, ethernet, MMC, and other peripherals necessary to start MLO and U-Boot, the hard-coded pinmux options can be removed since they are now handed by DM and only muxed when the respective peripheral needs it.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index db2134bb9d..aec2b410c8 100644 --- a/board/logicpd/am3517evm/am3517evm.h +++ b/board/logicpd/am3517evm/am3517evm.h @@ -122,64 +122,7 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))
/*GPIO_64*/\
/* - ETH_nRESET*/\ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) \
/* DSS */\
MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0)) \
/* CAMERA */\
MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_XCLKA), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CAM_FLD), (IDIS | PTD | DIS | M4))
/*GPIO_98*/\
/* - CAM_RESET*/\
MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D10), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_D11), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_XCLKB), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4))
/*GPIO_167*/\
MUX_VAL(CP(CAM_STROBE), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DX1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CSI2_DY1), (IEN | PTD | DIS | M0)) \ /* MMC */\ MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \
@@ -187,144 +130,15 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \
/* WriteProtect */\
MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4))
/*CardDetect*/\
MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \
MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \
\
MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MMC2_CMD), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MMC2_DAT3), (IEN | PTD | DIS | M0)) \
/* McBSP */\
MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP2_FSX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP2_DX), (IDIS | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP3_DX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_DR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M0)) \
\
MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4))
/*GPIO_152*/\
/* - LCD_INI*/\
MUX_VAL(CP(MCBSP4_DR), (IDIS | PTD | DIS | M4))
/*GPIO_153*/\
/* - LCD_ENVDD */\
MUX_VAL(CP(MCBSP4_DX), (IDIS | PTD | DIS | M4))
/*GPIO_154*/\
/* -
LCD_QVGA/nVGA */\
MUX_VAL(CP(MCBSP4_FSX), (IDIS | PTD | DIS | M4))
/*GPIO_155*/\
/* - LCD_RESB */\ /* UART */\
MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \
\
MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \
MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \
\ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) \
/* I2C */\
MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0)) \
/* McSPI */\
MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \
MUX_VAL(CP(MCSPI1_CS1), (IEN | PTD | EN | M4))
/*GPIO_175*/\
MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | DIS | M4))
/*GPIO_176*/\
/* - LAN_INTR*/\
MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M0)) \
\
MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M4)) \
MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M4)) \
/* CCDC */\
MUX_VAL(CP(CCDC_PCLK), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_HD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_VD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(CCDC_WEN), (IEN | PTD | DIS | M1)) \
MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(CCDC_DATA7), (IEN | PTD | DIS | M0)) \
/* RMII */\
MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \
MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
MUX_VAL(CP(RMII_RXD0) , (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \
MUX_VAL(CP(RMII_RXER), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \
MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \
MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \
MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTD | EN | M0)) \
/* HECC */\
MUX_VAL(CP(HECC1_TXD), (IEN | PTU | EN | M0)) \
MUX_VAL(CP(HECC1_RXD), (IEN | PTU | EN | M0)) \
/* HSUSB */\
MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \
MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \
MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0)) \
/* HDQ */\
MUX_VAL(CP(HDQ_SIO), (IEN | PTU | EN | M0)) \ /* Control and debug */\ MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(SYS_NIRQ), (IEN | PTU | EN | M0)) \
/*SYS_nRESWARM */\
MUX_VAL(CP(SYS_NRESWARM), (IDIS | PTU | EN | M4)) \
/* - GPIO30 */\
MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4))
/*GPIO_2*/\
/* - PEN_IRQ */\
MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3
*/\
MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4))
/*GPIO_4*/\
MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4))
/*GPIO_5*/\
MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4))
/*GPIO_6*/\
MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))
/*GPIO_7*/\
MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M4))
/*GPIO_8*/\
/* - VIO_1V8*/\ MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | EN | M0)) \ MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | EN | M0)) \ \
@@ -339,18 +153,6 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) \ /* ETK (ES2 onwards) */\
MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | EN | M3))
/*HSUSB1_STP*/\
MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTU | DIS | M3))
/*HSUSB1_CLK*/\
MUX_VAL(CP(ETK_D0_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA0*/\
MUX_VAL(CP(ETK_D1_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA1*/\
MUX_VAL(CP(ETK_D2_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA2*/\
MUX_VAL(CP(ETK_D3_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA7*/\
MUX_VAL(CP(ETK_D4_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA4*/\
MUX_VAL(CP(ETK_D5_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA5*/\
MUX_VAL(CP(ETK_D6_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA6*/\
MUX_VAL(CP(ETK_D7_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DATA3*/\
MUX_VAL(CP(ETK_D8_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_DIR*/\
MUX_VAL(CP(ETK_D9_ES2), (IEN | PTU | DIS | M3))
/*HSUSB1_NXT*/\ MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M0)) \ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M0)) \ -- 2.34.1
Works on AM3517 Zoom eXperimenter.
Tested-by: Derald D. Woods woods.technical@gmail.com

On Sat, Feb 26, 2022 at 03:17:24PM -0600, Adam Ford wrote:
With updated device trees now supporting pinmuxing for USB, ethernet, MMC, and other peripherals necessary to start MLO and U-Boot, the hard-coded pinmux options can be removed since they are now handed by DM and only muxed when the respective peripheral needs it.
Signed-off-by: Adam Ford aford173@gmail.com Tested-by: Derald D. Woods woods.technical@gmail.com
diff --git a/board/logicpd/am3517evm/am3517evm.h b/board/logicpd/am3517evm/am3517evm.h index db2134bb9d..aec2b410c8 100644
Applied to u-boot/next, thanks!

On Sat, Feb 26, 2022 at 3:17 PM Adam Ford aford173@gmail.com wrote:
Sync the am3517-evm device tree files with those from Linux 5.17-rc5 with some additional fixes for pinmuxing Ethernet and moving the pinmux references to the respective peripherals.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi index d5a4ce97d1..1a70630322 100644 --- a/arch/arm/dts/am3517-evm-u-boot.dtsi +++ b/arch/arm/dts/am3517-evm-u-boot.dtsi @@ -37,7 +37,18 @@ /delete-property/ u-boot,dm-spl; };
-/delete-node/ &uart1; -/delete-node/ &uart2; -/delete-node/ &mmc2; -/delete-node/ &mmc3; +&mmc2 {
/delete-property/ u-boot,dm-spl;
+};
+&mmc3 {
/delete-property/ u-boot,dm-spl;
+};
+&uart1 {
/delete-property/ u-boot,dm-spl;
+};
+&uart2 {
/delete-property/ u-boot,dm-spl;
+}; diff --git a/arch/arm/dts/am3517-evm-ui.dtsi b/arch/arm/dts/am3517-evm-ui.dtsi index 54aa2522aa..7d8f32bf70 100644 --- a/arch/arm/dts/am3517-evm-ui.dtsi +++ b/arch/arm/dts/am3517-evm-ui.dtsi @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /*
- Copyright (C) 2018 Logic PD, Inc - http://www.logicpd.com/
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
*/
- Copyright (C) 2018 Logic PD, Inc - https://www.logicpd.com/
#include <dt-bindings/input/input.h> diff --git a/arch/arm/dts/am3517-evm.dts b/arch/arm/dts/am3517-evm.dts index 935c471c97..a01f9cf047 100644 --- a/arch/arm/dts/am3517-evm.dts +++ b/arch/arm/dts/am3517-evm.dts @@ -1,9 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0-only /*
- Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
- Copyright (C) 2011 Texas Instruments Incorporated -
https://www.ti.com/ */ /dts-v1/;
@@ -127,10 +124,11 @@ };
lcd0: display@0 {
compatible = "panel-dpi";
/* This isn't the exact LCD, but the timings meet spec */
/* To make it work, set CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=4
*/
compatible = "newhaven,nhd-4.3-480272ef-atxl"; label = "15";
status = "okay";
pinctrl-names = "default";
backlight = <&bl>; enable-gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; /*
gpio176, lcd INI */ vcc-supply = <&vdd_io_reg>;
@@ -139,22 +137,6 @@ remote-endpoint = <&dpi_out>; }; };
panel-timing {
clock-frequency = <9000000>;
hactive = <480>;
vactive = <272>;
hfront-porch = <3>;
hback-porch = <2>;
hsync-len = <42>;
vback-porch = <3>;
vfront-porch = <4>;
vsync-len = <11>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <1>;
}; }; bl: backlight {
@@ -174,10 +156,13 @@ pinctrl-0 = <&pwm_pins>; ti,timers = <&timer11>; #pwm-cells = <3>;
ti,clock-source = <0x01>; }; /* HS USB Host PHY on PORT 1 */ hsusb1_phy: hsusb1_phy {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_rst_pins>; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>; /* gpio_57 */ #phy-cells = <0>;
@@ -185,7 +170,9 @@ };
&davinci_emac {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <ðernet_pins>;
status = "okay";
};
&davinci_mdio { @@ -240,6 +227,8 @@ };
&usbhshost {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_pins>; port1-mode = "ehci-phy";
};
@@ -248,8 +237,21 @@ };
&omap3_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_rst_pins>;
ethernet_pins: pinmux_ethernet_pins {
pinctrl-single,pins = <
OMAP3_CORE1_IOPAD(0x21fe, PIN_INPUT | MUX_MODE0)
/* rmii_mdio_data */
OMAP3_CORE1_IOPAD(0x2200, MUX_MODE0) /*
rmii_mdio_clk */
OMAP3_CORE1_IOPAD(0x2202, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* rmii_rxd0 */
OMAP3_CORE1_IOPAD(0x2204, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* rmii_rxd1 */
OMAP3_CORE1_IOPAD(0x2206, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* rmii_crs_dv */
OMAP3_CORE1_IOPAD(0x2208, PIN_OUTPUT_PULLDOWN |
MUX_MODE0) /* rmii_rxer */
OMAP3_CORE1_IOPAD(0x220a, PIN_OUTPUT_PULLDOWN |
MUX_MODE0) /* rmii_txd0 */
OMAP3_CORE1_IOPAD(0x220c, PIN_OUTPUT_PULLDOWN |
MUX_MODE0) /* rmii_txd1 */
OMAP3_CORE1_IOPAD(0x220e, PIN_OUTPUT_PULLDOWN
|MUX_MODE0) /* rmii_txen */
OMAP3_CORE1_IOPAD(0x2210, PIN_INPUT_PULLDOWN |
MUX_MODE0) /* rmii_50mhz_clk */
>;
}; leds_pins: pinmux_leds_pins { pinctrl-single,pins = <
@@ -317,8 +319,6 @@ };
&omap3_pmx_core2 {
pinctrl-names = "default";
pinctrl-0 = <&hsusb1_pins>; hsusb1_pins: pinmux_hsusb1_pins { pinctrl-single,pins = <
diff --git a/arch/arm/dts/am3517-som.dtsi b/arch/arm/dts/am3517-som.dtsi index b1c988eed8..8b669e2eaf 100644 --- a/arch/arm/dts/am3517-som.dtsi +++ b/arch/arm/dts/am3517-som.dtsi @@ -1,11 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0-only /*
- Copyright (C) 2016 Derald D. Woods woods.technical@gmail.com
- Based on am3517-evm.dts
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
*/
- published by the Free Software Foundation.
/ {
2.34.1
Works on AM3517 Zoom eXperimenter.
Tested-by: Derald D. Woods woods.technical@gmail.com

On Sat, Feb 26, 2022 at 03:17:23PM -0600, Adam Ford wrote:
Sync the am3517-evm device tree files with those from Linux 5.17-rc5 with some additional fixes for pinmuxing Ethernet and moving the pinmux references to the respective peripherals.
Signed-off-by: Adam Ford aford173@gmail.com Tested-by: Derald D. Woods woods.technical@gmail.com
diff --git a/arch/arm/dts/am3517-evm-u-boot.dtsi b/arch/arm/dts/am3517-evm-u-boot.dtsi index d5a4ce97d1..1a70630322 100644
Applied to u-boot/next, thanks!
participants (3)
-
Adam Ford
-
Derald Woods
-
Tom Rini