Re: [U-Boot] [U-Boot, 2/3] mpc85xx: Add deep sleep framework support
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-----Original Message----- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote:
Use an I/O accessor.
In_be64?? No such function.
Why do you need in_be64() rather than two in_be32()s?
Avoid ECC error. Although, according to my test, in_be32() works too.
Why would you get an ECC error?
-Scott
On 2014/2/18 星期二 3:18, Scott Wood wrote:
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-----Original Message----- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote:
Use an I/O accessor.
In_be64?? No such function.
Why do you need in_be64() rather than two in_be32()s?
Avoid ECC error. Although, according to my test, in_be32() works too.
Why would you get an ECC error?
-Scott
DDR operation is always in 64bits. if writing a 32bits to memory, you need to read a 32bits first, and combine it to form a 64bits. when the new 64bits is written to memory, ECC occurs. I was required to do so by hardware team.
Regards, Yuantian
On Mon, 2014-02-24 at 14:44 +0800, Tang Yuantian-B29983 wrote:
On 2014/2/18 星期二 3:18, Scott Wood wrote:
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-----Original Message----- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote:
Use an I/O accessor.
In_be64?? No such function.
Why do you need in_be64() rather than two in_be32()s?
Avoid ECC error. Although, according to my test, in_be32() works too.
Why would you get an ECC error?
-Scott
DDR operation is always in 64bits. if writing a 32bits to memory, you need to read a 32bits first, and combine it to form a 64bits. when the new 64bits is written to memory, ECC occurs. I was required to do so by hardware team.
U-Boot on PPC is a 32-bit binary (even on 64-bit hardware), so the compiler is already turning that into two 32-bit writes.
-Scott
On 2014/2/25 星期二 3:11, Scott Wood wrote:
On Mon, 2014-02-24 at 14:44 +0800, Tang Yuantian-B29983 wrote:
On 2014/2/18 星期二 3:18, Scott Wood wrote:
On Sun, 2014-02-16 at 21:35 -0600, Tang Yuantian-B29983 wrote:
-----Original Message----- From: Wood Scott-B07421 To: Tang Yuantian-B29983 Cc: Sun York-R58495; Li Yang-Leo-R58472; u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Jin Zhengxiong-R64188 Subject: Re: [U-Boot,2/3] mpc85xx: Add deep sleep framework support
On Thu, 2014-02-13 at 02:12 -0600, Tang Yuantian-B29983 wrote:
> Use an I/O accessor. In_be64?? No such function.
Why do you need in_be64() rather than two in_be32()s?
Avoid ECC error. Although, according to my test, in_be32() works too.
Why would you get an ECC error?
-Scott
DDR operation is always in 64bits. if writing a 32bits to memory, you need to read a 32bits first, and combine it to form a 64bits. when the new 64bits is written to memory, ECC occurs. I was required to do so by hardware team.
U-Boot on PPC is a 32-bit binary (even on 64-bit hardware), so the compiler is already turning that into two 32-bit writes.
-Scott
I quote: (from Welker James A.-RA8497 ) 3) You only need 8-byte (or multiple of 8-byte) transactions when initializing the memory. Typically, we would simply use 2, 64-byte writes to DRAM. This is because a sub-doubleword transactions will result in a read-modify-write, which would encounter an ECC error (and then mask the write data). After the first 128-bytes of memory have been re-initialized, you can issue any transactions to those locations again.
I think the transactions between CPU and DDRC are always in 64 bits physically because DDRC has 64 bits data bus. But I am sure about this. If you are sure about this, I will change as your suggestion.
Regards, Yuantian
participants (2)
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Scott Wood -
Tang Yuantian-B29983