[PATCH v3 10/25] pinctrl: rockchip: Add pinctrl route types
Some pins in rockchip are routed via Top GRF and PMU GRF instead of direct regmap.
Add support to handle all these routing paths so that the SoC pinctrl drivers will use them accordingly.
Signed-off-by: Jianqun Xu jay.xu@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
drivers/pinctrl/rockchip/pinctrl-px30.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk3128.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk322x.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk3288.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk3308.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk3328.c | 11 +--- drivers/pinctrl/rockchip/pinctrl-rk3399.c | 11 +--- .../pinctrl/rockchip/pinctrl-rockchip-core.c | 45 ++++++++++++-- drivers/pinctrl/rockchip/pinctrl-rockchip.h | 58 ++++++++++++++++++- 9 files changed, 102 insertions(+), 78 deletions(-)
diff --git a/drivers/pinctrl/rockchip/pinctrl-px30.c b/drivers/pinctrl/rockchip/pinctrl-px30.c index 9de29c0b8b..2c35491b24 100644 --- a/drivers/pinctrl/rockchip/pinctrl-px30.c +++ b/drivers/pinctrl/rockchip/pinctrl-px30.c @@ -80,7 +80,7 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -90,15 +90,6 @@ static int px30_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3128.c b/drivers/pinctrl/rockchip/pinctrl-rk3128.c index e6dc1af86e..355c45eb7f 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3128.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3128.c @@ -106,7 +106,7 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -119,15 +119,6 @@ static int rk3128_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk322x.c b/drivers/pinctrl/rockchip/pinctrl-rk322x.c index 7c58f40d93..351406da2d 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk322x.c @@ -150,7 +150,7 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -160,15 +160,6 @@ static int rk3228_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3288.c b/drivers/pinctrl/rockchip/pinctrl-rk3288.c index 5894f47f53..a976b7aeeb 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3288.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3288.c @@ -37,7 +37,7 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -47,15 +47,6 @@ static int rk3288_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - /* bank0 is special, there are no higher 16 bit writing bits. */ if (bank->bank_num == 0) { regmap_read(regmap, reg, &data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3308.c b/drivers/pinctrl/rockchip/pinctrl-rk3308.c index 83186f40f6..f9ac6347ea 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3308.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3308.c @@ -258,7 +258,7 @@ static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -271,15 +271,6 @@ static int rk3308_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3328.c b/drivers/pinctrl/rockchip/pinctrl-rk3328.c index 1c3c5986a5..65a7500767 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3328.c @@ -130,7 +130,7 @@ static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -143,15 +143,6 @@ static int rk3328_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) if (bank->recalced_mask & BIT(pin)) rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rk3399.c b/drivers/pinctrl/rockchip/pinctrl-rk3399.c index caa92200c6..ae785573ba 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rk3399.c +++ b/drivers/pinctrl/rockchip/pinctrl-rk3399.c @@ -59,7 +59,7 @@ static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) struct regmap *regmap; int reg, ret, mask, mux_type; u8 bit; - u32 data, route_reg, route_val; + u32 data;
regmap = (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) ? priv->regmap_pmu : priv->regmap_base; @@ -69,15 +69,6 @@ static int rk3399_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) reg = bank->iomux[iomux_num].offset; reg += rockchip_get_mux_data(mux_type, pin, &bit, &mask);
- if (bank->route_mask & BIT(pin)) { - if (rockchip_get_mux_route(bank, pin, mux, &route_reg, - &route_val)) { - ret = regmap_write(regmap, route_reg, route_val); - if (ret) - return ret; - } - } - data = (mask << (bit + 16)); data |= (mux & mask) << bit; ret = regmap_write(regmap, reg, data); diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c index 630513ba3a..d9d61fdb72 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip-core.c @@ -62,8 +62,9 @@ void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, *bit = data->bit; }
-bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value) +static enum rockchip_pin_route_type +rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, + int mux, u32 *reg, u32 *value) { struct rockchip_pinctrl_priv *priv = bank->priv; struct rockchip_pin_ctrl *ctrl = priv->ctrl; @@ -78,12 +79,12 @@ bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, }
if (i >= ctrl->niomux_routes) - return false; + return ROUTE_TYPE_INVALID;
*reg = data->route_offset; *value = data->route_val;
- return true; + return data->route_type; }
int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask) @@ -214,8 +215,40 @@ static int rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) return -ENOTSUPP;
ret = ctrl->set_mux(bank, pin, mux); + if (ret) + return ret;
- return ret; + if (bank->route_mask & BIT(pin)) { + struct regmap *regmap; + u32 route_reg = 0, route_val = 0; + + ret = rockchip_get_mux_route(bank, pin, mux, + &route_reg, &route_val); + switch (ret) { + case ROUTE_TYPE_DEFAULT: + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; + + regmap_write(regmap, route_reg, route_val); + break; + case ROUTE_TYPE_TOPGRF: + regmap_write(priv->regmap_base, route_reg, route_val); + break; + case ROUTE_TYPE_PMUGRF: + regmap_write(priv->regmap_pmu, route_reg, route_val); + break; + case ROUTE_TYPE_INVALID: + fallthrough; + default: + break; + } + } + + return 0; }
static int rockchip_perpin_drv_list[DRV_TYPE_MAX][8] = { @@ -545,7 +578,7 @@ static struct rockchip_pin_ctrl *rockchip_pinctrl_get_soc_data(struct udevice *d inc = (iom->type & (IOMUX_WIDTH_4BIT | IOMUX_WIDTH_3BIT | IOMUX_8WIDTH_2BIT)) ? 8 : 4; - if (iom->type & IOMUX_SOURCE_PMU) + if ((iom->type & IOMUX_SOURCE_PMU) || (iom->type & IOMUX_L_SOURCE_PMU)) pmu_offs += inc; else grf_offs += inc; diff --git a/drivers/pinctrl/rockchip/pinctrl-rockchip.h b/drivers/pinctrl/rockchip/pinctrl-rockchip.h index d969c20082..8dfaba5c74 100644 --- a/drivers/pinctrl/rockchip/pinctrl-rockchip.h +++ b/drivers/pinctrl/rockchip/pinctrl-rockchip.h @@ -9,6 +9,9 @@ #include <linux/bitops.h> #include <linux/types.h>
+#define RK_GENMASK_VAL(h, l, v) \ + (GENMASK(((h) + 16), ((l) + 16)) | (((v) << (l)) & GENMASK((h), (l)))) + /** * Encode variants of iomux registers into a type variable */ @@ -18,6 +21,7 @@ #define IOMUX_UNROUTED BIT(3) #define IOMUX_WIDTH_3BIT BIT(4) #define IOMUX_8WIDTH_2BIT BIT(5) +#define IOMUX_L_SOURCE_PMU BIT(6)
/** * Defined some common pins constants @@ -62,6 +66,22 @@ enum rockchip_pin_pull_type { PULL_TYPE_MAX };
+/** + * Rockchip pinctrl route type + * + * DEFAULT : Same regmap as pin iomux + * TOPGRF : Mux route setting in topgrf + * PMUGRF : Mux route setting in pmugrf + * INVALID : Nnot need to set mux route + */ +enum rockchip_pin_route_type { + ROUTE_TYPE_DEFAULT = 0, + ROUTE_TYPE_TOPGRF = 1, + ROUTE_TYPE_PMUGRF = 2, + + ROUTE_TYPE_INVALID = -1, +}; + /** * @drv_type: drive strength variant using rockchip_perpin_drv_type * @offset: if initialized to -1 it will be autocalculated, by specifying @@ -126,6 +146,21 @@ struct rockchip_pin_bank { }, \ }
+#define PIN_BANK_IOMUX_FLAGS_OFFSET(id, pins, label, iom0, iom1, iom2, \ + iom3, offset0, offset1, offset2, \ + offset3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = offset0 }, \ + { .type = iom1, .offset = offset1 }, \ + { .type = iom2, .offset = offset2 }, \ + { .type = iom3, .offset = offset3 }, \ + }, \ + } + #define PIN_BANK_DRV_FLAGS(id, pins, label, type0, type1, type2, type3) \ { \ .bank_num = id, \ @@ -220,6 +255,25 @@ struct rockchip_pin_bank { .pull_type[3] = pull3, \ }
+#define PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, FLAG) \ + { \ + .bank_num = ID, \ + .pin = PIN, \ + .func = FUNC, \ + .route_offset = REG, \ + .route_val = VAL, \ + .route_type = FLAG, \ + } + +#define MR_DEFAULT(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_DEFAULT) + +#define MR_TOPGRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_TOPGRF) + +#define MR_PMUGRF(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROUTE_TYPE_PMUGRF) + /** * struct rockchip_mux_recalced_data: recalculate a pin iomux data. * @num: bank number. @@ -241,6 +295,7 @@ struct rockchip_mux_recalced_data { * @bank_num: bank number. * @pin: index at register or used to calc index. * @func: the min pin. + * @route_type: the register type. * @route_offset: the max pin. * @route_val: the register offset. */ @@ -248,6 +303,7 @@ struct rockchip_mux_route_data { u8 bank_num; u8 pin; u8 func; + enum rockchip_pin_route_type route_type : 8; u32 route_offset; u32 route_val; }; @@ -289,8 +345,6 @@ extern const struct pinctrl_ops rockchip_pinctrl_ops; int rockchip_pinctrl_probe(struct udevice *dev); void rockchip_get_recalced_mux(struct rockchip_pin_bank *bank, int pin, int *reg, u8 *bit, int *mask); -bool rockchip_get_mux_route(struct rockchip_pin_bank *bank, int pin, - int mux, u32 *reg, u32 *value); int rockchip_get_mux_data(int mux_type, int pin, u8 *bit, int *mask); int rockchip_translate_drive_value(int type, int strength); int rockchip_translate_pull_value(int type, int pull);
Add pinctrl driver for Rockchip RV1126.
Signed-off-by: Jianqun Xu jay.xu@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl-rv1126.c | 416 ++++++++++++++++++++++ 2 files changed, 417 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl-rv1126.c
diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 7d03f8101d..9884355473 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_ROCKCHIP_RK3328) += pinctrl-rk3328.o obj-$(CONFIG_ROCKCHIP_RK3368) += pinctrl-rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += pinctrl-rk3399.o obj-$(CONFIG_ROCKCHIP_RV1108) += pinctrl-rv1108.o +obj-$(CONFIG_ROCKCHIP_RV1126) += pinctrl-rv1126.o diff --git a/drivers/pinctrl/rockchip/pinctrl-rv1126.c b/drivers/pinctrl/rockchip/pinctrl-rv1126.c new file mode 100644 index 0000000000..eefb8b1776 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl-rv1126.c @@ -0,0 +1,416 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2020 Rockchip Electronics Co., Ltd + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <dm/pinctrl.h> +#include <regmap.h> +#include <syscon.h> +#include <linux/bitops.h> +#include <dt-bindings/pinctrl/rockchip.h> + +#include "pinctrl-rockchip.h" + +static struct rockchip_mux_recalced_data rv1126_mux_recalced_data[] = { + { + .num = 0, + .pin = 20, + .reg = 0x10000, + .bit = 0, + .mask = 0xf + }, + { + .num = 0, + .pin = 21, + .reg = 0x10000, + .bit = 4, + .mask = 0xf + }, + { + .num = 0, + .pin = 22, + .reg = 0x10000, + .bit = 8, + .mask = 0xf + }, + { + .num = 0, + .pin = 23, + .reg = 0x10000, + .bit = 12, + .mask = 0xf + }, +}; + +static struct rockchip_mux_route_data rv1126_mux_route_data[] = { + MR_TOPGRF(RK_GPIO3, RK_PD2, 1, 0x10260, RK_GENMASK_VAL(0, 0, 0)), /* I2S0_MCLK_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB0, 3, 0x10260, RK_GENMASK_VAL(0, 0, 1)), /* I2S0_MCLK_M1 */ + + MR_TOPGRF(RK_GPIO0, RK_PD4, 4, 0x10260, RK_GENMASK_VAL(3, 2, 0)), /* I2S1_MCLK_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 2, 0x10260, RK_GENMASK_VAL(3, 2, 1)), /* I2S1_MCLK_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PC7, 6, 0x10260, RK_GENMASK_VAL(3, 2, 2)), /* I2S1_MCLK_M2 */ + + MR_TOPGRF(RK_GPIO1, RK_PD0, 1, 0x10260, RK_GENMASK_VAL(4, 4, 0)), /* I2S2_MCLK_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB3, 2, 0x10260, RK_GENMASK_VAL(4, 4, 1)), /* I2S2_MCLK_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PD4, 2, 0x10260, RK_GENMASK_VAL(12, 12, 0)), /* PDM_CLK0_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PC0, 3, 0x10260, RK_GENMASK_VAL(12, 12, 1)), /* PDM_CLK0_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PC6, 1, 0x10264, RK_GENMASK_VAL(0, 0, 0)), /* CIF_CLKOUT_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD1, 3, 0x10264, RK_GENMASK_VAL(0, 0, 1)), /* CIF_CLKOUT_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 5, 0x10264, RK_GENMASK_VAL(5, 4, 0)), /* I2C3_SCL_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD4, 7, 0x10264, RK_GENMASK_VAL(5, 4, 1)), /* I2C3_SCL_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD6, 3, 0x10264, RK_GENMASK_VAL(5, 4, 2)), /* I2C3_SCL_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA0, 7, 0x10264, RK_GENMASK_VAL(6, 6, 0)), /* I2C4_SCL_M0 */ + MR_TOPGRF(RK_GPIO4, RK_PA0, 4, 0x10264, RK_GENMASK_VAL(6, 6, 1)), /* I2C4_SCL_M1 */ + + MR_TOPGRF(RK_GPIO2, RK_PA5, 7, 0x10264, RK_GENMASK_VAL(9, 8, 0)), /* I2C5_SCL_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PB0, 5, 0x10264, RK_GENMASK_VAL(9, 8, 1)), /* I2C5_SCL_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD0, 4, 0x10264, RK_GENMASK_VAL(9, 8, 2)), /* I2C5_SCL_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PC0, 5, 0x10264, RK_GENMASK_VAL(11, 10, 0)), /* SPI1_CLK_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PC6, 3, 0x10264, RK_GENMASK_VAL(11, 10, 1)), /* SPI1_CLK_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PD5, 6, 0x10264, RK_GENMASK_VAL(11, 10, 2)), /* SPI1_CLK_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PC0, 2, 0x10264, RK_GENMASK_VAL(12, 12, 0)), /* RGMII_CLK_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB7, 2, 0x10264, RK_GENMASK_VAL(12, 12, 1)), /* RGMII_CLK_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA1, 3, 0x10264, RK_GENMASK_VAL(13, 13, 0)), /* CAN_TXD_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA7, 5, 0x10264, RK_GENMASK_VAL(13, 13, 1)), /* CAN_TXD_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 6, 0x10268, RK_GENMASK_VAL(0, 0, 0)), /* PWM8_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD7, 5, 0x10268, RK_GENMASK_VAL(0, 0, 1)), /* PWM8_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA5, 6, 0x10268, RK_GENMASK_VAL(2, 2, 0)), /* PWM9_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD6, 5, 0x10268, RK_GENMASK_VAL(2, 2, 1)), /* PWM9_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA6, 6, 0x10268, RK_GENMASK_VAL(4, 4, 0)), /* PWM10_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PD5, 5, 0x10268, RK_GENMASK_VAL(4, 4, 1)), /* PWM10_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PA7, 6, 0x10268, RK_GENMASK_VAL(6, 6, 0)), /* PWM11_IR_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA1, 5, 0x10268, RK_GENMASK_VAL(6, 6, 1)), /* PWM11_IR_M1 */ + + MR_TOPGRF(RK_GPIO1, RK_PA5, 3, 0x10268, RK_GENMASK_VAL(8, 8, 0)), /* UART2_TX_M0 */ + MR_TOPGRF(RK_GPIO3, RK_PA2, 1, 0x10268, RK_GENMASK_VAL(8, 8, 1)), /* UART2_TX_M1 */ + + MR_TOPGRF(RK_GPIO3, RK_PC6, 3, 0x10268, RK_GENMASK_VAL(11, 10, 0)), /* UART3_TX_M0 */ + MR_TOPGRF(RK_GPIO1, RK_PA7, 2, 0x10268, RK_GENMASK_VAL(11, 10, 1)), /* UART3_TX_M1 */ + MR_TOPGRF(RK_GPIO3, RK_PA0, 4, 0x10268, RK_GENMASK_VAL(11, 10, 2)), /* UART3_TX_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA4, 4, 0x10268, RK_GENMASK_VAL(13, 12, 0)), /* UART4_TX_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(13, 12, 1)), /* UART4_TX_M1 */ + MR_TOPGRF(RK_GPIO1, RK_PD5, 3, 0x10268, RK_GENMASK_VAL(13, 12, 2)), /* UART4_TX_M2 */ + + MR_TOPGRF(RK_GPIO3, RK_PA6, 4, 0x10268, RK_GENMASK_VAL(15, 14, 0)), /* UART5_TX_M0 */ + MR_TOPGRF(RK_GPIO2, RK_PB0, 4, 0x10268, RK_GENMASK_VAL(15, 14, 1)), /* UART5_TX_M1 */ + MR_TOPGRF(RK_GPIO2, RK_PA0, 3, 0x10268, RK_GENMASK_VAL(15, 14, 2)), /* UART5_TX_M2 */ + + MR_PMUGRF(RK_GPIO0, RK_PB6, 3, 0x0114, RK_GENMASK_VAL(0, 0, 0)), /* PWM0_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB3, 5, 0x0114, RK_GENMASK_VAL(0, 0, 1)), /* PWM0_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB7, 3, 0x0114, RK_GENMASK_VAL(2, 2, 0)), /* PWM1_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB2, 5, 0x0114, RK_GENMASK_VAL(2, 2, 1)), /* PWM1_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC0, 3, 0x0114, RK_GENMASK_VAL(4, 4, 0)), /* PWM2_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB1, 5, 0x0114, RK_GENMASK_VAL(4, 4, 1)), /* PWM2_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC1, 3, 0x0114, RK_GENMASK_VAL(6, 6, 0)), /* PWM3_IR_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PB0, 5, 0x0114, RK_GENMASK_VAL(6, 6, 1)), /* PWM3_IR_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC2, 3, 0x0114, RK_GENMASK_VAL(8, 8, 0)), /* PWM4_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA7, 5, 0x0114, RK_GENMASK_VAL(8, 8, 1)), /* PWM4_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PC3, 3, 0x0114, RK_GENMASK_VAL(10, 10, 0)), /* PWM5_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA6, 5, 0x0114, RK_GENMASK_VAL(10, 10, 1)), /* PWM5_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB2, 3, 0x0114, RK_GENMASK_VAL(12, 12, 0)), /* PWM6_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PD4, 5, 0x0114, RK_GENMASK_VAL(12, 12, 1)), /* PWM6_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB1, 3, 0x0114, RK_GENMASK_VAL(14, 14, 0)), /* PWM7_IR_M0 */ + MR_PMUGRF(RK_GPIO3, RK_PA0, 5, 0x0114, RK_GENMASK_VAL(14, 14, 1)), /* PWM7_IR_M1 */ + + MR_PMUGRF(RK_GPIO0, RK_PB0, 1, 0x0118, RK_GENMASK_VAL(1, 0, 0)), /* SPI0_CLK_M0 */ + MR_PMUGRF(RK_GPIO2, RK_PA1, 1, 0x0118, RK_GENMASK_VAL(1, 0, 1)), /* SPI0_CLK_M1 */ + MR_PMUGRF(RK_GPIO2, RK_PB2, 6, 0x0118, RK_GENMASK_VAL(1, 0, 2)), /* SPI0_CLK_M2 */ + + MR_PMUGRF(RK_GPIO0, RK_PB6, 2, 0x0118, RK_GENMASK_VAL(2, 2, 0)), /* UART1_TX_M0 */ + MR_PMUGRF(RK_GPIO1, RK_PD0, 5, 0x0118, RK_GENMASK_VAL(2, 2, 1)), /* UART1_TX_M1 */ + MR_PMUGRF(RK_GPIO0, RK_PC3, 1, 0x0118, RK_GENMASK_VAL(4, 4, 1)), /* I2C2 */ +}; + +static int rv1126_set_mux(struct rockchip_pin_bank *bank, int pin, int mux) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int iomux_num = (pin / 8); + struct regmap *regmap; + int reg, ret, mask, mux_type; + u8 bit; + u32 data; + + debug("setting mux of GPIO%d-%d to %d\n", bank->bank_num, pin, mux); + + if (bank->iomux[iomux_num].type & IOMUX_SOURCE_PMU) + regmap = priv->regmap_pmu; + else if (bank->iomux[iomux_num].type & IOMUX_L_SOURCE_PMU) + regmap = (pin % 8 < 4) ? priv->regmap_pmu : priv->regmap_base; + else + regmap = priv->regmap_base; + + /* get basic quadrupel of mux registers and the correct reg inside */ + mux_type = bank->iomux[iomux_num].type; + reg = bank->iomux[iomux_num].offset; + if (mux_type & IOMUX_WIDTH_4BIT) { + if ((pin % 8) >= 4) + reg += 0x4; + bit = (pin % 4) * 4; + mask = 0xf; + } else { + bit = (pin % 8) * 2; + mask = 0x3; + } + + if (bank->recalced_mask & BIT(pin)) + rockchip_get_recalced_mux(bank, pin, ®, &bit, &mask); + + data = (mask << (bit + 16)); + data |= (mux & mask) << bit; + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126_PULL_PMU_OFFSET 0x40 +#define RV1126_PULL_GRF_GPIO1A0_OFFSET 0x10108 +#define RV1126_PULL_PINS_PER_REG 8 +#define RV1126_PULL_BITS_PER_PIN 2 +#define RV1126_PULL_BANK_STRIDE 16 +#define RV1126_GPIO_C4_D7(p) (p >= 20 && p <= 31) /* GPIO0_C4 ~ GPIO0_D7 */ + +static void rv1126_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_PULL_PINS_PER_REG + 1) * 4); + *bit = pin_num % RV1126_PULL_PINS_PER_REG; + *bit *= RV1126_PULL_BITS_PER_PIN; + return; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_PULL_PMU_OFFSET; + } else { + *reg = RV1126_PULL_GRF_GPIO1A0_OFFSET; + *regmap = priv->regmap_base; + *reg += (bank->bank_num - 1) * RV1126_PULL_BANK_STRIDE; + } + + *reg += ((pin_num / RV1126_PULL_PINS_PER_REG) * 4); + *bit = (pin_num % RV1126_PULL_PINS_PER_REG); + *bit *= RV1126_PULL_BITS_PER_PIN; +} + +static int rv1126_set_pull(struct rockchip_pin_bank *bank, + int pin_num, int pull) +{ + struct regmap *regmap; + int reg, ret; + u8 bit, type; + u32 data; + + if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) + return -EOPNOTSUPP; + + rv1126_calc_pull_reg_and_bit(bank, pin_num, ®map, ®, &bit); + type = bank->pull_type[pin_num / 8]; + ret = rockchip_translate_pull_value(type, pull); + if (ret < 0) { + debug("unsupported pull setting %d\n", pull); + return ret; + } + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_PULL_BITS_PER_PIN) - 1) << (bit + 16); + + data |= (ret << bit); + ret = regmap_write(regmap, reg, data); + + return ret; +} + +#define RV1126_DRV_PMU_OFFSET 0x20 +#define RV1126_DRV_GRF_GPIO1A0_OFFSET 0x10090 +#define RV1126_DRV_BITS_PER_PIN 4 +#define RV1126_DRV_PINS_PER_REG 4 +#define RV1126_DRV_BANK_STRIDE 32 + +static void rv1126_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + + /* The first 24 pins of the first bank are located in PMU */ + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_DRV_PINS_PER_REG + 1) * 4); + *reg -= 0x4; + *bit = pin_num % RV1126_DRV_PINS_PER_REG; + *bit *= RV1126_DRV_BITS_PER_PIN; + return; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_DRV_PMU_OFFSET; + } else { + *regmap = priv->regmap_base; + *reg = RV1126_DRV_GRF_GPIO1A0_OFFSET; + *reg += (bank->bank_num - 1) * RV1126_DRV_BANK_STRIDE; + } + + *reg += ((pin_num / RV1126_DRV_PINS_PER_REG) * 4); + *bit = pin_num % RV1126_DRV_PINS_PER_REG; + *bit *= RV1126_DRV_BITS_PER_PIN; +} + +static int rv1126_set_drive(struct rockchip_pin_bank *bank, + int pin_num, int strength) +{ + struct regmap *regmap; + int reg; + u32 data; + u8 bit; + + rv1126_calc_drv_reg_and_bit(bank, pin_num, ®map, ®, &bit); + + /* enable the write to the equivalent lower bits */ + data = ((1 << ROCKCHIP_DRV_BITS_PER_PIN) - 1) << (bit + 16); + data |= (strength << bit); + + return regmap_write(regmap, reg, data); +} + +#define RV1126_SCHMITT_PMU_OFFSET 0x60 +#define RV1126_SCHMITT_GRF_GPIO1A0_OFFSET 0x10188 +#define RV1126_SCHMITT_BANK_STRIDE 16 +#define RV1126_SCHMITT_PINS_PER_GRF_REG 8 +#define RV1126_SCHMITT_PINS_PER_PMU_REG 8 + +static int rv1126_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank, + int pin_num, + struct regmap **regmap, + int *reg, u8 *bit) +{ + struct rockchip_pinctrl_priv *priv = bank->priv; + int pins_per_reg; + + if (bank->bank_num == 0) { + if (RV1126_GPIO_C4_D7(pin_num)) { + *regmap = priv->regmap_base; + *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; + *reg -= (((31 - pin_num) / RV1126_SCHMITT_PINS_PER_GRF_REG + 1) * 4); + *bit = pin_num % RV1126_SCHMITT_PINS_PER_GRF_REG; + return 0; + } + *regmap = priv->regmap_pmu; + *reg = RV1126_SCHMITT_PMU_OFFSET; + pins_per_reg = RV1126_SCHMITT_PINS_PER_PMU_REG; + } else { + *regmap = priv->regmap_base; + *reg = RV1126_SCHMITT_GRF_GPIO1A0_OFFSET; + pins_per_reg = RV1126_SCHMITT_PINS_PER_GRF_REG; + *reg += (bank->bank_num - 1) * RV1126_SCHMITT_BANK_STRIDE; + } + *reg += ((pin_num / pins_per_reg) * 4); + *bit = pin_num % pins_per_reg; + + return 0; +} + +static int rv1126_set_schmitt(struct rockchip_pin_bank *bank, + int pin_num, int enable) +{ + struct regmap *regmap; + int reg; + u8 bit; + u32 data; + + rv1126_calc_schmitt_reg_and_bit(bank, pin_num, ®map, ®, &bit); + /* enable the write to the equivalent lower bits */ + data = BIT(bit + 16) | (enable << bit); + + return regmap_write(regmap, reg, data); +} + +static struct rockchip_pin_bank rv1126_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU, + IOMUX_WIDTH_4BIT | IOMUX_L_SOURCE_PMU, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + 0x10010, 0x10018, 0x10020, 0x10028), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT, + IOMUX_WIDTH_4BIT), + PIN_BANK_IOMUX_FLAGS(4, 2, "gpio4", + IOMUX_WIDTH_4BIT, 0, 0, 0), +}; + +static const struct rockchip_pin_ctrl rv1126_pin_ctrl = { + .pin_banks = rv1126_pin_banks, + .nr_banks = ARRAY_SIZE(rv1126_pin_banks), + .nr_pins = 130, + .grf_mux_offset = 0x10004, /* mux offset from GPIO0_D0 */ + .pmu_mux_offset = 0x0, + .iomux_routes = rv1126_mux_route_data, + .niomux_routes = ARRAY_SIZE(rv1126_mux_route_data), + .iomux_recalced = rv1126_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rv1126_mux_recalced_data), + .set_mux = rv1126_set_mux, + .set_pull = rv1126_set_pull, + .set_drive = rv1126_set_drive, + .set_schmitt = rv1126_set_schmitt, +}; + +static const struct udevice_id rv1126_pinctrl_ids[] = { + { + .compatible = "rockchip,rv1126-pinctrl", + .data = (ulong)&rv1126_pin_ctrl + }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rv1126) = { + .name = "rockchip_rv1126_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rv1126_pinctrl_ids, + .priv_auto = sizeof(struct rockchip_pinctrl_priv), + .ops = &rockchip_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rockchip_pinctrl_probe, +};
Add clock and reset unit header include for rv1126.
Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
.../include/asm/arch-rockchip/cru_rv1126.h | 459 ++++++++++++++++++ 1 file changed, 459 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1126.h
diff --git a/arch/arm/include/asm/arch-rockchip/cru_rv1126.h b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h new file mode 100644 index 0000000000..49a1f76379 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rv1126.h @@ -0,0 +1,459 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao finley.xiao@rock-chips.com + */ + +#ifndef _ASM_ARCH_CRU_RV1126_H +#define _ASM_ARCH_CRU_RV1126_H + +#define MHz 1000000 +#define KHz 1000 +#define OSC_HZ (24 * MHz) + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define APLL_HZ (1008 * MHz) +#else +#define APLL_HZ (816 * MHz) +#endif +#define GPLL_HZ (1188 * MHz) +#define CPLL_HZ (500 * MHz) +#define HPLL_HZ (1400 * MHz) +#define PCLK_PDPMU_HZ (100 * MHz) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define ACLK_PDBUS_HZ (396 * MHz) +#else +#define ACLK_PDBUS_HZ (500 * MHz) +#endif +#define HCLK_PDBUS_HZ (200 * MHz) +#define PCLK_PDBUS_HZ (100 * MHz) +#define ACLK_PDPHP_HZ (300 * MHz) +#define HCLK_PDPHP_HZ (200 * MHz) +#define HCLK_PDCORE_HZ (200 * MHz) +#define HCLK_PDAUDIO_HZ (150 * MHz) +#define CLK_OSC0_DIV_HZ (32768) +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) +#define ACLK_PDVI_HZ (297 * MHz) +#define CLK_ISP_HZ (297 * MHz) +#define ACLK_PDISPP_HZ (297 * MHz) +#define CLK_ISPP_HZ (237 * MHz) +#define ACLK_VOP_HZ (300 * MHz) +#define DCLK_VOP_HZ (65 * MHz) +#endif + +/* RV1126 pll id */ +enum rv1126_pll_id { + APLL, + DPLL, + CPLL, + HPLL, + GPLL, + PLL_COUNT, +}; + +struct rv1126_clk_info { + unsigned long id; + char *name; + bool is_cru; +}; + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rv1126_pmuclk_priv { + struct rv1126_pmucru *pmucru; + ulong gpll_hz; +}; + +struct rv1126_clk_priv { + struct rv1126_cru *cru; + struct rv1126_grf *grf; + ulong gpll_hz; + ulong cpll_hz; + ulong hpll_hz; + ulong armclk_hz; + ulong armclk_enter_hz; + ulong armclk_init_hz; + bool sync_kernel; + bool set_armclk_rate; +}; + +struct rv1126_pll { + unsigned int con0; + unsigned int con1; + unsigned int con2; + unsigned int con3; + unsigned int con4; + unsigned int con5; + unsigned int con6; + unsigned int reserved0[1]; +}; + +struct rv1126_pmucru { + unsigned int pmu_mode; + unsigned int reserved1[3]; + struct rv1126_pll pll; + unsigned int offsetcal_status; + unsigned int reserved2[51]; + unsigned int pmu_clksel_con[14]; + unsigned int reserved3[18]; + unsigned int pmu_clkgate_con[3]; + unsigned int reserved4[29]; + unsigned int pmu_softrst_con[2]; + unsigned int reserved5[14]; + unsigned int pmu_autocs_con[2]; +}; + +check_member(rv1126_pmucru, pmu_autocs_con[1], 0x244); + +struct rv1126_cru { + struct rv1126_pll pll[4]; + unsigned int offsetcal_status[4]; + unsigned int mode; + unsigned int reserved1[27]; + unsigned int clksel_con[78]; + unsigned int reserved2[18]; + unsigned int clkgate_con[25]; + unsigned int reserved3[7]; + unsigned int softrst_con[15]; + unsigned int reserved4[17]; + unsigned int ssgtbl[32]; + unsigned int glb_cnt_th; + unsigned int glb_rst_st; + unsigned int glb_srst_fst; + unsigned int glb_srst_snd; + unsigned int glb_rst_con; + unsigned int reserved5[11]; + unsigned int sdmmc_con[2]; + unsigned int sdio_con[2]; + unsigned int emmc_con[2]; + unsigned int reserved6[2]; + unsigned int gmac_con; + unsigned int misc[2]; + unsigned int reserved7[45]; + unsigned int autocs_con[26]; +}; + +check_member(rv1126_cru, autocs_con[25], 0x584); + +struct pll_rate_table { + unsigned long rate; + unsigned int fbdiv; + unsigned int postdiv1; + unsigned int refdiv; + unsigned int postdiv2; + unsigned int dsmpd; + unsigned int frac; +}; + +struct cpu_rate_table { + unsigned long rate; + unsigned int aclk_div; + unsigned int pclk_div; +}; + +#define RV1126_PMU_MODE 0x0 +#define RV1126_PMU_PLL_CON(x) ((x) * 0x4 + 0x10) +#define RV1126_PLL_CON(x) ((x) * 0x4) +#define RV1126_MODE_CON 0x90 + +enum { + /* CRU_PMU_CLK_SEL0_CON */ + RTC32K_SEL_SHIFT = 7, + RTC32K_SEL_MASK = 0x3 << RTC32K_SEL_SHIFT, + RTC32K_SEL_PMUPVTM = 0, + RTC32K_SEL_OSC1_32K, + RTC32K_SEL_OSC0_DIV32K, + + /* CRU_PMU_CLK_SEL1_CON */ + PCLK_PDPMU_DIV_SHIFT = 0, + PCLK_PDPMU_DIV_MASK = 0x1f, + + /* CRU_PMU_CLK_SEL2_CON */ + CLK_I2C0_DIV_SHIFT = 0, + CLK_I2C0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL3_CON */ + CLK_I2C2_DIV_SHIFT = 0, + CLK_I2C2_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL6_CON */ + CLK_PWM1_SEL_SHIFT = 15, + CLK_PWM1_SEL_MASK = 1 << CLK_PWM1_SEL_SHIFT, + CLK_PWM1_SEL_XIN24M = 0, + CLK_PWM1_SEL_GPLL, + CLK_PWM1_DIV_SHIFT = 8, + CLK_PWM1_DIV_MASK = 0x7f << CLK_PWM1_DIV_SHIFT, + CLK_PWM0_SEL_SHIFT = 7, + CLK_PWM0_SEL_MASK = 1 << CLK_PWM0_SEL_SHIFT, + CLK_PWM0_SEL_XIN24M = 0, + CLK_PWM0_SEL_GPLL, + CLK_PWM0_DIV_SHIFT = 0, + CLK_PWM0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL9_CON */ + CLK_SPI0_SEL_SHIFT = 7, + CLK_SPI0_SEL_MASK = 1 << CLK_SPI0_SEL_SHIFT, + CLK_SPI0_SEL_GPLL = 0, + CLK_SPI0_SEL_XIN24M, + CLK_SPI0_DIV_SHIFT = 0, + CLK_SPI0_DIV_MASK = 0x7f, + + /* CRU_PMU_CLK_SEL13_CON */ + CLK_RTC32K_FRAC_NUMERATOR_SHIFT = 16, + CLK_RTC32K_FRAC_NUMERATOR_MASK = 0xffff << 16, + CLK_RTC32K_FRAC_DENOMINATOR_SHIFT = 0, + CLK_RTC32K_FRAC_DENOMINATOR_MASK = 0xffff, + + /* CRU_CLK_SEL0_CON */ + CORE_HCLK_DIV_SHIFT = 8, + CORE_HCLK_DIV_MASK = 0x1f << CORE_HCLK_DIV_SHIFT, + + /* CRU_CLK_SEL1_CON */ + CORE_ACLK_DIV_SHIFT = 4, + CORE_ACLK_DIV_MASK = 0xf << CORE_ACLK_DIV_SHIFT, + CORE_DBG_DIV_SHIFT = 0, + CORE_DBG_DIV_MASK = 0x7, + + /* CRU_CLK_SEL2_CON */ + HCLK_PDBUS_SEL_SHIFT = 15, + HCLK_PDBUS_SEL_MASK = 1 << HCLK_PDBUS_SEL_SHIFT, + HCLK_PDBUS_SEL_GPLL = 0, + HCLK_PDBUS_SEL_CPLL, + HCLK_PDBUS_DIV_SHIFT = 8, + HCLK_PDBUS_DIV_MASK = 0x1f << HCLK_PDBUS_DIV_SHIFT, + ACLK_PDBUS_SEL_SHIFT = 6, + ACLK_PDBUS_SEL_MASK = 0x3 << ACLK_PDBUS_SEL_SHIFT, + ACLK_PDBUS_SEL_GPLL = 0, + ACLK_PDBUS_SEL_CPLL, + ACLK_PDBUS_SEL_DPLL, + ACLK_PDBUS_DIV_SHIFT = 0, + ACLK_PDBUS_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL3_CON */ + CLK_SCR1_SEL_SHIFT = 15, + CLK_SCR1_SEL_MASK = 1 << CLK_SCR1_SEL_SHIFT, + CLK_SCR1_SEL_GPLL = 0, + CLK_SCR1_SEL_CPLL, + CLK_SCR1_DIV_SHIFT = 8, + CLK_SCR1_DIV_MASK = 0x1f << CLK_SCR1_DIV_SHIFT, + PCLK_PDBUS_SEL_SHIFT = 7, + PCLK_PDBUS_SEL_MASK = 1 << PCLK_PDBUS_SEL_SHIFT, + PCLK_PDBUS_SEL_GPLL = 0, + PCLK_PDBUS_SEL_CPLL, + PCLK_PDBUS_DIV_SHIFT = 0, + PCLK_PDBUS_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL4_CON */ + ACLK_CRYPTO_SEL_SHIFT = 7, + ACLK_CRYPTO_SEL_MASK = 1 << ACLK_CRYPTO_SEL_SHIFT, + ACLK_CRYPTO_SEL_GPLL = 0, + ACLK_CRYPTO_SEL_CPLL, + ACLK_CRYPTO_DIV_SHIFT = 0, + ACLK_CRYPTO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL5_CON */ + CLK_I2C3_DIV_SHIFT = 8, + CLK_I2C3_DIV_MASK = 0x7f << CLK_I2C3_DIV_SHIFT, + CLK_I2C1_DIV_SHIFT = 0, + CLK_I2C1_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL6_CON */ + CLK_I2C5_DIV_SHIFT = 8, + CLK_I2C5_DIV_MASK = 0x7f << CLK_I2C5_DIV_SHIFT, + CLK_I2C4_DIV_SHIFT = 0, + CLK_I2C4_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL7_CON */ + CLK_CRYPTO_PKA_SEL_SHIFT = 15, + CLK_CRYPTO_PKA_SEL_MASK = 1 << CLK_CRYPTO_PKA_SEL_SHIFT, + CLK_CRYPTO_PKA_SEL_GPLL = 0, + CLK_CRYPTO_PKA_SEL_CPLL, + CLK_CRYPTO_PKA_DIV_SHIFT = 8, + CLK_CRYPTO_PKA_DIV_MASK = 0x1f << CLK_CRYPTO_PKA_DIV_SHIFT, + CLK_CRYPTO_CORE_SEL_SHIFT = 7, + CLK_CRYPTO_CORE_SEL_MASK = 1 << CLK_CRYPTO_CORE_SEL_SHIFT, + CLK_CRYPTO_CORE_SEL_GPLL = 0, + CLK_CRYPTO_CORE_SEL_CPLL, + CLK_CRYPTO_CORE_DIV_SHIFT = 0, + CLK_CRYPTO_CORE_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL8_CON */ + CLK_SPI1_SEL_SHIFT = 8, + CLK_SPI1_SEL_MASK = 1 << CLK_SPI1_SEL_SHIFT, + CLK_SPI1_SEL_GPLL = 0, + CLK_SPI1_SEL_XIN24M, + CLK_SPI1_DIV_SHIFT = 0, + CLK_SPI1_DIV_MASK = 0x7f, + + /* CRU_CLK_SEL9_CON */ + CLK_PWM2_SEL_SHIFT = 15, + CLK_PWM2_SEL_MASK = 1 << CLK_PWM2_SEL_SHIFT, + CLK_PWM2_SEL_XIN24M = 0, + CLK_PWM2_SEL_GPLL, + CLK_PWM2_DIV_SHIFT = 8, + CLK_PWM2_DIV_MASK = 0x7f << CLK_PWM2_DIV_SHIFT, + + /* CRU_CLK_SEL20_CON */ + CLK_SARADC_DIV_SHIFT = 0, + CLK_SARADC_DIV_MASK = 0x7ff, + + /* CRU_CLK_SEL25_CON */ + DCLK_DECOM_SEL_SHIFT = 15, + DCLK_DECOM_SEL_MASK = 1 << DCLK_DECOM_SEL_SHIFT, + DCLK_DECOM_SEL_GPLL = 0, + DCLK_DECOM_SEL_CPLL, + DCLK_DECOM_DIV_SHIFT = 8, + DCLK_DECOM_DIV_MASK = 0x7f << DCLK_DECOM_DIV_SHIFT, + + /* CRU_CLK_SEL26_CON */ + HCLK_PDAUDIO_DIV_SHIFT = 0, + HCLK_PDAUDIO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL45_CON */ + ACLK_PDVO_SEL_SHIFT = 7, + ACLK_PDVO_SEL_MASK = 1 << ACLK_PDVO_SEL_SHIFT, + ACLK_PDVO_SEL_GPLL = 0, + ACLK_PDVO_SEL_CPLL, + ACLK_PDVO_DIV_SHIFT = 0, + ACLK_PDVO_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL47_CON */ + DCLK_VOP_SEL_SHIFT = 8, + DCLK_VOP_SEL_MASK = 1 << DCLK_VOP_SEL_SHIFT, + DCLK_VOP_SEL_GPLL = 0, + DCLK_VOP_SEL_CPLL, + DCLK_VOP_DIV_SHIFT = 0, + DCLK_VOP_DIV_MASK = 0xff, + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) + /* CRU_CLK_SEL49_CON */ + ACLK_PDVI_SEL_SHIFT = 6, + ACLK_PDVI_SEL_MASK = 0x3 << ACLK_PDVI_SEL_SHIFT, + ACLK_PDVI_SEL_CPLL = 0, + ACLK_PDVI_SEL_GPLL, + ACLK_PDVI_SEL_HPLL, + ACLK_PDVI_DIV_SHIFT = 0, + ACLK_PDVI_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL50_CON */ + CLK_ISP_SEL_SHIFT = 6, + CLK_ISP_SEL_MASK = 0x3 << CLK_ISP_SEL_SHIFT, + CLK_ISP_SEL_GPLL = 0, + CLK_ISP_SEL_CPLL, + CLK_ISP_SEL_HPLL, + CLK_ISP_DIV_SHIFT = 0, + CLK_ISP_DIV_MASK = 0x1f, +#endif + + /* CRU_CLK_SEL53_CON */ + HCLK_PDPHP_DIV_SHIFT = 8, + HCLK_PDPHP_DIV_MASK = 0x1f << HCLK_PDPHP_DIV_SHIFT, + ACLK_PDPHP_SEL_SHIFT = 7, + ACLK_PDPHP_SEL_MASK = 1 << ACLK_PDPHP_SEL_SHIFT, + ACLK_PDPHP_SEL_GPLL = 0, + ACLK_PDPHP_SEL_CPLL, + ACLK_PDPHP_DIV_SHIFT = 0, + ACLK_PDPHP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL57_CON */ + EMMC_SEL_SHIFT = 14, + EMMC_SEL_MASK = 0x3 << EMMC_SEL_SHIFT, + EMMC_SEL_GPLL = 0, + EMMC_SEL_CPLL, + EMMC_SEL_XIN24M, + EMMC_DIV_SHIFT = 0, + EMMC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL58_CON */ + SCLK_SFC_SEL_SHIFT = 15, + SCLK_SFC_SEL_MASK = 0x1 << SCLK_SFC_SEL_SHIFT, + SCLK_SFC_SEL_CPLL = 0, + SCLK_SFC_SEL_GPLL, + SCLK_SFC_DIV_SHIFT = 0, + SCLK_SFC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL59_CON */ + CLK_NANDC_SEL_SHIFT = 15, + CLK_NANDC_SEL_MASK = 0x1 << CLK_NANDC_SEL_SHIFT, + CLK_NANDC_SEL_GPLL = 0, + CLK_NANDC_SEL_CPLL, + CLK_NANDC_DIV_SHIFT = 0, + CLK_NANDC_DIV_MASK = 0xff, + + /* CRU_CLK_SEL61_CON */ + CLK_GMAC_OUT_SEL_SHIFT = 15, + CLK_GMAC_OUT_SEL_MASK = 0x1 << CLK_GMAC_OUT_SEL_SHIFT, + CLK_GMAC_OUT_SEL_CPLL = 0, + CLK_GMAC_OUT_SEL_GPLL, + CLK_GMAC_OUT_DIV_SHIFT = 8, + CLK_GMAC_OUT_DIV_MASK = 0x1f << CLK_GMAC_OUT_DIV_SHIFT, + + /* CRU_CLK_SEL63_CON */ + PCLK_GMAC_DIV_SHIFT = 8, + PCLK_GMAC_DIV_MASK = 0x1f << PCLK_GMAC_DIV_SHIFT, + CLK_GMAC_SRC_SEL_SHIFT = 7, + CLK_GMAC_SRC_SEL_MASK = 0x1 << CLK_GMAC_SRC_SEL_SHIFT, + CLK_GMAC_SRC_SEL_CPLL = 0, + CLK_GMAC_SRC_SEL_GPLL, + CLK_GMAC_SRC_DIV_SHIFT = 0, + CLK_GMAC_SRC_DIV_MASK = 0x1f << CLK_GMAC_SRC_DIV_SHIFT, + +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_KERNEL_BOOT) + /* CRU_CLK_SEL68_CON */ + ACLK_PDISPP_SEL_SHIFT = 6, + ACLK_PDISPP_SEL_MASK = 0x3 << ACLK_PDISPP_SEL_SHIFT, + ACLK_PDISPP_SEL_CPLL = 0, + ACLK_PDISPP_SEL_GPLL, + ACLK_PDISPP_SEL_HPLL, + ACLK_PDISPP_DIV_SHIFT = 0, + ACLK_PDISPP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL69_CON */ + CLK_ISPP_SEL_SHIFT = 6, + CLK_ISPP_SEL_MASK = 0x3 << CLK_ISPP_SEL_SHIFT, + CLK_ISPP_SEL_CPLL = 0, + CLK_ISPP_SEL_GPLL, + CLK_ISPP_SEL_HPLL, + CLK_ISPP_DIV_SHIFT = 0, + CLK_ISPP_DIV_MASK = 0x1f, + + /* CRU_CLK_SEL73_CON */ + MIPICSI_OUT_SEL_SHIFT = 10, + MIPICSI_OUT_SEL_MASK = 0x3 << MIPICSI_OUT_SEL_SHIFT, + MIPICSI_OUT_SEL_XIN24M = 0, + MIPICSI_OUT_SEL_DIV, + MIPICSI_OUT_SEL_FRACDIV, + MIPICSI_OUT_DIV_SHIFT = 0, + MIPICSI_OUT_DIV_MASK = 0x1f, +#endif + + /* CRU_GMAC_CON */ + GMAC_SRC_M1_SEL_SHIFT = 5, + GMAC_SRC_M1_SEL_MASK = 0x1 << GMAC_SRC_M1_SEL_SHIFT, + GMAC_SRC_M1_SEL_INT = 0, + GMAC_SRC_M1_SEL_EXT, + GMAC_MODE_SEL_SHIFT = 4, + GMAC_MODE_SEL_MASK = 0x1 << GMAC_MODE_SEL_SHIFT, + GMAC_RGMII_MODE = 0, + GMAC_RMII_MODE, + RGMII_CLK_SEL_SHIFT = 2, + RGMII_CLK_SEL_MASK = 0x3 << RGMII_CLK_SEL_SHIFT, + RGMII_CLK_DIV0 = 0, + RGMII_CLK_DIV1, + RGMII_CLK_DIV50, + RGMII_CLK_DIV5, + RMII_CLK_SEL_SHIFT = 1, + RMII_CLK_SEL_MASK = 0x1 << RMII_CLK_SEL_SHIFT, + RMII_CLK_DIV20 = 0, + RMII_CLK_DIV2, + GMAC_SRC_M0_SEL_SHIFT = 0, + GMAC_SRC_M0_SEL_MASK = 0x1, + GMAC_SRC_M0_SEL_INT = 0, + GMAC_SRC_M0_SEL_EXT, + + /* GRF_IOFUNC_CON1 */ + GMAC_SRC_SEL_SHIFT = 12, + GMAC_SRC_SEL_MASK = 1 << GMAC_SRC_SEL_SHIFT, + GMAC_SRC_SEL_M0 = 0, + GMAC_SRC_SEL_M1, +}; +#endif
Add the dt-bindings header for the Rockchip RV1126, that gets shared between the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao finley.xiao@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
.../dt-bindings/clock/rockchip,rv1126-cru.h | 632 ++++++++++++++++++ 1 file changed, 632 insertions(+) create mode 100644 include/dt-bindings/clock/rockchip,rv1126-cru.h
diff --git a/include/dt-bindings/clock/rockchip,rv1126-cru.h b/include/dt-bindings/clock/rockchip,rv1126-cru.h new file mode 100644 index 0000000000..cfba8226de --- /dev/null +++ b/include/dt-bindings/clock/rockchip,rv1126-cru.h @@ -0,0 +1,632 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2019 Rockchip Electronics Co. Ltd. + * Author: Finley Xiao finley.xiao@rock-chips.com + */ + +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H +#define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H + +/* pmucru-clocks indices */ + +/* pll clocks */ +#define PLL_GPLL 1 + +/* sclk (special clocks) */ +#define CLK_OSC0_DIV32K 2 +#define CLK_RTC32K 3 +#define CLK_WIFI_DIV 4 +#define CLK_WIFI_OSC0 5 +#define CLK_WIFI 6 +#define CLK_PMU 7 +#define SCLK_UART1_DIV 8 +#define SCLK_UART1_FRACDIV 9 +#define SCLK_UART1_MUX 10 +#define SCLK_UART1 11 +#define CLK_I2C0 12 +#define CLK_I2C2 13 +#define CLK_CAPTURE_PWM0 14 +#define CLK_PWM0 15 +#define CLK_CAPTURE_PWM1 16 +#define CLK_PWM1 17 +#define CLK_SPI0 18 +#define DBCLK_GPIO0 19 +#define CLK_PMUPVTM 20 +#define CLK_CORE_PMUPVTM 21 +#define CLK_REF12M 22 +#define CLK_USBPHY_OTG_REF 23 +#define CLK_USBPHY_HOST_REF 24 +#define CLK_REF24M 25 +#define CLK_MIPIDSIPHY_REF 26 + +/* pclk */ +#define PCLK_PDPMU 30 +#define PCLK_PMU 31 +#define PCLK_UART1 32 +#define PCLK_I2C0 33 +#define PCLK_I2C2 34 +#define PCLK_PWM0 35 +#define PCLK_PWM1 36 +#define PCLK_SPI0 37 +#define PCLK_GPIO0 38 +#define PCLK_PMUSGRF 39 +#define PCLK_PMUGRF 40 +#define PCLK_PMUCRU 41 +#define PCLK_CHIPVEROTP 42 +#define PCLK_PDPMU_NIU 43 +#define PCLK_PMUPVTM 44 +#define PCLK_SCRKEYGEN 45 + +#define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1) + +/* cru-clocks indices */ + +/* pll clocks */ +#define PLL_APLL 1 +#define PLL_DPLL 2 +#define PLL_CPLL 3 +#define PLL_HPLL 4 + +/* sclk (special clocks) */ +#define ARMCLK 5 +#define USB480M 6 +#define CLK_CORE_CPUPVTM 7 +#define CLK_CPUPVTM 8 +#define CLK_SCR1 9 +#define CLK_SCR1_CORE 10 +#define CLK_SCR1_RTC 11 +#define CLK_SCR1_JTAG 12 +#define SCLK_UART0_DIV 13 +#define SCLK_UART0_FRAC 14 +#define SCLK_UART0_MUX 15 +#define SCLK_UART0 16 +#define SCLK_UART2_DIV 17 +#define SCLK_UART2_FRAC 18 +#define SCLK_UART2_MUX 19 +#define SCLK_UART2 20 +#define SCLK_UART3_DIV 21 +#define SCLK_UART3_FRAC 22 +#define SCLK_UART3_MUX 23 +#define SCLK_UART3 24 +#define SCLK_UART4_DIV 25 +#define SCLK_UART4_FRAC 26 +#define SCLK_UART4_MUX 27 +#define SCLK_UART4 28 +#define SCLK_UART5_DIV 29 +#define SCLK_UART5_FRAC 30 +#define SCLK_UART5_MUX 31 +#define SCLK_UART5 32 +#define CLK_I2C1 33 +#define CLK_I2C3 34 +#define CLK_I2C4 35 +#define CLK_I2C5 36 +#define CLK_SPI1 37 +#define CLK_CAPTURE_PWM2 38 +#define CLK_PWM2 39 +#define DBCLK_GPIO1 40 +#define DBCLK_GPIO2 41 +#define DBCLK_GPIO3 42 +#define DBCLK_GPIO4 43 +#define CLK_SARADC 44 +#define CLK_TIMER0 45 +#define CLK_TIMER1 46 +#define CLK_TIMER2 47 +#define CLK_TIMER3 48 +#define CLK_TIMER4 49 +#define CLK_TIMER5 50 +#define CLK_CAN 51 +#define CLK_NPU_TSADC 52 +#define CLK_NPU_TSADCPHY 53 +#define CLK_CPU_TSADC 54 +#define CLK_CPU_TSADCPHY 55 +#define CLK_CRYPTO_CORE 56 +#define CLK_CRYPTO_PKA 57 +#define MCLK_I2S0_TX_DIV 58 +#define MCLK_I2S0_TX_FRACDIV 59 +#define MCLK_I2S0_TX_MUX 60 +#define MCLK_I2S0_TX 61 +#define MCLK_I2S0_RX_DIV 62 +#define MCLK_I2S0_RX_FRACDIV 63 +#define MCLK_I2S0_RX_MUX 64 +#define MCLK_I2S0_RX 65 +#define MCLK_I2S0_TX_OUT2IO 66 +#define MCLK_I2S0_RX_OUT2IO 67 +#define MCLK_I2S1_DIV 68 +#define MCLK_I2S1_FRACDIV 69 +#define MCLK_I2S1_MUX 70 +#define MCLK_I2S1 71 +#define MCLK_I2S1_OUT2IO 72 +#define MCLK_I2S2_DIV 73 +#define MCLK_I2S2_FRACDIV 74 +#define MCLK_I2S2_MUX 75 +#define MCLK_I2S2 76 +#define MCLK_I2S2_OUT2IO 77 +#define MCLK_PDM 78 +#define SCLK_ADUPWM_DIV 79 +#define SCLK_AUDPWM_FRACDIV 80 +#define SCLK_AUDPWM_MUX 81 +#define SCLK_AUDPWM 82 +#define CLK_ACDCDIG_ADC 83 +#define CLK_ACDCDIG_DAC 84 +#define CLK_ACDCDIG_I2C 85 +#define CLK_VENC_CORE 86 +#define CLK_VDEC_CORE 87 +#define CLK_VDEC_CA 88 +#define CLK_VDEC_HEVC_CA 89 +#define CLK_RGA_CORE 90 +#define CLK_IEP_CORE 91 +#define CLK_ISP_DIV 92 +#define CLK_ISP_NP5 93 +#define CLK_ISP_NUX 94 +#define CLK_ISP 95 +#define CLK_CIF_OUT_DIV 96 +#define CLK_CIF_OUT_FRACDIV 97 +#define CLK_CIF_OUT_MUX 98 +#define CLK_CIF_OUT 99 +#define CLK_MIPICSI_OUT_DIV 100 +#define CLK_MIPICSI_OUT_FRACDIV 101 +#define CLK_MIPICSI_OUT_MUX 102 +#define CLK_MIPICSI_OUT 103 +#define CLK_ISPP_DIV 104 +#define CLK_ISPP_NP5 105 +#define CLK_ISPP_NUX 106 +#define CLK_ISPP 107 +#define CLK_SDMMC 108 +#define SCLK_SDMMC_DRV 109 +#define SCLK_SDMMC_SAMPLE 110 +#define CLK_SDIO 111 +#define SCLK_SDIO_DRV 112 +#define SCLK_SDIO_SAMPLE 113 +#define CLK_EMMC 114 +#define SCLK_EMMC_DRV 115 +#define SCLK_EMMC_SAMPLE 116 +#define CLK_NANDC 117 +#define SCLK_SFC 118 +#define CLK_USBHOST_UTMI_OHCI 119 +#define CLK_USBOTG_REF 120 +#define CLK_GMAC_DIV 121 +#define CLK_GMAC_RGMII_M0 122 +#define CLK_GMAC_SRC_M0 123 +#define CLK_GMAC_RGMII_M1 124 +#define CLK_GMAC_SRC_M1 125 +#define CLK_GMAC_SRC 126 +#define CLK_GMAC_REF 127 +#define CLK_GMAC_TX_SRC 128 +#define CLK_GMAC_TX_DIV5 129 +#define CLK_GMAC_TX_DIV50 130 +#define RGMII_MODE_CLK 131 +#define CLK_GMAC_RX_SRC 132 +#define CLK_GMAC_RX_DIV2 133 +#define CLK_GMAC_RX_DIV20 134 +#define RMII_MODE_CLK 135 +#define CLK_GMAC_TX_RX 136 +#define CLK_GMAC_PTPREF 137 +#define CLK_GMAC_ETHERNET_OUT 138 +#define CLK_DDRPHY 139 +#define CLK_DDR_MON 140 +#define TMCLK_DDR_MON 141 +#define CLK_NPU_DIV 142 +#define CLK_NPU_NP5 143 +#define CLK_CORE_NPU 144 +#define CLK_CORE_NPUPVTM 145 +#define CLK_NPUPVTM 146 +#define SCLK_DDRCLK 147 +#define CLK_OTP 148 + +/* dclk */ +#define DCLK_DECOM 150 +#define DCLK_VOP_DIV 151 +#define DCLK_VOP_FRACDIV 152 +#define DCLK_VOP_MUX 153 +#define DCLK_VOP 154 +#define DCLK_CIF 155 +#define DCLK_CIFLITE 156 + +/* aclk */ +#define ACLK_PDBUS 160 +#define ACLK_DMAC 161 +#define ACLK_DCF 162 +#define ACLK_SPINLOCK 163 +#define ACLK_DECOM 164 +#define ACLK_PDCRYPTO 165 +#define ACLK_CRYPTO 166 +#define ACLK_PDVEPU 167 +#define ACLK_VENC 168 +#define ACLK_PDVDEC 169 +#define ACLK_PDJPEG 170 +#define ACLK_VDEC 171 +#define ACLK_JPEG 172 +#define ACLK_PDVO 173 +#define ACLK_RGA 174 +#define ACLK_VOP 175 +#define ACLK_IEP 176 +#define ACLK_PDVI_DIV 177 +#define ACLK_PDVI_NP5 178 +#define ACLK_PDVI 179 +#define ACLK_ISP 180 +#define ACLK_CIF 181 +#define ACLK_CIFLITE 182 +#define ACLK_PDISPP_DIV 183 +#define ACLK_PDISPP_NP5 184 +#define ACLK_PDISPP 185 +#define ACLK_ISPP 186 +#define ACLK_PDPHP 187 +#define ACLK_PDUSB 188 +#define ACLK_USBOTG 189 +#define ACLK_PDGMAC 190 +#define ACLK_GMAC 191 +#define ACLK_PDNPU_DIV 192 +#define ACLK_PDNPU_NP5 193 +#define ACLK_PDNPU 194 +#define ACLK_NPU 195 + +/* hclk */ +#define HCLK_PDCORE_NIU 200 +#define HCLK_PDUSB 201 +#define HCLK_PDCRYPTO 202 +#define HCLK_CRYPTO 203 +#define HCLK_PDAUDIO 204 +#define HCLK_I2S0 205 +#define HCLK_I2S1 206 +#define HCLK_I2S2 207 +#define HCLK_PDM 208 +#define HCLK_AUDPWM 209 +#define HCLK_PDVEPU 210 +#define HCLK_VENC 211 +#define HCLK_PDVDEC 212 +#define HCLK_PDJPEG 213 +#define HCLK_VDEC 214 +#define HCLK_JPEG 215 +#define HCLK_PDVO 216 +#define HCLK_RGA 217 +#define HCLK_VOP 218 +#define HCLK_IEP 219 +#define HCLK_PDVI 220 +#define HCLK_ISP 221 +#define HCLK_CIF 222 +#define HCLK_CIFLITE 223 +#define HCLK_PDISPP 224 +#define HCLK_ISPP 225 +#define HCLK_PDPHP 226 +#define HCLK_PDSDMMC 227 +#define HCLK_SDMMC 228 +#define HCLK_PDSDIO 229 +#define HCLK_SDIO 230 +#define HCLK_PDNVM 231 +#define HCLK_EMMC 232 +#define HCLK_NANDC 233 +#define HCLK_SFC 234 +#define HCLK_SFCXIP 235 +#define HCLK_PDBUS 236 +#define HCLK_USBHOST 237 +#define HCLK_USBHOST_ARB 238 +#define HCLK_PDNPU 239 +#define HCLK_NPU 240 + +/* pclk */ +#define PCLK_CPUPVTM 245 +#define PCLK_PDBUS 246 +#define PCLK_DCF 247 +#define PCLK_WDT 248 +#define PCLK_MAILBOX 249 +#define PCLK_UART0 250 +#define PCLK_UART2 251 +#define PCLK_UART3 252 +#define PCLK_UART4 253 +#define PCLK_UART5 254 +#define PCLK_I2C1 255 +#define PCLK_I2C3 256 +#define PCLK_I2C4 257 +#define PCLK_I2C5 258 +#define PCLK_SPI1 259 +#define PCLK_PWM2 261 +#define PCLK_GPIO1 262 +#define PCLK_GPIO2 263 +#define PCLK_GPIO3 264 +#define PCLK_GPIO4 265 +#define PCLK_SARADC 266 +#define PCLK_TIMER 267 +#define PCLK_DECOM 268 +#define PCLK_CAN 269 +#define PCLK_NPU_TSADC 270 +#define PCLK_CPU_TSADC 271 +#define PCLK_ACDCDIG 272 +#define PCLK_PDVO 273 +#define PCLK_DSIHOST 274 +#define PCLK_PDVI 275 +#define PCLK_CSIHOST 276 +#define PCLK_PDGMAC 277 +#define PCLK_GMAC 278 +#define PCLK_PDDDR 279 +#define PCLK_DDR_MON 280 +#define PCLK_PDNPU 281 +#define PCLK_NPUPVTM 282 +#define PCLK_PDTOP 283 +#define PCLK_TOPCRU 284 +#define PCLK_TOPGRF 285 +#define PCLK_CPUEMADET 286 +#define PCLK_DDRPHY 287 +#define PCLK_DSIPHY 289 +#define PCLK_CSIPHY0 290 +#define PCLK_CSIPHY1 291 +#define PCLK_USBPHY_HOST 292 +#define PCLK_USBPHY_OTG 293 +#define PCLK_OTP 294 + +#define CLK_NR_CLKS (PCLK_OTP + 1) + +/* pmu soft-reset indices */ + +/* pmu_cru_softrst_con0 */ +#define SRST_PDPMU_NIU_P 0 +#define SRST_PMU_SGRF_P 1 +#define SRST_PMU_SGRF_REMAP_P 2 +#define SRST_I2C0_P 3 +#define SRST_I2C0 4 +#define SRST_I2C2_P 7 +#define SRST_I2C2 8 +#define SRST_UART1_P 9 +#define SRST_UART1 10 +#define SRST_PWM0_P 11 +#define SRST_PWM0 12 +#define SRST_PWM1_P 13 +#define SRST_PWM1 14 +#define SRST_DDR_FAIL_SAFE 15 + +/* pmu_cru_softrst_con1 */ +#define SRST_GPIO0_P 17 +#define SRST_GPIO0_DB 18 +#define SRST_SPI0_P 19 +#define SRST_SPI0 20 +#define SRST_PMUGRF_P 21 +#define SRST_CHIPVEROTP_P 22 +#define SRST_PMUPVTM 24 +#define SRST_PMUPVTM_P 25 +#define SRST_PMUCRU_P 30 + +/* soft-reset indices */ + +/* cru_softrst_con0 */ +#define SRST_CORE0_PO 0 +#define SRST_CORE1_PO 1 +#define SRST_CORE2_PO 2 +#define SRST_CORE3_PO 3 +#define SRST_CORE0 4 +#define SRST_CORE1 5 +#define SRST_CORE2 6 +#define SRST_CORE3 7 +#define SRST_CORE0_DBG 8 +#define SRST_CORE1_DBG 9 +#define SRST_CORE2_DBG 10 +#define SRST_CORE3_DBG 11 +#define SRST_NL2 12 +#define SRST_CORE_NIU_A 13 +#define SRST_DBG_DAPLITE_P 14 +#define SRST_DAPLITE_P 15 + +/* cru_softrst_con1 */ +#define SRST_PDBUS_NIU1_A 16 +#define SRST_PDBUS_NIU1_H 17 +#define SRST_PDBUS_NIU1_P 18 +#define SRST_PDBUS_NIU2_A 19 +#define SRST_PDBUS_NIU2_H 20 +#define SRST_PDBUS_NIU3_A 21 +#define SRST_PDBUS_NIU3_H 22 +#define SRST_PDBUS_HOLD_NIU1_A 23 +#define SRST_DBG_NIU_P 24 +#define SRST_PDCORE_NIIU_H 25 +#define SRST_MUC_NIU 26 +#define SRST_DCF_A 29 +#define SRST_DCF_P 30 +#define SRST_SYSTEM_SRAM_A 31 + +/* cru_softrst_con2 */ +#define SRST_I2C1_P 32 +#define SRST_I2C1 33 +#define SRST_I2C3_P 34 +#define SRST_I2C3 35 +#define SRST_I2C4_P 36 +#define SRST_I2C4 37 +#define SRST_I2C5_P 38 +#define SRST_I2C5 39 +#define SRST_SPI1_P 40 +#define SRST_SPI1 41 +#define SRST_MCU_CORE 42 +#define SRST_PWM2_P 44 +#define SRST_PWM2 45 +#define SRST_SPINLOCK_A 46 + +/* cru_softrst_con3 */ +#define SRST_UART0_P 48 +#define SRST_UART0 49 +#define SRST_UART2_P 50 +#define SRST_UART2 51 +#define SRST_UART3_P 52 +#define SRST_UART3 53 +#define SRST_UART4_P 54 +#define SRST_UART4 55 +#define SRST_UART5_P 56 +#define SRST_UART5 57 +#define SRST_WDT_P 58 +#define SRST_SARADC_P 59 +#define SRST_GRF_P 61 +#define SRST_TIMER_P 62 +#define SRST_MAILBOX_P 63 + +/* cru_softrst_con4 */ +#define SRST_TIMER0 64 +#define SRST_TIMER1 65 +#define SRST_TIMER2 66 +#define SRST_TIMER3 67 +#define SRST_TIMER4 68 +#define SRST_TIMER5 69 +#define SRST_INTMUX_P 70 +#define SRST_GPIO1_P 72 +#define SRST_GPIO1_DB 73 +#define SRST_GPIO2_P 74 +#define SRST_GPIO2_DB 75 +#define SRST_GPIO3_P 76 +#define SRST_GPIO3_DB 77 +#define SRST_GPIO4_P 78 +#define SRST_GPIO4_DB 79 + +/* cru_softrst_con5 */ +#define SRST_CAN_P 80 +#define SRST_CAN 81 +#define SRST_DECOM_A 85 +#define SRST_DECOM_P 86 +#define SRST_DECOM_D 87 +#define SRST_PDCRYPTO_NIU_A 88 +#define SRST_PDCRYPTO_NIU_H 89 +#define SRST_CRYPTO_A 90 +#define SRST_CRYPTO_H 91 +#define SRST_CRYPTO_CORE 92 +#define SRST_CRYPTO_PKA 93 +#define SRST_SGRF_P 95 + +/* cru_softrst_con6 */ +#define SRST_PDAUDIO_NIU_H 96 +#define SRST_PDAUDIO_NIU_P 97 +#define SRST_I2S0_H 98 +#define SRST_I2S0_TX_M 99 +#define SRST_I2S0_RX_M 100 +#define SRST_I2S1_H 101 +#define SRST_I2S1_M 102 +#define SRST_I2S2_H 103 +#define SRST_I2S2_M 104 +#define SRST_PDM_H 105 +#define SRST_PDM_M 106 +#define SRST_AUDPWM_H 107 +#define SRST_AUDPWM 108 +#define SRST_ACDCDIG_P 109 +#define SRST_ACDCDIG 110 + +/* cru_softrst_con7 */ +#define SRST_PDVEPU_NIU_A 112 +#define SRST_PDVEPU_NIU_H 113 +#define SRST_VENC_A 114 +#define SRST_VENC_H 115 +#define SRST_VENC_CORE 116 +#define SRST_PDVDEC_NIU_A 117 +#define SRST_PDVDEC_NIU_H 118 +#define SRST_VDEC_A 119 +#define SRST_VDEC_H 120 +#define SRST_VDEC_CORE 121 +#define SRST_VDEC_CA 122 +#define SRST_VDEC_HEVC_CA 123 +#define SRST_PDJPEG_NIU_A 124 +#define SRST_PDJPEG_NIU_H 125 +#define SRST_JPEG_A 126 +#define SRST_JPEG_H 127 + +/* cru_softrst_con8 */ +#define SRST_PDVO_NIU_A 128 +#define SRST_PDVO_NIU_H 129 +#define SRST_PDVO_NIU_P 130 +#define SRST_RGA_A 131 +#define SRST_RGA_H 132 +#define SRST_RGA_CORE 133 +#define SRST_VOP_A 134 +#define SRST_VOP_H 135 +#define SRST_VOP_D 136 +#define SRST_TXBYTEHS_DSIHOST 137 +#define SRST_DSIHOST_P 138 +#define SRST_IEP_A 139 +#define SRST_IEP_H 140 +#define SRST_IEP_CORE 141 +#define SRST_ISP_RX_P 142 + +/* cru_softrst_con9 */ +#define SRST_PDVI_NIU_A 144 +#define SRST_PDVI_NIU_H 145 +#define SRST_PDVI_NIU_P 146 +#define SRST_ISP 147 +#define SRST_CIF_A 148 +#define SRST_CIF_H 149 +#define SRST_CIF_D 150 +#define SRST_CIF_P 151 +#define SRST_CIF_I 152 +#define SRST_CIF_RX_P 153 +#define SRST_PDISPP_NIU_A 154 +#define SRST_PDISPP_NIU_H 155 +#define SRST_ISPP_A 156 +#define SRST_ISPP_H 157 +#define SRST_ISPP 158 +#define SRST_CSIHOST_P 159 + +/* cru_softrst_con10 */ +#define SRST_PDPHPMID_NIU_A 160 +#define SRST_PDPHPMID_NIU_H 161 +#define SRST_PDNVM_NIU_H 163 +#define SRST_SDMMC_H 164 +#define SRST_SDIO_H 165 +#define SRST_EMMC_H 166 +#define SRST_SFC_H 167 +#define SRST_SFCXIP_H 168 +#define SRST_SFC 169 +#define SRST_NANDC_H 170 +#define SRST_NANDC 171 +#define SRST_PDSDMMC_H 173 +#define SRST_PDSDIO_H 174 + +/* cru_softrst_con11 */ +#define SRST_PDUSB_NIU_A 176 +#define SRST_PDUSB_NIU_H 177 +#define SRST_USBHOST_H 178 +#define SRST_USBHOST_ARB_H 179 +#define SRST_USBHOST_UTMI 180 +#define SRST_USBOTG_A 181 +#define SRST_USBPHY_OTG_P 182 +#define SRST_USBPHY_HOST_P 183 +#define SRST_USBPHYPOR_OTG 184 +#define SRST_USBPHYPOR_HOST 185 +#define SRST_PDGMAC_NIU_A 188 +#define SRST_PDGMAC_NIU_P 189 +#define SRST_GMAC_A 190 + +/* cru_softrst_con12 */ +#define SRST_DDR_DFICTL_P 193 +#define SRST_DDR_MON_P 194 +#define SRST_DDR_STANDBY_P 195 +#define SRST_DDR_GRF_P 196 +#define SRST_DDR_MSCH_P 197 +#define SRST_DDR_SPLIT_A 198 +#define SRST_DDR_MSCH 199 +#define SRST_DDR_DFICTL 202 +#define SRST_DDR_STANDBY 203 +#define SRST_NPUMCU_NIU 205 +#define SRST_DDRPHY_P 206 +#define SRST_DDRPHY 207 + +/* cru_softrst_con13 */ +#define SRST_PDNPU_NIU_A 208 +#define SRST_PDNPU_NIU_H 209 +#define SRST_PDNPU_NIU_P 210 +#define SRST_NPU_A 211 +#define SRST_NPU_H 212 +#define SRST_NPU 213 +#define SRST_NPUPVTM_P 214 +#define SRST_NPUPVTM 215 +#define SRST_NPU_TSADC_P 216 +#define SRST_NPU_TSADC 217 +#define SRST_NPU_TSADCPHY 218 +#define SRST_CIFLITE_A 220 +#define SRST_CIFLITE_H 221 +#define SRST_CIFLITE_D 222 +#define SRST_CIFLITE_RX_P 223 + +/* cru_softrst_con14 */ +#define SRST_TOPNIU_P 224 +#define SRST_TOPCRU_P 225 +#define SRST_TOPGRF_P 226 +#define SRST_CPUEMADET_P 227 +#define SRST_CSIPHY0_P 228 +#define SRST_CSIPHY1_P 229 +#define SRST_DSIPHY_P 230 +#define SRST_CPU_TSADC_P 232 +#define SRST_CPU_TSADC 233 +#define SRST_CPU_TSADCPHY 234 +#define SRST_CPUPVTM_P 235 +#define SRST_CPUPVTM 236 + +#endif
Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen chenjh@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rv1126.c | 1889 +++++++++++++++++++++++++++++ 2 files changed, 1890 insertions(+) create mode 100644 drivers/clk/rockchip/clk_rv1126.c
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index a72d8fe58a..f719f4e379 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += clk_rk3368.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o obj-$(CONFIG_ROCKCHIP_RK3568) += clk_rk3568.o obj-$(CONFIG_ROCKCHIP_RV1108) += clk_rv1108.o +obj-$(CONFIG_ROCKCHIP_RV1126) += clk_rv1126.o diff --git a/drivers/clk/rockchip/clk_rv1126.c b/drivers/clk/rockchip/clk_rv1126.c new file mode 100644 index 0000000000..3ed29364de --- /dev/null +++ b/drivers/clk/rockchip/clk_rv1126.c @@ -0,0 +1,1889 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + * Author: Finley Xiao finley.xiao@rock-chips.com + */ + +#include <common.h> +#include <bitfield.h> +#include <clk-uclass.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1126.h> +#include <asm/arch-rockchip/grf_rv1126.h> +#include <asm/arch-rockchip/hardware.h> +#include <dm/device-internal.h> +#include <asm/io.h> +#include <dm/lists.h> +#include <dt-bindings/clock/rockchip,rv1126-cru.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define RV1126_CPUCLK_RATE(_rate, _aclk_div, _pclk_div) \ +{ \ + .rate = _rate##U, \ + .aclk_div = _aclk_div, \ + .pclk_div = _pclk_div, \ +} + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +static struct rockchip_cpu_rate_table rv1126_cpu_rates[] = { + RV1126_CPUCLK_RATE(1200000000, 1, 5), + RV1126_CPUCLK_RATE(1008000000, 1, 5), + RV1126_CPUCLK_RATE(816000000, 1, 3), + RV1126_CPUCLK_RATE(600000000, 1, 3), + RV1126_CPUCLK_RATE(408000000, 1, 1), +}; + +static struct rockchip_pll_rate_table rv1126_pll_rates[] = { + /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */ + RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0), + RK3036_PLL_RATE(1400000000, 3, 350, 2, 1, 1, 0), + RK3036_PLL_RATE(1200000000, 1, 100, 2, 1, 1, 0), + RK3036_PLL_RATE(1188000000, 1, 99, 2, 1, 1, 0), + RK3036_PLL_RATE(1100000000, 3, 275, 2, 1, 1, 0), + RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0), + RK3036_PLL_RATE(1000000000, 3, 250, 2, 1, 1, 0), + RK3036_PLL_RATE(816000000, 1, 68, 2, 1, 1, 0), + RK3036_PLL_RATE(800000000, 3, 200, 2, 1, 1, 0), + RK3036_PLL_RATE(600000000, 1, 100, 4, 1, 1, 0), + RK3036_PLL_RATE(594000000, 1, 99, 4, 1, 1, 0), + RK3036_PLL_RATE(500000000, 1, 125, 6, 1, 1, 0), + RK3036_PLL_RATE(200000000, 1, 100, 6, 2, 1, 0), + RK3036_PLL_RATE(100000000, 1, 100, 6, 4, 1, 0), + { /* sentinel */ }, +}; + +static struct rockchip_pll_clock rv1126_pll_clks[] = { + [APLL] = PLL(pll_rk3328, PLL_APLL, RV1126_PLL_CON(0), + RV1126_MODE_CON, 0, 10, 0, rv1126_pll_rates), + [DPLL] = PLL(pll_rk3328, PLL_DPLL, RV1126_PLL_CON(8), + RV1126_MODE_CON, 2, 10, 0, NULL), + [CPLL] = PLL(pll_rk3328, PLL_CPLL, RV1126_PLL_CON(16), + RV1126_MODE_CON, 4, 10, 0, rv1126_pll_rates), + [HPLL] = PLL(pll_rk3328, PLL_HPLL, RV1126_PLL_CON(24), + RV1126_MODE_CON, 6, 10, 0, rv1126_pll_rates), + [GPLL] = PLL(pll_rk3328, PLL_GPLL, RV1126_PMU_PLL_CON(0), + RV1126_PMU_MODE, 0, 10, 0, rv1126_pll_rates), +}; + +static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, + struct rv1126_pmuclk_priv *pmu_priv, + ulong rate); +/* + * + * rational_best_approximation(31415, 10000, + * (1 << 8) - 1, (1 << 5) - 1, &n, &d); + * + * you may look at given_numerator as a fixed point number, + * with the fractional part size described in given_denominator. + * + * for theoretical background, see: + * http://en.wikipedia.org/wiki/Continued_fraction + */ +static void rational_best_approximation(unsigned long given_numerator, + unsigned long given_denominator, + unsigned long max_numerator, + unsigned long max_denominator, + unsigned long *best_numerator, + unsigned long *best_denominator) +{ + unsigned long n, d, n0, d0, n1, d1; + + n = given_numerator; + d = given_denominator; + n0 = 0; + d1 = 0; + n1 = 1; + d0 = 1; + for (;;) { + unsigned long t, a; + + if (n1 > max_numerator || d1 > max_denominator) { + n1 = n0; + d1 = d0; + break; + } + if (d == 0) + break; + t = d; + a = n / d; + d = n % d; + n = t; + t = n0 + a * n1; + n0 = n1; + n1 = t; + t = d0 + a * d1; + d0 = d1; + d1 = t; + } + *best_numerator = n1; + *best_denominator = d1; +} + +static ulong rv1126_gpll_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + return rockchip_pll_get_rate(&rv1126_pll_clks[GPLL], + priv->pmucru, GPLL); +} + +static ulong rv1126_gpll_set_pmuclk(struct rv1126_pmuclk_priv *pmu_priv, ulong rate) +{ + struct udevice *cru_dev; + struct rv1126_clk_priv *priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_cru), + &cru_dev); + if (ret) { + printf("%s: could not find cru device\n", __func__); + return ret; + } + priv = dev_get_priv(cru_dev); + + if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { + printf("%s: failed to set gpll rate %lu\n", __func__, rate); + return -EINVAL; + } + return 0; +} + +static ulong rv1126_rtc32k_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + unsigned long m, n; + u32 fracdiv; + + fracdiv = readl(&pmucru->pmu_clksel_con[13]); + m = fracdiv & CLK_RTC32K_FRAC_NUMERATOR_MASK; + m >>= CLK_RTC32K_FRAC_NUMERATOR_SHIFT; + n = fracdiv & CLK_RTC32K_FRAC_DENOMINATOR_MASK; + n >>= CLK_RTC32K_FRAC_DENOMINATOR_SHIFT; + + return OSC_HZ * m / n; +} + +static ulong rv1126_rtc32k_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + unsigned long m, n, val; + + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + + rational_best_approximation(rate, OSC_HZ, + GENMASK(16 - 1, 0), + GENMASK(16 - 1, 0), + &m, &n); + val = m << CLK_RTC32K_FRAC_NUMERATOR_SHIFT | n; + writel(val, &pmucru->pmu_clksel_con[13]); + + return rv1126_rtc32k_get_pmuclk(priv); +} + +static ulong rv1126_i2c_get_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + switch (clk_id) { + case CLK_I2C0: + con = readl(&pmucru->pmu_clksel_con[2]); + div = (con & CLK_I2C0_DIV_MASK) >> CLK_I2C0_DIV_SHIFT; + break; + case CLK_I2C2: + con = readl(&pmucru->pmu_clksel_con[3]); + div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_i2c_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case CLK_I2C0: + rk_clrsetreg(&pmucru->pmu_clksel_con[2], CLK_I2C0_DIV_MASK, + (src_clk_div - 1) << CLK_I2C0_DIV_SHIFT); + break; + case CLK_I2C2: + rk_clrsetreg(&pmucru->pmu_clksel_con[3], CLK_I2C2_DIV_MASK, + (src_clk_div - 1) << CLK_I2C2_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_i2c_get_pmuclk(priv, clk_id); +} + +static ulong rv1126_pwm_get_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, sel, con; + + switch (clk_id) { + case CLK_PWM0: + con = readl(&pmucru->pmu_clksel_con[6]); + sel = (con & CLK_PWM0_SEL_MASK) >> CLK_PWM0_SEL_SHIFT; + div = (con & CLK_PWM0_DIV_MASK) >> CLK_PWM0_DIV_SHIFT; + if (sel == CLK_PWM0_SEL_XIN24M) + return OSC_HZ; + break; + case CLK_PWM1: + con = readl(&pmucru->pmu_clksel_con[6]); + sel = (con & CLK_PWM1_SEL_MASK) >> CLK_PWM1_SEL_SHIFT; + div = (con & CLK_PWM1_DIV_MASK) >> CLK_PWM1_DIV_SHIFT; + if (sel == CLK_PWM1_SEL_XIN24M) + return OSC_HZ; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pwm_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong clk_id, ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + switch (clk_id) { + case CLK_PWM0: + if (rate == OSC_HZ) { + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_SEL_MASK, + CLK_PWM0_SEL_XIN24M << CLK_PWM0_SEL_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_DIV_MASK, + (src_clk_div - 1) << CLK_PWM0_DIV_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM0_SEL_MASK, + CLK_PWM0_SEL_GPLL << CLK_PWM0_SEL_SHIFT); + } + break; + case CLK_PWM1: + if (rate == OSC_HZ) { + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_SEL_MASK, + CLK_PWM1_SEL_XIN24M << CLK_PWM1_SEL_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_DIV_MASK, + (src_clk_div - 1) << CLK_PWM1_DIV_SHIFT); + rk_clrsetreg(&pmucru->pmu_clksel_con[6], + CLK_PWM1_SEL_MASK, + CLK_PWM1_SEL_GPLL << CLK_PWM1_SEL_SHIFT); + } + break; + default: + return -ENOENT; + } + + return rv1126_pwm_get_pmuclk(priv, clk_id); +} + +static ulong rv1126_spi_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + con = readl(&pmucru->pmu_clksel_con[9]); + div = (con & CLK_SPI0_DIV_MASK) >> CLK_SPI0_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_spi_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + rk_clrsetreg(&pmucru->pmu_clksel_con[9], + CLK_SPI0_SEL_MASK | CLK_SPI0_DIV_MASK, + CLK_SPI0_SEL_GPLL << CLK_SPI0_SEL_SHIFT | + (src_clk_div - 1) << CLK_SPI0_DIV_SHIFT); + + return rv1126_spi_get_pmuclk(priv); +} + +static ulong rv1126_pdpmu_get_pmuclk(struct rv1126_pmuclk_priv *priv) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + u32 div, con; + + con = readl(&pmucru->pmu_clksel_con[1]); + div = (con & PCLK_PDPMU_DIV_MASK) >> PCLK_PDPMU_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdpmu_set_pmuclk(struct rv1126_pmuclk_priv *priv, + ulong rate) +{ + struct rv1126_pmucru *pmucru = priv->pmucru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&pmucru->pmu_clksel_con[1], + PCLK_PDPMU_DIV_MASK, + (src_clk_div - 1) << PCLK_PDPMU_DIV_SHIFT); + + return rv1126_pdpmu_get_pmuclk(priv); +} + +static ulong rv1126_pmuclk_get_rate(struct clk *clk) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + debug("%s %ld\n", __func__, clk->id); + switch (clk->id) { + case PLL_GPLL: + rate = rv1126_gpll_get_pmuclk(priv); + break; + case CLK_RTC32K: + rate = rv1126_rtc32k_get_pmuclk(priv); + break; + case CLK_I2C0: + case CLK_I2C2: + rate = rv1126_i2c_get_pmuclk(priv, clk->id); + break; + case CLK_PWM0: + case CLK_PWM1: + rate = rv1126_pwm_get_pmuclk(priv, clk->id); + break; + case CLK_SPI0: + rate = rv1126_spi_get_pmuclk(priv); + break; + case PCLK_PDPMU: + rate = rv1126_pdpmu_get_pmuclk(priv); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +} + +static ulong rv1126_pmuclk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + debug("%s %ld %ld\n", __func__, clk->id, rate); + switch (clk->id) { + case PLL_GPLL: + ret = rv1126_gpll_set_pmuclk(priv, rate); + break; + case CLK_RTC32K: + ret = rv1126_rtc32k_set_pmuclk(priv, rate); + break; + case CLK_I2C0: + case CLK_I2C2: + ret = rv1126_i2c_set_pmuclk(priv, clk->id, rate); + break; + case CLK_PWM0: + case CLK_PWM1: + ret = rv1126_pwm_set_pmuclk(priv, clk->id, rate); + break; + case CLK_SPI0: + ret = rv1126_spi_set_pmuclk(priv, rate); + break; + case PCLK_PDPMU: + ret = rv1126_pdpmu_set_pmuclk(priv, rate); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return ret; +} + +static int rv1126_rtc32k_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_pmucru *pmucru = priv->pmucru; + + if (parent->id == CLK_OSC0_DIV32K) + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC0_DIV32K << RTC32K_SEL_SHIFT); + else + rk_clrsetreg(&pmucru->pmu_clksel_con[0], RTC32K_SEL_MASK, + RTC32K_SEL_OSC1_32K << RTC32K_SEL_SHIFT); + + return 0; +} + +static int rv1126_pmuclk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case CLK_RTC32K: + return rv1126_rtc32k_set_parent(clk, parent); + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } +} + +static struct clk_ops rv1126_pmuclk_ops = { + .get_rate = rv1126_pmuclk_get_rate, + .set_rate = rv1126_pmuclk_set_rate, + .set_parent = rv1126_pmuclk_set_parent, +}; + +static int rv1126_pmuclk_probe(struct udevice *dev) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); + + priv->gpll_hz = rv1126_gpll_get_pmuclk(priv); + + return 0; +} + +static int rv1126_pmuclk_of_to_plat(struct udevice *dev) +{ + struct rv1126_pmuclk_priv *priv = dev_get_priv(dev); + + priv->pmucru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rv1126_pmuclk_bind(struct udevice *dev) +{ +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + int ret; + + ret = offsetof(struct rv1126_pmucru, pmu_softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 2); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; +} + +static const struct udevice_id rv1126_pmuclk_ids[] = { + { .compatible = "rockchip,rv1126-pmucru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rv1126_pmucru) = { + .name = "rockchip_rv1126_pmucru", + .id = UCLASS_CLK, + .of_match = rv1126_pmuclk_ids, + .priv_auto = sizeof(struct rv1126_pmuclk_priv), + .of_to_plat = rv1126_pmuclk_of_to_plat, + .ops = &rv1126_pmuclk_ops, + .bind = rv1126_pmuclk_bind, + .probe = rv1126_pmuclk_probe, +}; + +static int rv1126_armclk_set_clk(struct rv1126_clk_priv *priv, ulong hz) +{ + struct rv1126_cru *cru = priv->cru; + const struct rockchip_cpu_rate_table *rate; + ulong old_rate; + + rate = rockchip_get_cpu_settings(rv1126_cpu_rates, hz); + if (!rate) { + printf("%s unsupported rate\n", __func__); + return -EINVAL; + } + + /* + * set up dependent divisors for DBG and ACLK clocks. + */ + old_rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL); + if (old_rate > hz) { + if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + rk_clrsetreg(&cru->clksel_con[1], + CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, + rate->pclk_div << CORE_DBG_DIV_SHIFT | + rate->aclk_div << CORE_ACLK_DIV_SHIFT); + } else if (old_rate < hz) { + rk_clrsetreg(&cru->clksel_con[1], + CORE_DBG_DIV_MASK | CORE_ACLK_DIV_MASK, + rate->pclk_div << CORE_DBG_DIV_SHIFT | + rate->aclk_div << CORE_ACLK_DIV_SHIFT); + if (rockchip_pll_set_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL, hz)) + return -EINVAL; + } + + return 0; +} + +static ulong rv1126_pdcore_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div; + + con = readl(&cru->clksel_con[0]); + div = (con & CORE_HCLK_DIV_MASK) >> CORE_HCLK_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdcore_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&cru->clksel_con[0], CORE_HCLK_DIV_MASK, + (src_clk_div - 1) << CORE_HCLK_DIV_SHIFT); + + return rv1126_pdcore_get_clk(priv); +} + +static ulong rv1126_pdbus_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div, sel, parent; + + switch (clk_id) { + case ACLK_PDBUS: + con = readl(&cru->clksel_con[2]); + div = (con & ACLK_PDBUS_DIV_MASK) >> ACLK_PDBUS_DIV_SHIFT; + sel = (con & ACLK_PDBUS_SEL_MASK) >> ACLK_PDBUS_SEL_SHIFT; + if (sel == ACLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case HCLK_PDBUS: + con = readl(&cru->clksel_con[2]); + div = (con & HCLK_PDBUS_DIV_MASK) >> HCLK_PDBUS_DIV_SHIFT; + sel = (con & HCLK_PDBUS_SEL_MASK) >> HCLK_PDBUS_SEL_SHIFT; + if (sel == HCLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == HCLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case PCLK_PDBUS: + case PCLK_WDT: + con = readl(&cru->clksel_con[3]); + div = (con & PCLK_PDBUS_DIV_MASK) >> PCLK_PDBUS_DIV_SHIFT; + sel = (con & PCLK_PDBUS_SEL_MASK) >> PCLK_PDBUS_SEL_SHIFT; + if (sel == PCLK_PDBUS_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == PCLK_PDBUS_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_pdbus_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div, clk_sel; + + switch (clk_id) { + case ACLK_PDBUS: + if (CPLL_HZ % rate) { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_GPLL; + } else { + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + clk_sel = ACLK_PDBUS_SEL_CPLL; + } + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[2], + ACLK_PDBUS_SEL_MASK | ACLK_PDBUS_DIV_MASK, + clk_sel << ACLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDBUS_DIV_SHIFT); + break; + case HCLK_PDBUS: + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[2], + HCLK_PDBUS_SEL_MASK | HCLK_PDBUS_DIV_MASK, + HCLK_PDBUS_SEL_GPLL << HCLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << HCLK_PDBUS_DIV_SHIFT); + break; + case PCLK_PDBUS: + case PCLK_WDT: + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[3], + PCLK_PDBUS_SEL_MASK | PCLK_PDBUS_DIV_MASK, + PCLK_PDBUS_SEL_GPLL << PCLK_PDBUS_SEL_SHIFT | + (src_clk_div - 1) << PCLK_PDBUS_DIV_SHIFT); + break; + + default: + printf("do not support this pdbus freq\n"); + return -EINVAL; + } + + return rv1126_pdbus_get_clk(priv, clk_id); +} + +static ulong rv1126_pdphp_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div, parent; + + switch (clk_id) { + case ACLK_PDPHP: + con = readl(&cru->clksel_con[53]); + div = (con & ACLK_PDPHP_DIV_MASK) >> ACLK_PDPHP_DIV_SHIFT; + parent = priv->gpll_hz; + break; + case HCLK_PDPHP: + con = readl(&cru->clksel_con[53]); + div = (con & HCLK_PDPHP_DIV_MASK) >> HCLK_PDPHP_DIV_SHIFT; + parent = priv->gpll_hz; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_pdphp_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + switch (clk_id) { + case ACLK_PDPHP: + rk_clrsetreg(&cru->clksel_con[53], + ACLK_PDPHP_SEL_MASK | ACLK_PDPHP_DIV_MASK, + ACLK_PDPHP_SEL_GPLL << ACLK_PDPHP_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDPHP_DIV_SHIFT); + break; + case HCLK_PDPHP: + rk_clrsetreg(&cru->clksel_con[53], + HCLK_PDPHP_DIV_MASK, + (src_clk_div - 1) << HCLK_PDPHP_DIV_SHIFT); + break; + default: + printf("do not support this pdphp freq\n"); + return -EINVAL; + } + + return rv1126_pdphp_get_clk(priv, clk_id); +} + +static ulong rv1126_pdaudio_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, div; + + con = readl(&cru->clksel_con[26]); + div = (con & HCLK_PDAUDIO_DIV_MASK) >> HCLK_PDAUDIO_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pdaudio_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + rk_clrsetreg(&cru->clksel_con[26], HCLK_PDAUDIO_DIV_MASK, + (src_clk_div - 1) << HCLK_PDAUDIO_DIV_SHIFT); + + return rv1126_pdaudio_get_clk(priv); +} + +static ulong rv1126_i2c_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + switch (clk_id) { + case CLK_I2C1: + con = readl(&cru->clksel_con[5]); + div = (con & CLK_I2C1_DIV_MASK) >> CLK_I2C1_DIV_SHIFT; + break; + case CLK_I2C3: + con = readl(&cru->clksel_con[5]); + div = (con & CLK_I2C3_DIV_MASK) >> CLK_I2C3_DIV_SHIFT; + break; + case CLK_I2C4: + con = readl(&cru->clksel_con[6]); + div = (con & CLK_I2C4_DIV_MASK) >> CLK_I2C4_DIV_SHIFT; + break; + case CLK_I2C5: + con = readl(&cru->clksel_con[6]); + div = (con & CLK_I2C5_DIV_MASK) >> CLK_I2C5_DIV_SHIFT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_i2c_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + switch (clk_id) { + case CLK_I2C1: + rk_clrsetreg(&cru->clksel_con[5], CLK_I2C1_DIV_MASK, + (src_clk_div - 1) << CLK_I2C1_DIV_SHIFT); + break; + case CLK_I2C3: + rk_clrsetreg(&cru->clksel_con[5], CLK_I2C3_DIV_MASK, + (src_clk_div - 1) << CLK_I2C3_DIV_SHIFT); + break; + case CLK_I2C4: + rk_clrsetreg(&cru->clksel_con[6], CLK_I2C4_DIV_MASK, + (src_clk_div - 1) << CLK_I2C4_DIV_SHIFT); + break; + case CLK_I2C5: + rk_clrsetreg(&cru->clksel_con[6], CLK_I2C5_DIV_MASK, + (src_clk_div - 1) << CLK_I2C5_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_i2c_get_clk(priv, clk_id); +} + +static ulong rv1126_spi_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[8]); + div = (con & CLK_SPI1_DIV_MASK) >> CLK_SPI1_DIV_SHIFT; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_spi_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + + rk_clrsetreg(&cru->clksel_con[8], + CLK_SPI1_SEL_MASK | CLK_SPI1_DIV_MASK, + CLK_SPI1_SEL_GPLL << CLK_SPI1_SEL_SHIFT | + (src_clk_div - 1) << CLK_SPI1_DIV_SHIFT); + + return rv1126_spi_get_clk(priv); +} + +static ulong rv1126_pwm_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con; + + con = readl(&cru->clksel_con[9]); + sel = (con & CLK_PWM2_SEL_MASK) >> CLK_PWM2_SEL_SHIFT; + div = (con & CLK_PWM2_DIV_MASK) >> CLK_PWM2_DIV_SHIFT; + if (sel == CLK_PWM2_SEL_XIN24M) + return OSC_HZ; + + return DIV_TO_RATE(priv->gpll_hz, div); +} + +static ulong rv1126_pwm_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + if (rate == OSC_HZ) { + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, + CLK_PWM2_SEL_XIN24M << CLK_PWM2_SEL_SHIFT); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, 0); + } else { + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_DIV_MASK, + (src_clk_div - 1) << CLK_PWM2_DIV_SHIFT); + rk_clrsetreg(&cru->clksel_con[9], CLK_PWM2_SEL_MASK, + CLK_PWM2_SEL_GPLL << CLK_PWM2_SEL_SHIFT); + } + + return rv1126_pwm_get_clk(priv); +} + +static ulong rv1126_saradc_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con; + + con = readl(&cru->clksel_con[20]); + div = (con & CLK_SARADC_DIV_MASK) >> CLK_SARADC_DIV_SHIFT; + + return DIV_TO_RATE(OSC_HZ, div); +} + +static ulong rv1126_saradc_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(OSC_HZ, rate); + assert(src_clk_div - 1 <= 2047); + rk_clrsetreg(&cru->clksel_con[20], CLK_SARADC_DIV_MASK, + (src_clk_div - 1) << CLK_SARADC_DIV_SHIFT); + + return rv1126_saradc_get_clk(priv); +} + +static ulong rv1126_crypto_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + switch (clk_id) { + case CLK_CRYPTO_CORE: + con = readl(&cru->clksel_con[7]); + div = (con & CLK_CRYPTO_CORE_DIV_MASK) >> CLK_CRYPTO_CORE_DIV_SHIFT; + sel = (con & CLK_CRYPTO_CORE_SEL_MASK) >> CLK_CRYPTO_CORE_SEL_SHIFT; + if (sel == CLK_CRYPTO_CORE_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_CRYPTO_CORE_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case CLK_CRYPTO_PKA: + con = readl(&cru->clksel_con[7]); + div = (con & CLK_CRYPTO_PKA_DIV_MASK) >> CLK_CRYPTO_PKA_DIV_SHIFT; + sel = (con & CLK_CRYPTO_PKA_SEL_MASK) >> CLK_CRYPTO_PKA_SEL_SHIFT; + if (sel == CLK_CRYPTO_PKA_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_CRYPTO_PKA_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + case ACLK_CRYPTO: + con = readl(&cru->clksel_con[4]); + div = (con & ACLK_CRYPTO_DIV_MASK) >> ACLK_CRYPTO_DIV_SHIFT; + sel = (con & ACLK_CRYPTO_SEL_MASK) >> ACLK_CRYPTO_SEL_SHIFT; + if (sel == ACLK_CRYPTO_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_CRYPTO_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + break; + default: + return -ENOENT; + } + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_crypto_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + + switch (clk_id) { + case CLK_CRYPTO_CORE: + rk_clrsetreg(&cru->clksel_con[7], + CLK_CRYPTO_CORE_SEL_MASK | + CLK_CRYPTO_CORE_DIV_MASK, + CLK_CRYPTO_CORE_SEL_GPLL << + CLK_CRYPTO_CORE_SEL_SHIFT | + (src_clk_div - 1) << CLK_CRYPTO_CORE_DIV_SHIFT); + break; + case CLK_CRYPTO_PKA: + rk_clrsetreg(&cru->clksel_con[7], + CLK_CRYPTO_PKA_SEL_MASK | + CLK_CRYPTO_PKA_DIV_MASK, + CLK_CRYPTO_PKA_SEL_GPLL << + CLK_CRYPTO_PKA_SEL_SHIFT | + (src_clk_div - 1) << CLK_CRYPTO_PKA_DIV_SHIFT); + break; + case ACLK_CRYPTO: + rk_clrsetreg(&cru->clksel_con[4], + ACLK_CRYPTO_SEL_MASK | ACLK_CRYPTO_DIV_MASK, + ACLK_CRYPTO_SEL_GPLL << ACLK_CRYPTO_SEL_SHIFT | + (src_clk_div - 1) << ACLK_CRYPTO_DIV_SHIFT); + break; + default: + return -ENOENT; + } + + return rv1126_crypto_get_clk(priv, clk_id); +} + +static ulong rv1126_mmc_get_clk(struct rv1126_clk_priv *priv, ulong clk_id) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, con_id; + + switch (clk_id) { + case HCLK_SDMMC: + case CLK_SDMMC: + con_id = 55; + break; + case HCLK_SDIO: + case CLK_SDIO: + con_id = 56; + break; + case HCLK_EMMC: + case CLK_EMMC: + case SCLK_EMMC_SAMPLE: + con_id = 57; + break; + default: + return -ENOENT; + } + + con = readl(&cru->clksel_con[con_id]); + div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT; + sel = (con & EMMC_SEL_MASK) >> EMMC_SEL_SHIFT; + if (sel == EMMC_SEL_GPLL) + return DIV_TO_RATE(priv->gpll_hz, div) / 2; + else if (sel == EMMC_SEL_CPLL) + return DIV_TO_RATE(priv->cpll_hz, div) / 2; + else if (sel == EMMC_SEL_XIN24M) + return DIV_TO_RATE(OSC_HZ, div) / 2; + + return -ENOENT; +} + +static ulong rv1126_mmc_set_clk(struct rv1126_clk_priv *priv, ulong clk_id, + ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + u32 con_id; + + switch (clk_id) { + case HCLK_SDMMC: + case CLK_SDMMC: + con_id = 55; + break; + case HCLK_SDIO: + case CLK_SDIO: + con_id = 56; + break; + case HCLK_EMMC: + case CLK_EMMC: + con_id = 57; + break; + default: + return -ENOENT; + } + + /* Select clk_sdmmc/emmc source from GPLL by default */ + /* mmc clock defaulg div 2 internal, need provide double in cru */ + src_clk_div = DIV_ROUND_UP(priv->gpll_hz / 2, rate); + + if (src_clk_div > 127) { + /* use 24MHz source for 400KHz clock */ + src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, rate); + rk_clrsetreg(&cru->clksel_con[con_id], + EMMC_SEL_MASK | EMMC_DIV_MASK, + EMMC_SEL_XIN24M << EMMC_SEL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + } else { + rk_clrsetreg(&cru->clksel_con[con_id], + EMMC_SEL_MASK | EMMC_DIV_MASK, + EMMC_SEL_GPLL << EMMC_SEL_SHIFT | + (src_clk_div - 1) << EMMC_DIV_SHIFT); + } + + return rv1126_mmc_get_clk(priv, clk_id); +} + +static ulong rv1126_sfc_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[58]); + div = (con & SCLK_SFC_DIV_MASK) >> SCLK_SFC_DIV_SHIFT; + sel = (con & SCLK_SFC_SEL_MASK) >> SCLK_SFC_SEL_SHIFT; + if (sel == SCLK_SFC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == SCLK_SFC_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_sfc_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(&cru->clksel_con[58], + SCLK_SFC_SEL_MASK | SCLK_SFC_DIV_MASK, + SCLK_SFC_SEL_GPLL << SCLK_SFC_SEL_SHIFT | + (src_clk_div - 1) << SCLK_SFC_DIV_SHIFT); + + return rv1126_sfc_get_clk(priv); +} + +static ulong rv1126_nand_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[59]); + div = (con & CLK_NANDC_DIV_MASK) >> CLK_NANDC_DIV_SHIFT; + sel = (con & CLK_NANDC_SEL_MASK) >> CLK_NANDC_SEL_SHIFT; + if (sel == CLK_NANDC_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_NANDC_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_nand_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + rk_clrsetreg(&cru->clksel_con[59], + CLK_NANDC_SEL_MASK | CLK_NANDC_DIV_MASK, + CLK_NANDC_SEL_GPLL << CLK_NANDC_SEL_SHIFT | + (src_clk_div - 1) << CLK_NANDC_DIV_SHIFT); + + return rv1126_nand_get_clk(priv); +} + +static ulong rv1126_aclk_vop_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[45]); + div = (con & ACLK_PDVO_DIV_MASK) >> ACLK_PDVO_DIV_SHIFT; + sel = (con & ACLK_PDVO_SEL_MASK) >> ACLK_PDVO_SEL_SHIFT; + if (sel == ACLK_PDVO_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == ACLK_PDVO_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_aclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[45], + ACLK_PDVO_SEL_MASK | ACLK_PDVO_DIV_MASK, + ACLK_PDVO_SEL_GPLL << ACLK_PDVO_SEL_SHIFT | + (src_clk_div - 1) << ACLK_PDVO_DIV_SHIFT); + + return rv1126_aclk_vop_get_clk(priv); +} + +static ulong rv1126_dclk_vop_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[47]); + div = (con & DCLK_VOP_DIV_MASK) >> DCLK_VOP_DIV_SHIFT; + sel = (con & DCLK_VOP_SEL_MASK) >> DCLK_VOP_SEL_SHIFT; + if (sel == DCLK_VOP_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_VOP_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_vop_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + ulong pll_rate, now, best_rate = 0; + u32 i, div, best_div = 0, best_sel = 0; + + for (i = 0; i <= DCLK_VOP_SEL_CPLL; i++) { + switch (i) { + case DCLK_VOP_SEL_GPLL: + pll_rate = priv->gpll_hz; + break; + case DCLK_VOP_SEL_CPLL: + pll_rate = priv->cpll_hz; + break; + default: + printf("do not support this vop pll sel\n"); + return -EINVAL; + } + + div = DIV_ROUND_UP(pll_rate, rate); + if (div > 255) + continue; + now = pll_rate / div; + if (abs(rate - now) < abs(rate - best_rate)) { + best_rate = now; + best_div = div; + best_sel = i; + } + debug("pll_rate=%lu, best_rate=%lu, best_div=%u, best_sel=%u\n", + pll_rate, best_rate, best_div, best_sel); + } + + if (best_rate) { + rk_clrsetreg(&cru->clksel_con[47], + DCLK_VOP_SEL_MASK | DCLK_VOP_DIV_MASK, + best_sel << DCLK_VOP_SEL_SHIFT | + (best_div - 1) << DCLK_VOP_DIV_SHIFT); + } else { + printf("do not support this vop freq %lu\n", rate); + return -EINVAL; + } + + return rv1126_dclk_vop_get_clk(priv); +} + +static ulong rv1126_scr1_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[3]); + div = (con & CLK_SCR1_DIV_MASK) >> CLK_SCR1_DIV_SHIFT; + sel = (con & CLK_SCR1_SEL_MASK) >> CLK_SCR1_SEL_SHIFT; + if (sel == CLK_SCR1_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == CLK_SCR1_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_scr1_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[3], + CLK_SCR1_SEL_MASK | CLK_SCR1_DIV_MASK, + CLK_SCR1_SEL_GPLL << CLK_SCR1_SEL_SHIFT | + (src_clk_div - 1) << CLK_SCR1_DIV_SHIFT); + + return rv1126_scr1_get_clk(priv); +} + +static ulong rv1126_gmac_src_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[63]); + div = (con & CLK_GMAC_SRC_DIV_MASK) >> CLK_GMAC_SRC_DIV_SHIFT; + sel = (con & CLK_GMAC_SRC_SEL_MASK) >> CLK_GMAC_SRC_SEL_SHIFT; + if (sel == CLK_GMAC_SRC_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == CLK_GMAC_SRC_SEL_GPLL) + parent = priv->gpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_gmac_src_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[63], + CLK_GMAC_SRC_SEL_MASK | CLK_GMAC_SRC_DIV_MASK, + CLK_GMAC_SRC_SEL_CPLL << CLK_GMAC_SRC_SEL_SHIFT | + (src_clk_div - 1) << CLK_GMAC_SRC_DIV_SHIFT); + + return rv1126_gmac_src_get_clk(priv); +} + +static ulong rv1126_gmac_out_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[61]); + div = (con & CLK_GMAC_OUT_DIV_MASK) >> CLK_GMAC_OUT_DIV_SHIFT; + sel = (con & CLK_GMAC_OUT_SEL_MASK) >> CLK_GMAC_OUT_SEL_SHIFT; + if (sel == CLK_GMAC_OUT_SEL_CPLL) + parent = priv->cpll_hz; + else if (sel == CLK_GMAC_OUT_SEL_GPLL) + parent = priv->gpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_gmac_out_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + int src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->cpll_hz, rate); + assert(src_clk_div - 1 <= 31); + rk_clrsetreg(&cru->clksel_con[61], + CLK_GMAC_OUT_SEL_MASK | CLK_GMAC_OUT_DIV_MASK, + CLK_GMAC_OUT_SEL_CPLL << CLK_GMAC_OUT_SEL_SHIFT | + (src_clk_div - 1) << CLK_GMAC_OUT_DIV_SHIFT); + + return rv1126_gmac_out_get_clk(priv); +} + +static ulong rv1126_gmac_tx_rx_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + u32 con, sel, div_sel; + + con = readl(&cru->gmac_con); + sel = (con & GMAC_MODE_SEL_MASK) >> GMAC_MODE_SEL_SHIFT; + + if (sel == GMAC_RGMII_MODE) { + if (rate == 2500000) + div_sel = RGMII_CLK_DIV50; + else if (rate == 25000000) + div_sel = RGMII_CLK_DIV5; + else + div_sel = RGMII_CLK_DIV0; + rk_clrsetreg(&cru->gmac_con, RGMII_CLK_SEL_MASK, + div_sel << RGMII_CLK_SEL_SHIFT); + } else if (sel == GMAC_RMII_MODE) { + if (rate == 2500000) + div_sel = RMII_CLK_DIV20; + else + div_sel = RMII_CLK_DIV2; + rk_clrsetreg(&cru->gmac_con, RMII_CLK_SEL_MASK, + div_sel << RMII_CLK_SEL_SHIFT); + } + + return 0; +} + +static ulong rv1126_pclk_gmac_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, con, parent; + + parent = rv1126_pdphp_get_clk(priv, ACLK_PDPHP); + + con = readl(&cru->clksel_con[63]); + div = (con & PCLK_GMAC_DIV_MASK) >> PCLK_GMAC_DIV_SHIFT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_decom_get_clk(struct rv1126_clk_priv *priv) +{ + struct rv1126_cru *cru = priv->cru; + u32 div, sel, con, parent; + + con = readl(&cru->clksel_con[25]); + div = (con & DCLK_DECOM_DIV_MASK) >> DCLK_DECOM_DIV_SHIFT; + sel = (con & DCLK_DECOM_SEL_MASK) >> DCLK_DECOM_SEL_SHIFT; + if (sel == DCLK_DECOM_SEL_GPLL) + parent = priv->gpll_hz; + else if (sel == DCLK_DECOM_SEL_CPLL) + parent = priv->cpll_hz; + else + return -ENOENT; + + return DIV_TO_RATE(parent, div); +} + +static ulong rv1126_dclk_decom_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct rv1126_cru *cru = priv->cru; + u32 src_clk_div; + + src_clk_div = DIV_ROUND_UP(priv->gpll_hz, rate); + assert(src_clk_div - 1 <= 127); + rk_clrsetreg(&cru->clksel_con[25], + DCLK_DECOM_SEL_MASK | DCLK_DECOM_DIV_MASK, + DCLK_DECOM_SEL_GPLL << DCLK_DECOM_SEL_SHIFT | + (src_clk_div - 1) << DCLK_DECOM_DIV_SHIFT); + + return rv1126_dclk_decom_get_clk(priv); +} + +static ulong rv1126_clk_get_rate(struct clk *clk) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + ulong rate = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[APLL], priv->cru, + APLL); + break; + case PLL_CPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL); + break; + case PLL_HPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL); + break; + case PLL_DPLL: + rate = rockchip_pll_get_rate(&rv1126_pll_clks[DPLL], priv->cru, + DPLL); + break; + case HCLK_PDCORE_NIU: + rate = rv1126_pdcore_get_clk(priv); + break; + case ACLK_PDBUS: + case HCLK_PDBUS: + case PCLK_PDBUS: + case PCLK_WDT: + rate = rv1126_pdbus_get_clk(priv, clk->id); + break; + case ACLK_PDPHP: + case HCLK_PDPHP: + rate = rv1126_pdphp_get_clk(priv, clk->id); + break; + case HCLK_PDAUDIO: + rate = rv1126_pdaudio_get_clk(priv); + break; + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + rate = rv1126_i2c_get_clk(priv, clk->id); + break; + case CLK_SPI1: + rate = rv1126_spi_get_clk(priv); + break; + case CLK_PWM2: + rate = rv1126_pwm_get_clk(priv); + break; + case CLK_SARADC: + rate = rv1126_saradc_get_clk(priv); + break; + case CLK_CRYPTO_CORE: + case CLK_CRYPTO_PKA: + case ACLK_CRYPTO: + rate = rv1126_crypto_get_clk(priv, clk->id); + break; + case CLK_SDMMC: + case HCLK_SDMMC: + case CLK_SDIO: + case HCLK_SDIO: + case CLK_EMMC: + case HCLK_EMMC: + case SCLK_EMMC_SAMPLE: + rate = rv1126_mmc_get_clk(priv, clk->id); + break; + case SCLK_SFC: + rate = rv1126_sfc_get_clk(priv); + break; + case CLK_NANDC: + rate = rv1126_nand_get_clk(priv); + break; + case ACLK_PDVO: + case ACLK_VOP: + rate = rv1126_aclk_vop_get_clk(priv); + break; + case DCLK_VOP: + rate = rv1126_dclk_vop_get_clk(priv); + break; + case CLK_SCR1_CORE: + rate = rv1126_scr1_get_clk(priv); + break; + case CLK_GMAC_SRC: + rate = rv1126_gmac_src_get_clk(priv); + break; + case CLK_GMAC_ETHERNET_OUT: + rate = rv1126_gmac_out_get_clk(priv); + break; + case PCLK_GMAC: + rate = rv1126_pclk_gmac_get_clk(priv); + break; + case DCLK_DECOM: + rate = rv1126_dclk_decom_get_clk(priv); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return rate; +}; + +static ulong rv1126_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + ulong ret = 0; + + if (!priv->gpll_hz) { + printf("%s gpll=%lu\n", __func__, priv->gpll_hz); + return -ENOENT; + } + + switch (clk->id) { + case PLL_APLL: + case ARMCLK: + if (priv->armclk_hz) + rv1126_armclk_set_clk(priv, rate); + priv->armclk_hz = rate; + break; + case PLL_CPLL: + ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL, rate); + break; + case PLL_HPLL: + ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL, rate); + break; + case ACLK_PDBUS: + case HCLK_PDBUS: + case PCLK_PDBUS: + case PCLK_WDT: + ret = rv1126_pdbus_set_clk(priv, clk->id, rate); + break; + case ACLK_PDPHP: + case HCLK_PDPHP: + ret = rv1126_pdphp_set_clk(priv, clk->id, rate); + break; + case HCLK_PDCORE_NIU: + ret = rv1126_pdcore_set_clk(priv, rate); + break; + case HCLK_PDAUDIO: + ret = rv1126_pdaudio_set_clk(priv, rate); + break; + case CLK_I2C1: + case CLK_I2C3: + case CLK_I2C4: + case CLK_I2C5: + ret = rv1126_i2c_set_clk(priv, clk->id, rate); + break; + case CLK_SPI1: + ret = rv1126_spi_set_clk(priv, rate); + break; + case CLK_PWM2: + ret = rv1126_pwm_set_clk(priv, rate); + break; + case CLK_SARADC: + ret = rv1126_saradc_set_clk(priv, rate); + break; + case CLK_CRYPTO_CORE: + case CLK_CRYPTO_PKA: + case ACLK_CRYPTO: + ret = rv1126_crypto_set_clk(priv, clk->id, rate); + break; + case CLK_SDMMC: + case HCLK_SDMMC: + case CLK_SDIO: + case HCLK_SDIO: + case CLK_EMMC: + case HCLK_EMMC: + ret = rv1126_mmc_set_clk(priv, clk->id, rate); + break; + case SCLK_SFC: + ret = rv1126_sfc_set_clk(priv, rate); + break; + case CLK_NANDC: + ret = rv1126_nand_set_clk(priv, rate); + break; + case ACLK_PDVO: + case ACLK_VOP: + ret = rv1126_aclk_vop_set_clk(priv, rate); + break; + case DCLK_VOP: + ret = rv1126_dclk_vop_set_clk(priv, rate); + break; + case CLK_SCR1_CORE: + ret = rv1126_scr1_set_clk(priv, rate); + break; + case CLK_GMAC_SRC: + ret = rv1126_gmac_src_set_clk(priv, rate); + break; + case CLK_GMAC_ETHERNET_OUT: + ret = rv1126_gmac_out_set_clk(priv, rate); + break; + case CLK_GMAC_TX_RX: + ret = rv1126_gmac_tx_rx_set_clk(priv, rate); + break; + case DCLK_DECOM: + ret = rv1126_dclk_decom_set_clk(priv, rate); + break; + default: + debug("%s: Unsupported CLK#%ld\n", __func__, clk->id); + return -ENOENT; + } + + return ret; +}; + +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) +static int rv1126_gmac_src_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_grf *grf = priv->grf; + + if (parent->id == CLK_GMAC_SRC_M0) + rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, + GMAC_SRC_SEL_M0 << GMAC_SRC_SEL_SHIFT); + else if (parent->id == CLK_GMAC_SRC_M1) + rk_clrsetreg(&grf->iofunc_con1, GMAC_SRC_SEL_MASK, + GMAC_SRC_SEL_M1 << GMAC_SRC_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_src_m0_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == CLK_GMAC_DIV) + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, + GMAC_SRC_M0_SEL_INT << GMAC_SRC_M0_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M0_SEL_MASK, + GMAC_SRC_M0_SEL_EXT << GMAC_SRC_M0_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_src_m1_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == CLK_GMAC_DIV) + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, + GMAC_SRC_M1_SEL_INT << GMAC_SRC_M1_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_SRC_M1_SEL_MASK, + GMAC_SRC_M1_SEL_EXT << GMAC_SRC_M1_SEL_SHIFT); + + return 0; +} + +static int rv1126_gmac_tx_rx_set_parent(struct clk *clk, struct clk *parent) +{ + struct rv1126_clk_priv *priv = dev_get_priv(clk->dev); + struct rv1126_cru *cru = priv->cru; + + if (parent->id == RGMII_MODE_CLK) + rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, + GMAC_RGMII_MODE << GMAC_MODE_SEL_SHIFT); + else + rk_clrsetreg(&cru->gmac_con, GMAC_MODE_SEL_MASK, + GMAC_RMII_MODE << GMAC_MODE_SEL_SHIFT); + + return 0; +} + +static int rv1126_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case CLK_GMAC_SRC: + return rv1126_gmac_src_set_parent(clk, parent); + case CLK_GMAC_SRC_M0: + return rv1126_gmac_src_m0_set_parent(clk, parent); + case CLK_GMAC_SRC_M1: + return rv1126_gmac_src_m1_set_parent(clk, parent); + case CLK_GMAC_TX_RX: + return rv1126_gmac_tx_rx_set_parent(clk, parent); + default: + return -ENOENT; + } + + return 0; +} +#endif + +static struct clk_ops rv1126_clk_ops = { + .get_rate = rv1126_clk_get_rate, + .set_rate = rv1126_clk_set_rate, +#if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) + .set_parent = rv1126_clk_set_parent, +#endif +}; + +static ulong rv1126_gpll_set_rate(struct rv1126_clk_priv *priv, + struct rv1126_pmuclk_priv *pmu_priv, + ulong rate) +{ + ulong emmc_rate, sfc_rate, nandc_rate; + bool restore = false; + + if (priv->gpll_hz != OSC_HZ) { + emmc_rate = rv1126_mmc_get_clk(priv, CLK_EMMC); + sfc_rate = rv1126_sfc_get_clk(priv); + nandc_rate = rv1126_nand_get_clk(priv); + debug("%s emmc=%lu, sfc=%lu, nandc=%lu\n", __func__, + emmc_rate, sfc_rate, nandc_rate); + restore = true; + } + + /* + * the child div is big enough for gpll 1188MHz, + * even maskrom has change some clocks. + */ + if (rockchip_pll_set_rate(&rv1126_pll_clks[GPLL], + pmu_priv->pmucru, GPLL, rate)) + return -EINVAL; + pmu_priv->gpll_hz = rate; + priv->gpll_hz = rate; + + if (restore) { + rv1126_mmc_set_clk(priv, CLK_EMMC, emmc_rate); + rv1126_sfc_set_clk(priv, sfc_rate); + rv1126_nand_set_clk(priv, nandc_rate); + } + + return 0; +} + +static int rv1126_gpll_set_clk(struct rv1126_clk_priv *priv, ulong rate) +{ + struct udevice *pmucru_dev; + struct rv1126_pmuclk_priv *pmu_priv; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_pmucru), + &pmucru_dev); + if (ret) { + printf("%s: could not find pmucru device\n", __func__); + return ret; + } + pmu_priv = dev_get_priv(pmucru_dev); + priv->gpll_hz = pmu_priv->gpll_hz; + + if (rv1126_gpll_set_rate(priv, pmu_priv, rate)) { + printf("%s: failed to set gpll rate %lu\n", __func__, rate); + return -EINVAL; + } + + rv1126_pdpmu_set_pmuclk(pmu_priv, PCLK_PDPMU_HZ); + rv1126_rtc32k_set_pmuclk(pmu_priv, CLK_OSC0_DIV_HZ); + + return 0; +} + +static void rv1126_clk_init(struct rv1126_clk_priv *priv) +{ + int ret; + + priv->sync_kernel = false; + if (!priv->armclk_enter_hz) { + priv->armclk_enter_hz = + rockchip_pll_get_rate(&rv1126_pll_clks[APLL], + priv->cru, APLL); + priv->armclk_init_hz = priv->armclk_enter_hz; + } + + if (priv->armclk_init_hz != APLL_HZ) { + ret = rv1126_armclk_set_clk(priv, APLL_HZ); + if (!ret) + priv->armclk_init_hz = APLL_HZ; + } + if (priv->cpll_hz != CPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126_pll_clks[CPLL], priv->cru, + CPLL, CPLL_HZ); + if (!ret) + priv->cpll_hz = CPLL_HZ; + } + if (priv->hpll_hz != HPLL_HZ) { + ret = rockchip_pll_set_rate(&rv1126_pll_clks[HPLL], priv->cru, + HPLL, HPLL_HZ); + if (!ret) + priv->hpll_hz = HPLL_HZ; + } + if (priv->gpll_hz != GPLL_HZ) + rv1126_gpll_set_clk(priv, GPLL_HZ); + + rv1126_pdbus_set_clk(priv, ACLK_PDBUS, ACLK_PDBUS_HZ); + rv1126_pdbus_set_clk(priv, HCLK_PDBUS, HCLK_PDBUS_HZ); + rv1126_pdbus_set_clk(priv, PCLK_PDBUS, PCLK_PDBUS_HZ); + rv1126_pdphp_set_clk(priv, ACLK_PDPHP, ACLK_PDPHP_HZ); + rv1126_pdphp_set_clk(priv, HCLK_PDPHP, HCLK_PDPHP_HZ); + rv1126_pdcore_set_clk(priv, HCLK_PDCORE_HZ); + rv1126_pdaudio_set_clk(priv, HCLK_PDAUDIO_HZ); +} + +static int rv1126_clk_probe(struct udevice *dev) +{ + struct rv1126_clk_priv *priv = dev_get_priv(dev); + int ret; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + + rv1126_clk_init(priv); + + /* Process 'assigned-{clocks/clock-parents/clock-rates}' properties */ + ret = clk_set_defaults(dev, 1); + if (ret) + debug("%s clk_set_defaults failed %d\n", __func__, ret); + else + priv->sync_kernel = true; + + return 0; +} + +static int rv1126_clk_of_to_plat(struct udevice *dev) +{ + struct rv1126_clk_priv *priv = dev_get_priv(dev); + + priv->cru = dev_read_addr_ptr(dev); + + return 0; +} + +static int rv1126_clk_bind(struct udevice *dev) +{ + int ret; + struct udevice *sys_child; + struct sysreset_reg *priv; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset", + &sys_child); + if (ret) { + debug("Warning: No sysreset driver: ret=%d\n", ret); + } else { + priv = malloc(sizeof(struct sysreset_reg)); + priv->glb_srst_fst_value = offsetof(struct rv1126_cru, + glb_srst_fst); + priv->glb_srst_snd_value = offsetof(struct rv1126_cru, + glb_srst_snd); + dev_set_priv(sys_child, priv); + } + +#if CONFIG_IS_ENABLED(RESET_ROCKCHIP) + ret = offsetof(struct rv1126_cru, softrst_con[0]); + ret = rockchip_reset_bind(dev, ret, 15); + if (ret) + debug("Warning: software reset driver bind faile\n"); +#endif + return 0; +} + +static const struct udevice_id rv1126_clk_ids[] = { + { .compatible = "rockchip,rv1126-cru" }, + { } +}; + +U_BOOT_DRIVER(rockchip_rv1126_cru) = { + .name = "rockchip_rv1126_cru", + .id = UCLASS_CLK, + .of_match = rv1126_clk_ids, + .priv_auto = sizeof(struct rv1126_clk_priv), + .of_to_plat = rv1126_clk_of_to_plat, + .ops = &rv1126_clk_ops, + .bind = rv1126_clk_bind, + .probe = rv1126_clk_probe, +};
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang zhangqing@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
.../dt-bindings/power/rockchip,rv1126-power.h | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 include/dt-bindings/power/rockchip,rv1126-power.h
diff --git a/include/dt-bindings/power/rockchip,rv1126-power.h b/include/dt-bindings/power/rockchip,rv1126-power.h new file mode 100644 index 0000000000..38a68e000d --- /dev/null +++ b/include/dt-bindings/power/rockchip,rv1126-power.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef __DT_BINDINGS_POWER_RV1126_POWER_H__ +#define __DT_BINDINGS_POWER_RV1126_POWER_H__ + +/* VD_CORE */ +#define RV1126_PD_CPU_0 0 +#define RV1126_PD_CPU_1 1 +#define RV1126_PD_CPU_2 2 +#define RV1126_PD_CPU_3 3 +#define RV1126_PD_CORE_ALIVE 4 + +/* VD_PMU */ +#define RV1126_PD_PMU 5 +#define RV1126_PD_PMU_ALIVE 6 + +/* VD_NPU */ +#define RV1126_PD_NPU 7 + +/* VD_VEPU */ +#define RV1126_PD_VEPU 8 + +/* VD_LOGIC */ +#define RV1126_PD_VI 9 +#define RV1126_PD_VO 10 +#define RV1126_PD_ISPP 11 +#define RV1126_PD_VDPU 12 +#define RV1126_PD_CRYPTO 13 +#define RV1126_PD_DDR 14 +#define RV1126_PD_NVM 15 +#define RV1126_PD_SDIO 16 +#define RV1126_PD_USB 17 +#define RV1126_PD_LOGIC_ALIVE 18 + +#endif
Add GRF header for Rockchip RV1126.
Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
.../include/asm/arch-rockchip/grf_rv1126.h | 251 ++++++++++++++++++ 1 file changed, 251 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1126.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1126.h b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h new file mode 100644 index 0000000000..4e0488b91a --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1126.h @@ -0,0 +1,251 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd. + */ + +#ifndef _ASM_ARCH_GRF_RV1126_H +#define _ASM_ARCH_GRF_RV1126_H + +struct rv1126_grf { + unsigned int soc_con0; + unsigned int soc_con1; + unsigned int soc_con2; + unsigned int reserved0[1]; + unsigned int soc_status0; + unsigned int soc_status1; + unsigned int reserved1[2]; + unsigned int cpu_con0; + unsigned int cpu_con1; + unsigned int reserved2[2]; + unsigned int cpu_status0; + unsigned int reserved3[3]; + unsigned int noc_con0; + unsigned int noc_con1; + unsigned int noc_con2; + unsigned int noc_con3; + unsigned int usbhost_con0; + unsigned int usbhost_con1; + unsigned int usbhost_status0; + unsigned int usbotg_con0; + unsigned int usbotg_con1; + unsigned int usbotg_status0; + unsigned int usbotg_status1; + unsigned int usbotg_status2; + unsigned int mac_con0; + unsigned int mac_con1; + unsigned int mac_con2; + unsigned int reserved4[2]; + unsigned int mac_status0; + unsigned int mac_status1; + unsigned int mac_status2; + unsigned int mem_con0; + unsigned int mem_con1; + unsigned int mem_con2; + unsigned int mem_con3; + unsigned int reserved5[(0x100 - 0x09c) / 4 - 1]; + unsigned int tsadc_con0; + unsigned int reserved6[3]; + unsigned int chip_id; + unsigned int reserved7[(0x10000 - 0x110) / 4 - 1]; + unsigned int gpio0c_iomux_h; + unsigned int gpio0d_iomux_l; + unsigned int gpio0d_iomux_h; + unsigned int reserved8[1]; + unsigned int gpio1a_iomux_l; + unsigned int gpio1a_iomux_h; + unsigned int gpio1b_iomux_l; + unsigned int gpio1b_iomux_h; + unsigned int gpio1c_iomux_l; + unsigned int gpio1c_iomux_h; + unsigned int gpio1d_iomux_l; + unsigned int gpio1d_iomux_h; + unsigned int gpio2a_iomux_l; + unsigned int gpio2a_iomux_h; + unsigned int gpio2b_iomux_l; + unsigned int gpio2b_iomux_h; + unsigned int gpio2c_iomux_l; + unsigned int gpio2c_iomux_h; + unsigned int gpio2d_iomux_l; + unsigned int gpio2d_iomux_h; + unsigned int gpio3a_iomux_l; + unsigned int gpio3a_iomux_h; + unsigned int gpio3b_iomux_l; + unsigned int gpio3b_iomux_h; + unsigned int gpio3c_iomux_l; + unsigned int gpio3c_iomux_h; + unsigned int gpio3d_iomux_l; + unsigned int gpio3d_iomux_h; + unsigned int gpio4a_iomux_l; + unsigned int reserved9[3]; + unsigned int gpio0c_ds_h; + unsigned int gpio0d_ds_l; + unsigned int gpio0d_ds_h; + unsigned int reserved10[1]; + unsigned int gpio1a_ds_l; + unsigned int gpio1a_ds_h; + unsigned int gpio1b_ds_l; + unsigned int gpio1b_ds_h; + unsigned int gpio1c_ds_l; + unsigned int gpio1c_ds_h; + unsigned int gpio1d_ds_l; + unsigned int gpio1d_ds_h; + unsigned int gpio2a_ds_l; + unsigned int gpio2a_ds_h; + unsigned int gpio2b_ds_l; + unsigned int gpio2b_ds_h; + unsigned int gpio2c_ds_l; + unsigned int gpio2c_ds_h; + unsigned int gpio2d_ds_l; + unsigned int gpio2d_ds_h; + unsigned int gpio3a_ds_l; + unsigned int gpio3a_ds_h; + unsigned int gpio3b_ds_l; + unsigned int gpio3b_ds_h; + unsigned int gpio3c_ds_l; + unsigned int gpio3c_ds_h; + unsigned int gpio3d_ds_l; + unsigned int gpio3d_ds_h; + unsigned int gpio4a_ds_l; + unsigned int reserved12[3]; + unsigned int gpio0c_p_h; + unsigned int gpio0d_p; + unsigned int gpio1a_p; + unsigned int gpio1b_p; + unsigned int gpio1c_p; + unsigned int gpio1d_p; + unsigned int gpio2a_p; + unsigned int gpio2b_p; + unsigned int gpio2c_p; + unsigned int gpio2d_p; + unsigned int gpio3a_p; + unsigned int gpio3b_p; + unsigned int gpio3c_p; + unsigned int gpio3d_p; + unsigned int gpio4a_p; + unsigned int reserved13[1]; + unsigned int gpio0c_ie_h; + unsigned int gpio0d_ie; + unsigned int gpio1a_ie; + unsigned int gpio1b_ie; + unsigned int gpio1c_ie; + unsigned int gpio1d_ie; + unsigned int gpio2a_ie; + unsigned int gpio2b_ie; + unsigned int gpio2c_ie; + unsigned int gpio2d_ie; + unsigned int gpio3a_ie; + unsigned int gpio3b_ie; + unsigned int gpio3c_ie; + unsigned int gpio3d_ie; + unsigned int gpio4a_ie; + unsigned int reserved14[1]; + unsigned int gpio0c_smt_h; + unsigned int gpio0d_smt; + unsigned int gpio1a_smt; + unsigned int gpio1b_smt; + unsigned int gpio1c_smt; + unsigned int gpio1d_smt; + unsigned int gpio2a_smt; + unsigned int gpio2b_smt; + unsigned int gpio2c_smt; + unsigned int gpio2d_smt; + unsigned int gpio3a_smt; + unsigned int gpio3b_smt; + unsigned int gpio3c_smt; + unsigned int gpio3d_smt; + unsigned int gpio4a_smt; + unsigned int reserved15[(0x10200 - 0x101b8) / 4 - 1]; + unsigned int csiphy0_con; + unsigned int reserved16[1]; + unsigned int csiphy0_status; + unsigned int reserved17[1]; + unsigned int csiphy1_con; + unsigned int reserved18[1]; + unsigned int csiphy1_status; + unsigned int reserved19[1]; + unsigned int dsiphy_con; + unsigned int reserved20[3]; + unsigned int usbphy_con0; + unsigned int usbphy_con1; + unsigned int usbphy_con2; + unsigned int reserved21[3]; + unsigned int usbphy_status; + unsigned int reserved22[1]; + unsigned int cifio_con; + unsigned int sddetflt_con; + unsigned int uart2rx_low_con; + unsigned int reserved23[1]; + unsigned int iofunc_con0; + unsigned int iofunc_con1; + unsigned int iofunc_con2; + unsigned int iofunc_con3; + unsigned int usbphy0_cfg_con; + unsigned int usbphy0_cfg_addrin; + unsigned int usbphy0_cfg_addrout; + unsigned int usbphy0_cfg_dly_con; + unsigned int usbphy1_cfg_con; + unsigned int usbphy1_cfg_addrin; + unsigned int usbphy1_cfg_addrout; + unsigned int usbphy1_cfg_dly_con; + unsigned int reserved24[(0x10300 - 0x1028c) / 4 - 1]; + unsigned int usb_sig_detect_con; + unsigned int usb_sig_detect_status; + unsigned int usb_sig_detect_clr; + unsigned int reserved25[1]; + unsigned int usb_linestate_con; + unsigned int usb_disconnect_con; + unsigned int usb_bvalid_con; + unsigned int usb_id_con; +}; + +check_member(rv1126_grf, usb_id_con, 0x1031c); + +struct rv1126_pmugrf { + unsigned int gpio0a_iomux_l; + unsigned int gpio0a_iomux_h; + unsigned int gpio0b_iomux_l; + unsigned int gpio0b_iomux_h; + unsigned int gpio0c_iomux_l; + unsigned int reserved0[3]; + unsigned int gpio0a_ds_l; + unsigned int gpio0a_ds_h; + unsigned int gpio0b_ds_l; + unsigned int gpio0b_ds_h; + unsigned int gpio0c_ds_l; + unsigned int osc_ds; + unsigned int reserved1[2]; + unsigned int gpio0a_p; + unsigned int gpio0b_p; + unsigned int gpio0c_p_l; + unsigned int reserved2[1]; + unsigned int gpio0a_ie; + unsigned int gpio0b_ie; + unsigned int gpio0c_ie_l; + unsigned int reserved3[1]; + unsigned int gpio0a_smt; + unsigned int gpio0b_smt; + unsigned int gpio0c_smt_l; + unsigned int reserved4[(0x100 - 0x68) / 4 - 1]; + unsigned int soc_con[7]; + unsigned int reserved5[(0x140 - 0x118) / 4 - 1]; + unsigned int io_vsel; + unsigned int io_vret; + unsigned int reserved6[(0x180 - 0x144) / 4 - 1]; + unsigned int pmupvtm_clkdiv; + unsigned int reserved7[(0x200 - 0x180) / 4 - 1]; + unsigned int os_reg[12]; + unsigned int rstfunc_status; + unsigned int rstfunc_clr; + unsigned int reserved8[(0x380 - 0x234) / 4 - 1]; + unsigned int sd_detect_con; + unsigned int reserved9[3]; + unsigned int sd_detect_status; + unsigned int reserved10[3]; + unsigned int sd_detect_clr; + unsigned int reserved11[3]; + unsigned int sd_det_count; +}; + +check_member(rv1126_pmugrf, sd_det_count, 0x3b0); + +#endif
Add pinctrl definitions for Rockchip RV1126.
Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
arch/arm/dts/rv1126-pinctrl.dtsi | 212 +++++++++++++++++++++++++++++++ 1 file changed, 212 insertions(+) create mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/rv1126-pinctrl.dtsi new file mode 100644 index 0000000000..621b210e7e --- /dev/null +++ b/arch/arm/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,212 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <dt-bindings/pinctrl/rockchip.h> +#include "rockchip-pinconf.dtsi" + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +};
RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16 hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin jon.lin@rock-chips.com Signed-off-by: Sugar Zhang sugar.zhang@rock-chips.com Signed-off-by: Jagan Teki jagan@edgeble.ai --- Changes for v3: - collect Kever r-b Changes for v2: - none
arch/arm/dts/rv1126.dtsi | 439 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 439 insertions(+) create mode 100644 arch/arm/dts/rv1126.dtsi
diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi new file mode 100644 index 0000000000..867f17ab0e --- /dev/null +++ b/arch/arm/dts/rv1126.dtsi @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <dt-bindings/clock/rockchip,rv1126-cru.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/rockchip.h> +#include <dt-bindings/power/rockchip,rv1126-power.h> +#include <dt-bindings/soc/rockchip,boot-mode.h> + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = <RV1126_PD_NVM>; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = <RV1126_PD_SDIO>; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + dmas = <&dmac 15>, <&dmac 14>; + clock-names = "baudclk", "apb_pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: saradc@ff5e0000 { + compatible = "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer: timer@ff660000 { + compatible = "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio0@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio1@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio2@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio3@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio4@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi"
Rockchip RV1126 is a high-performance vision processor SoC for IPC/CVR, especially for AI related application.
Add arch core support for it.
Signed-off-by: Jagan Teki jagan@edgeble.ai Reviewed-by: Kever Yang kever.yang@rock-chips.com --- Changes for v3: - collect Kever r-b Changes for v2: - none
arch/arm/include/asm/arch-rv1126/boot0.h | 11 ++++ arch/arm/include/asm/arch-rv1126/gpio.h | 11 ++++ arch/arm/mach-rockchip/Kconfig | 46 ++++++++++++++ arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rv1126/Kconfig | 43 +++++++++++++ arch/arm/mach-rockchip/rv1126/Makefile | 13 ++++ arch/arm/mach-rockchip/rv1126/clk_rv1126.c | 33 ++++++++++ arch/arm/mach-rockchip/rv1126/rv1126.c | 63 +++++++++++++++++++ arch/arm/mach-rockchip/rv1126/syscon_rv1126.c | 47 ++++++++++++++ common/spl/Kconfig.tpl | 2 +- include/configs/rv1126_common.h | 42 +++++++++++++ 11 files changed, 311 insertions(+), 1 deletion(-) create mode 100644 arch/arm/include/asm/arch-rv1126/boot0.h create mode 100644 arch/arm/include/asm/arch-rv1126/gpio.h create mode 100644 arch/arm/mach-rockchip/rv1126/Kconfig create mode 100644 arch/arm/mach-rockchip/rv1126/Makefile create mode 100644 arch/arm/mach-rockchip/rv1126/clk_rv1126.c create mode 100644 arch/arm/mach-rockchip/rv1126/rv1126.c create mode 100644 arch/arm/mach-rockchip/rv1126/syscon_rv1126.c create mode 100644 include/configs/rv1126_common.h
diff --git a/arch/arm/include/asm/arch-rv1126/boot0.h b/arch/arm/include/asm/arch-rv1126/boot0.h new file mode 100644 index 0000000000..2e78b074ad --- /dev/null +++ b/arch/arm/include/asm/arch-rv1126/boot0.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_BOOT0_H__ +#define __ASM_ARCH_BOOT0_H__ + +#include <asm/arch-rockchip/boot0.h> + +#endif diff --git a/arch/arm/include/asm/arch-rv1126/gpio.h b/arch/arm/include/asm/arch-rv1126/gpio.h new file mode 100644 index 0000000000..eca79d5159 --- /dev/null +++ b/arch/arm/include/asm/arch-rv1126/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + */ + +#ifndef __ASM_ARCH_GPIO_H__ +#define __ASM_ARCH_GPIO_H__ + +#include <asm/arch-rockchip/gpio.h> + +#endif diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 69d51ff378..7c67084113 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -301,6 +301,51 @@ config ROCKCHIP_RV1108 The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7 and a DSP.
+config ROCKCHIP_RV1126 + bool "Support Rockchip RV1126" + select CPU_V7A + select SKIP_LOWLEVEL_INIT_ONLY + select TPL + select SUPPORT_TPL + select TPL_NEEDS_SEPARATE_STACK + select TPL_ROCKCHIP_BACK_TO_BROM + select SPL + select SUPPORT_SPL + select SPL_STACK_R + select CLK + select FIT + select PINCTRL + select RAM + select ROCKCHIP_SDRAM_COMMON + select REGMAP + select SYSCON + select DM_PMIC + select DM_REGULATOR_FIXED + select DM_RESET + select REGULATOR_RK8XX + select PMIC_RK8XX + select BOARD_LATE_INIT + imply ROCKCHIP_COMMON_BOARD + imply TPL_DM + imply TPL_LIBCOMMON_SUPPORT + imply TPL_LIBGENERIC_SUPPORT + imply TPL_OF_CONTROL + imply TPL_OF_PLATDATA + imply TPL_RAM + imply TPL_ROCKCHIP_COMMON_BOARD + imply TPL_SERIAL + imply SPL_CLK + imply SPL_DM + imply SPL_DRIVERS_MISC + imply SPL_LIBCOMMON_SUPPORT + imply SPL_LIBGENERIC_SUPPORT + imply SPL_OF_CONTROL + imply SPL_RAM + imply SPL_REGMAP + imply SPL_ROCKCHIP_COMMON_BOARD + imply SPL_SERIAL + imply SPL_SYSCON + config ROCKCHIP_USB_UART bool "Route uart output to usb pins" help @@ -446,4 +491,5 @@ source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" +source "arch/arm/mach-rockchip/rv1126/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 6c1c7b8a10..32138fa723 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -45,6 +45,7 @@ obj-$(CONFIG_ROCKCHIP_RK3368) += rk3368/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/ obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/ +obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
# Clear out SPL objects, in case this is a TPL build obj-spl-$(CONFIG_TPL_BUILD) = diff --git a/arch/arm/mach-rockchip/rv1126/Kconfig b/arch/arm/mach-rockchip/rv1126/Kconfig new file mode 100644 index 0000000000..4f5021b083 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/Kconfig @@ -0,0 +1,43 @@ +if ROCKCHIP_RV1126 + +config SOC_SPECIFIC_OPTIONS # dummy + def_bool y + select HAS_CUSTOM_SYS_INIT_SP_ADDR + +config ROCKCHIP_BOOT_MODE_REG + default 0xfe020200 + +config ROCKCHIP_STIMER_BASE + default 0xff670020 + +config SYS_SOC + default "rv1126" + +config CUSTOM_SYS_INIT_SP_ADDR + default 0x800000 + +config SPL_STACK + default 0x600000 + +config SPL_STACK_R_ADDR + default 0x800000 + +config TPL_LDSCRIPT + default "arch/arm/mach-rockchip/u-boot-tpl.lds" + +config TPL_STACK + default 0xff718000 + +config TPL_SYS_MALLOC_F_LEN + default 0x2000 + +config TPL_TEXT_BASE + default 0xff701000 + +config SYS_MALLOC_F_LEN + default 0x2000 + +config TEXT_BASE + default 0x600000 + +endif diff --git a/arch/arm/mach-rockchip/rv1126/Makefile b/arch/arm/mach-rockchip/rv1126/Makefile new file mode 100644 index 0000000000..b2875633db --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/Makefile @@ -0,0 +1,13 @@ +# +# (C) Copyright 2019 Rockchip Electronics Co., Ltd +# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += rv1126.o + +ifndef CONFIG_TPL_BUILD +obj-y += clk_rv1126.o +obj-y += syscon_rv1126.o +endif diff --git a/arch/arm/mach-rockchip/rv1126/clk_rv1126.c b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c new file mode 100644 index 0000000000..bd8902718f --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/clk_rv1126.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rv1126.h> +#include <linux/err.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_DRIVER_GET(rockchip_rv1126_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rv1126_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c b/arch/arm/mach-rockchip/rv1126/rv1126.c new file mode 100644 index 0000000000..91554c98b6 --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/rv1126.c @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch-rockchip/bootrom.h> +#include <asm/arch-rockchip/hardware.h> +#include <asm/arch-rockchip/grf_rv1126.h> + +#define GRF_BASE 0xFE000000 + +const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { + [BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000", + [BROM_BOOTSOURCE_SD] = "/mmc@ffc60000", +}; + +/* GRF_GPIO3A_IOMUX_L */ +enum { + GPIO3A3_SHIFT = 12, + GPIO3A3_MASK = GENMASK(14, 12), + GPIO3A3_GPIO = 0, + GPIO3A3_UART2_RX_M1, + GPIO3A3_A7_JTAG_TMS_M1, + + GPIO3A2_SHIFT = 8, + GPIO3A2_MASK = GENMASK(10, 8), + GPIO3A2_GPIO = 0, + GPIO3A2_UART2_TX_M1, + GPIO3A2_A7_JTAG_TCK_M1, +}; + +/* GRF_IOFUNC_CON2 */ +enum { + UART2_IO_SEL_SHIFT = 8, + UART2_IO_SEL_MASK = GENMASK(8, 8), + UART2_IO_SEL_M0 = 0, + UART2_IO_SEL_M1, +}; + +void board_debug_uart_init(void) +{ + static struct rv1126_grf * const grf = (void *)GRF_BASE; + + /* Enable early UART2 channel m1 on the rv1126 */ + rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK, + UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT); + + /* Switch iomux */ + rk_clrsetreg(&grf->gpio3a_iomux_l, + GPIO3A3_MASK | GPIO3A2_MASK, + GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT | + GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT); +} + +#ifndef CONFIG_TPL_BUILD +int arch_cpu_init(void) +{ + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c new file mode 100644 index 0000000000..599ea66e3d --- /dev/null +++ b/arch/arm/mach-rockchip/rv1126/syscon_rv1126.c @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#include <common.h> +#include <dm.h> +#include <log.h> +#include <syscon.h> +#include <asm/arch-rockchip/clock.h> + +static const struct udevice_id rv1126_syscon_ids[] = { + { .compatible = "rockchip,rv1126-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rv1126-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF }, + { } +}; + +U_BOOT_DRIVER(syscon_rv1126) = { + .name = "rv1126_syscon", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rv1126_syscon_bind_of_plat(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rv1126_pmu) = { + .name = "rockchip_rv1126_pmu", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids, + .bind = rv1126_syscon_bind_of_plat, +}; + +U_BOOT_DRIVER(rockchip_rv1126_pmugrf) = { + .name = "rockchip_rv1126_pmugrf", + .id = UCLASS_SYSCON, + .of_match = rv1126_syscon_ids + 1, + .bind = rv1126_syscon_bind_of_plat, +}; +#endif diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl index e314b793a2..1874f9db4f 100644 --- a/common/spl/Kconfig.tpl +++ b/common/spl/Kconfig.tpl @@ -132,7 +132,7 @@ config TPL_TEXT_BASE config TPL_MAX_SIZE hex "Maximum size (in bytes) for the TPL stage" default 0x2e000 if ROCKCHIP_RK3399 - default 0x8000 if ROCKCHIP_RK3288 + default 0x8000 if ROCKCHIP_RK3288 || ROCKCHIP_RV1126 default 0x7000 if ROCKCHIP_RK322X || ROCKCHIP_RK3328 || ROCKCHIP_RK3368 default 0x2800 if ROCKCHIP_PX30 default 0x0 diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_common.h new file mode 100644 index 0000000000..6ab5b2ce5f --- /dev/null +++ b/include/configs/rv1126_common.h @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 Rockchip Electronics Co., Ltd + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +#ifndef __CONFIG_RV1126_COMMON_H +#define __CONFIG_RV1126_COMMON_H + +#include "rockchip-common.h" + +#define CONFIG_SYS_HZ_CLOCK 24000000 + +#define CONFIG_IRAM_BASE 0xff700000 + +#define GICD_BASE 0xfeff1000 +#define GICC_BASE 0xfeff2000 + +#define CONFIG_SYS_SDRAM_BASE 0 +#define SDRAM_MAX_SIZE 0xfd000000 + +#define CONFIG_SYS_MONITOR_LEN (600 * 1024) + +/* memory size > 128MB */ +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x00000000\0" \ + "pxefile_addr_r=0x00100000\0" \ + "fdt_addr_r=0x08300000\0" \ + "kernel_addr_r=0x02008000\0" \ + "ramdisk_addr_r=0x0a200000\0" + +#include <config_distro_bootcmd.h> +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x0fffffff\0" \ + "initrd_high=0x0fffffff\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* __CONFIG_RV1126_COMMON_H */
participants (1)
-
Jagan Teki