From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI.

https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die)

The full version can be found in the following links (registration required). https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Sempe... https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-M...

S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable sector architecture. By default, the 512Mb and 1Gb, single-die package parts are configured to non-uniform that 4KB sectors overlaid on bottom address. To support this, an erase hook makes overlaid sectors appear as uniform sectors. The 2Gb, dual-die package parts are configured to uniform by default.

Tested on Xilinx Zynq-7000 FPGA board.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - Remove USE_CLSR flag from S25HL02GT and S25HS02GT - Remove comment block and update commit description

Changes in v5: - Remove 256Mb and 4Gb parts

drivers/mtd/spi/spi-nor-ids.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 59f2d3e4d6..1af1c86486 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -225,6 +225,22 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_S28HS512T { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, #endif

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

Some of Spansion/Cypress chips support Read/Write Any Register commands. These commands are mainly used to write volatile registers and access to the registers in second and subsequent die for multi-die package parts.

The Read Any Register instruction (65h) is followed by register address and dummy cycles, then the selected register byte is returned.

The Write Any Register instruction (71h) is followed by register address and register byte to write.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - No change

Changes in v5: - Remove unused defines from spi-nor.h

drivers/mtd/spi/spi-nor-core.c | 25 +++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 27 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 8dd44c0f1e..9e85f7d73e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -315,6 +315,31 @@ static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) return spi_nor_read_write_reg(nor, &op, buf); }

+#ifdef CONFIG_SPI_FLASH_SPANSION +static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, + u8 *val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_DUMMY(dummy / 8, 1), + SPI_MEM_OP_DATA_IN(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, val); +} + +static int spansion_write_any_reg(struct spi_nor *nor, u32 addr, u8 val) +{ + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WRAR, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_DATA_OUT(1, NULL, 1)); + + return spi_nor_read_write_reg(nor, &op, &val); +} +#endif + static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, u_char *buf) { diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 95ea6eb27a..5bb06882ea 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,8 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_RDAR 0x65 /* Read any register */ +#define SPINOR_OP_WRAR 0x71 /* Write any register */

/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

Some of Spansion/Cypress chips support volatile version of configuration registers and it is recommended to update volatile registers in the field application due to a risk of the non-volatile registers corruption by power interrupt. This patch adds a function to set Quad Enable bit in CFR1 volatile.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - Define spansion_quad_enable_volatile() under CONFIG_SPI_FLASH_SPANSION

Changes in v7: - No change

Changes in v6: - No change

Changes in v5: - Fix register address calculation, 'base | offset' -> 'base + offset'

drivers/mtd/spi/spi-nor-core.c | 55 ++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 56 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9e85f7d73e..2b72d65b0a 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1711,6 +1711,61 @@ static int macronix_quad_enable(struct spi_nor *nor) } #endif

+#ifdef CONFIG_SPI_FLASH_SPANSION +/** + * spansion_quad_enable_volatile() - enable Quad I/O mode in volatile register. + * @nor: pointer to a 'struct spi_nor' + * @addr_base: base address of register (can be >0 in multi-die parts) + * @dummy: number of dummy cycles for register read + * + * It is recommended to update volatile registers in the field application due + * to a risk of the non-volatile registers corruption by power interrupt. This + * function sets Quad Enable bit in CFR1 volatile. + * + * Return: 0 on success, -errno otherwise. + */ +static int spansion_quad_enable_volatile(struct spi_nor *nor, u32 addr_base, + u8 dummy) +{ + u32 addr = addr_base + SPINOR_REG_ADDR_CFR1V; + + u8 cr; + int ret; + + /* Check current Quad Enable bit value. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret < 0) { + dev_dbg(nor->dev, + "error while reading configuration register\n"); + return -EINVAL; + } + + if (cr & CR_QUAD_EN_SPAN) + return 0; + + cr |= CR_QUAD_EN_SPAN; + + write_enable(nor); + + ret = spansion_write_any_reg(nor, addr, cr); + + if (ret < 0) { + dev_dbg(nor->dev, + "error while writing configuration register\n"); + return -EINVAL; + } + + /* Read back and check it. */ + ret = spansion_read_any_reg(nor, addr, dummy, &cr); + if (ret || !(cr & CR_QUAD_EN_SPAN)) { + dev_dbg(nor->dev, "Spansion Quad bit not set\n"); + return -EINVAL; + } + + return 0; +} +#endif + #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) /* * Write status Register and configuration register with 2 bytes diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 5bb06882ea..81df05fe84 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_CFR1V 0x00800002

/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

For dual/quad die package devices from Spansion/Cypress, the device's status needs to be checked by reading status registers in all dies, by using Read Any Register command. To support this, a Flash specific hook that can overwrite the legacy status check is needed.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - Rebase and fix commit description

Changes in v5: - Move spansion_sr_ready() to different patch - Move original code in spi_nor_ready() to newly created spi_nor_default_ready()

drivers/mtd/spi/spi-nor-core.c | 10 +++++++++- include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 2b72d65b0a..d953c7e44f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -713,7 +713,7 @@ static int spi_nor_fsr_ready(struct spi_nor *nor) return fsr & FSR_READY; }

-static int spi_nor_ready(struct spi_nor *nor) +static int spi_nor_default_ready(struct spi_nor *nor) { int sr, fsr;

@@ -726,6 +726,14 @@ static int spi_nor_ready(struct spi_nor *nor) return sr && fsr; }

+static int spi_nor_ready(struct spi_nor *nor) +{ + if (nor->ready) + return nor->ready(nor); + + return spi_nor_default_ready(nor); +} + /* * Service routine to read status register until ready, or timeout occurs. * Returns non-zero if error. diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 81df05fe84..e579ff2c7e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -504,6 +504,7 @@ struct spi_flash { * completely locked * @quad_enable: [FLASH-SPECIFIC] enables SPI NOR quad mode * @octal_dtr_enable: [FLASH-SPECIFIC] enables SPI NOR octal DTR mode. + * @ready: [FLASH-SPECIFIC] check if the flash is ready * @priv: the private data */ struct spi_nor { @@ -552,6 +553,7 @@ struct spi_nor { int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len); int (*quad_enable)(struct spi_nor *nor); int (*octal_dtr_enable)(struct spi_nor *nor); + int (*ready)(struct spi_nor *nor);

void *priv; /* Compatibility for spi_flash, remove once sf layer is merged with mtd */

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

The spansion_sr_ready() reads status register 1 by Read Any Register commnad. This function is called from Flash specific hook with die address and dummy cycles to support multi-die package parts from Spansion/Cypress.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com Reviewed-by: Pratyush Yadav p.yadav@ti.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - No change

Changes in v5: - New in v5, separated from another patch

drivers/mtd/spi/spi-nor-core.c | 29 +++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 30 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index d953c7e44f..7f1ed1bb36 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -669,6 +669,35 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, } }

+#ifdef CONFIG_SPI_FLASH_SPANSION +/* + * Read status register 1 by using Read Any Register command to support multi + * die package parts. + */ +static int spansion_sr_ready(struct spi_nor *nor, u32 addr_base, u8 dummy) +{ + u32 reg_addr = addr_base + SPINOR_REG_ADDR_STR1V; + u8 sr; + int ret; + + ret = spansion_read_any_reg(nor, reg_addr, dummy, &sr); + if (ret < 0) + return ret; + + if (sr & (SR_E_ERR | SR_P_ERR)) { + if (sr & SR_E_ERR) + dev_dbg(nor->dev, "Erase Error occurred\n"); + else + dev_dbg(nor->dev, "Programming Error occurred\n"); + + nor->write_reg(nor, SPINOR_OP_CLSR, NULL, 0); + return -EIO; + } + + return !(sr & SR_WIP); +} +#endif + static int spi_nor_sr_ready(struct spi_nor *nor) { int sr = read_sr(nor); diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index e579ff2c7e..b9d66458a0 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -125,6 +125,7 @@ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ +#define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002

/* Used for Micron flashes only. */

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.

Cypress chips support B8h to disable 4-byte addressing mode instead of SPINOR_OP_EX4B(E9h).

This patch defines new opcode and updates set_4byte() to support enable/disable 4-byte addressing mode for Cypress chips.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - Define SPINOR_OP_EX4B_CYPRESS and use it

drivers/mtd/spi/spi-nor-core.c | 3 +++ include/linux/mtd/spi-nor.h | 1 + 2 files changed, 4 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 7f1ed1bb36..94dfa97110 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -662,6 +662,9 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info, }

return status; + case SNOR_MFR_CYPRESS: + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS; + return nor->write_reg(nor, cmd, NULL, 0); default: /* Spansion style */ nor->cmd_buf[0] = enable << 7; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index b9d66458a0..6df82bde94 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -123,6 +123,7 @@ #define SPINOR_OP_BRWR 0x17 /* Bank register write */ #define SPINOR_OP_BRRD 0x16 /* Bank register read */ #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */ +#define SPINOR_OP_EX4B_CYPRESS 0xB8 /* Exit 4-byte mode */ #define SPINOR_OP_RDAR 0x65 /* Read any register */ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

The nor->ready() and spansion_sr_ready() introduced earlier in this series are used for multi-die package parts.

The nor->quad_enable() sets the volatile QE bit on each die.

The nor->erase() is hooked if the device is not configured to uniform sectors, assuming it has 32 x 4KB sectors overlaid on bottom address. Other configurations, top and split, are not supported at this point. Will submit additional patches to support it as needed.

The post_bfpt/sfdp() fixes the params wrongly advertised in SFDP.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - Fix return type of s25hx_t_erase_non_uniform() to 'int'

Changes in v6: - Remove mtd.writesize fixup - Check if uniform sector is selected in multi-die package parts - Fix some other minor issues

Changes in v5: - Add s25hx_t_erase_non_uniform() - Change mtd.writesize and mtd.flags in s25hx_t_setup() - Fix page size and erase size issues in s25hx_t_post_bfpt_fixup()

drivers/mtd/spi/spi-nor-core.c | 144 ++++++++++++++++++++++++++++++++- include/linux/mtd/spi-nor.h | 3 + 2 files changed, 146 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 94dfa97110..99e2f16349 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -952,7 +952,7 @@ erase_err: return ret; }

-#ifdef CONFIG_SPI_FLASH_S28HS512T +#ifdef CONFIG_SPI_FLASH_SPANSION /** * spansion_erase_non_uniform() - erase non-uniform sectors for Spansion/Cypress * chips @@ -3085,6 +3085,134 @@ static int spi_nor_setup(struct spi_nor *nor, const struct flash_info *info, return nor->setup(nor, info, params); }

+#ifdef CONFIG_SPI_FLASH_SPANSION +static int s25hx_t_mdp_ready(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_sr_ready(nor, addr, 0); + if (!ret) + return ret; + } + + return 1; +} + +static int s25hx_t_quad_enable(struct spi_nor *nor) +{ + u32 addr; + int ret; + + for (addr = 0; addr < nor->mtd.size; addr += SZ_128M) { + ret = spansion_quad_enable_volatile(nor, addr, 0); + if (ret) + return ret; + } + + return 0; +} + +static int s25hx_t_erase_non_uniform(struct spi_nor *nor, loff_t addr) +{ + /* Support 32 x 4KB sectors at bottom */ + return spansion_erase_non_uniform(nor, addr, SPINOR_OP_BE_4K_4B, 0, + SZ_128K); +} + +static int s25hx_t_setup(struct spi_nor *nor, const struct flash_info *info, + const struct spi_nor_flash_parameter *params) +{ + int ret; + u8 cfr3v; + +#ifdef CONFIG_SPI_FLASH_BAR + return -ENOTSUPP; /* Bank Address Register is not supported */ +#endif + /* + * Read CFR3V to check if uniform sector is selected. If not, assign an + * erase hook that supports non-uniform erase. + */ + ret = spansion_read_any_reg(nor, SPINOR_REG_ADDR_CFR3V, 0, &cfr3v); + if (ret) + return ret; + if (!(cfr3v & CFR3V_UNHYSA)) + nor->erase = s25hx_t_erase_non_uniform; + + /* + * For the multi-die package parts, the ready() hook is needed to check + * all dies' status via read any register. + */ + if (nor->mtd.size > SZ_128M) + nor->ready = s25hx_t_mdp_ready; + + return spi_nor_default_setup(nor, info, params); +} + +static void s25hx_t_default_init(struct spi_nor *nor) +{ + nor->setup = s25hx_t_setup; +} + +static int s25hx_t_post_bfpt_fixup(struct spi_nor *nor, + const struct sfdp_parameter_header *header, + const struct sfdp_bfpt *bfpt, + struct spi_nor_flash_parameter *params) +{ + int ret; + u32 addr; + u8 cfr3v; + + /* erase size in case it is set to 4K from BFPT */ + nor->erase_opcode = SPINOR_OP_SE_4B; + nor->mtd.erasesize = nor->info->sector_size; + + ret = set_4byte(nor, nor->info, 1); + if (ret) + return ret; + nor->addr_width = 4; + + /* + * The page_size is set to 512B from BFPT, but it actually depends on + * the configuration register. Look up the CFR3V and determine the + * page_size. For multi-die package parts, use 512B only when the all + * dies are configured to 512B buffer. + */ + for (addr = 0; addr < params->size; addr += SZ_128M) { + ret = spansion_read_any_reg(nor, addr + SPINOR_REG_ADDR_CFR3V, + 0, &cfr3v); + if (ret) + return ret; + + if (!(cfr3v & CFR3V_PGMBUF)) { + params->page_size = 256; + return 0; + } + } + params->page_size = 512; + + return 0; +} + +static void s25hx_t_post_sfdp_fixup(struct spi_nor *nor, + struct spi_nor_flash_parameter *params) +{ + /* READ_FAST_4B (0Ch) requires mode cycles*/ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; + /* PP_1_1_4 is not supported */ + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* Use volatile register to enable quad */ + params->quad_enable = s25hx_t_quad_enable; +} + +static struct spi_nor_fixups s25hx_t_fixups = { + .default_init = s25hx_t_default_init, + .post_bfpt = s25hx_t_post_bfpt_fixup, + .post_sfdp = s25hx_t_post_sfdp_fixup, +}; +#endif + #ifdef CONFIG_SPI_FLASH_S28HS512T /** * spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes. @@ -3493,6 +3621,20 @@ int spi_nor_remove(struct spi_nor *nor)

void spi_nor_set_fixups(struct spi_nor *nor) { +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(nor->info) == SNOR_MFR_CYPRESS) { + switch (nor->info->id[1]) { + case 0x2a: /* S25HL (QSPI, 3.3V) */ + case 0x2b: /* S25HS (QSPI, 1.8V) */ + nor->fixups = &s25hx_t_fixups; + break; + + default: + break; + } + } +#endif + #ifdef CONFIG_SPI_FLASH_S28HS512T if (!strcmp(nor->info->name, "s28hs512t")) nor->fixups = &s28hs512t_fixups; diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 6df82bde94..7ddc4ba2bf 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -128,6 +128,9 @@ #define SPINOR_OP_WRAR 0x71 /* Write any register */ #define SPINOR_REG_ADDR_STR1V 0x00800000 #define SPINOR_REG_ADDR_CFR1V 0x00800002 +#define SPINOR_REG_ADDR_CFR3V 0x00800004 +#define CFR3V_UNHYSA BIT(3) /* Uniform sectors or not */ +#define CFR3V_PGMBUF BIT(4) /* Program buffer size */

/* Used for Micron flashes only. */ #define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */

From: Takahiro Kuwano Takahiro.Kuwano@infineon.com

Fixes mode clocks for SPINOR_OP_READ_FAST_4B in tiny.

Signed-off-by: Takahiro Kuwano Takahiro.Kuwano@infineon.com --- Changes in v9: - Rebase on top of u-boot-spi/next

Changes in v8: - No change

Changes in v7: - No change

Changes in v6: - Remove spansion_quad_enable_volatile() per comment in https://patchwork.ozlabs.org/project/uboot/patch/a5c3cf1353d9a621379e2fcfefc...

Changes in v5: - Add a comment about Flash models and respective IDs

drivers/mtd/spi/spi-nor-tiny.c | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/drivers/mtd/spi/spi-nor-tiny.c b/drivers/mtd/spi/spi-nor-tiny.c index 70061f1a61..68152ce3b4 100644 --- a/drivers/mtd/spi/spi-nor-tiny.c +++ b/drivers/mtd/spi/spi-nor-tiny.c @@ -583,6 +583,12 @@ static int spi_nor_init_params(struct spi_nor *nor, spi_nor_set_read_settings(&params->reads[SNOR_CMD_READ_FAST], 0, 8, SPINOR_OP_READ_FAST, SNOR_PROTO_1_1_1); +#ifdef CONFIG_SPI_FLASH_SPANSION + if (JEDEC_MFR(info) == SNOR_MFR_CYPRESS && + (info->id[1] == 0x2a || info->id[1] == 0x2b)) + /* 0x2a: S25HL (QSPI, 3.3V), 0x2b: S25HS (QSPI, 1.8V) */ + params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8; +#endif }

if (info->flags & SPI_NOR_QUAD_READ) {