From: Keerthy j-keerthy@ti.com

The K3 AM65x family of SoCs have the next generation of the PRU-ICSS processor subsystem, commonly referred to as ICSSG. Each ICSSG processor subsystem on AM65x SR1.0 contains two primary PRU cores and two new auxiliary PRU cores called RTUs. The AM65x SR2.0 SoCs have a revised ICSSG IP that is based off the subsequent IP revision used on J721E SoCs. This IP instance has two new custom auxiliary PRU cores called Transmit PRUs (Tx_PRUs) in addition to the existing PRUs and RTUs.

Each RTU and Tx_PRU cores have their own dedicated IRAM (smaller than a PRU), Control and debug feature sets, but is different in terms of sub-modules integrated around it and does not have the full capabilities associated with a PRU core. The RTU core is typically used to aid a PRU core in accelerating data transfers, while the Tx_PRU cores is normally used to control the TX L2 FIFO if enabled in Ethernet applications. Both can also be used to run independent applications. The RTU and Tx_PRU cores though share the same Data RAMs as the PRU cores, so the memories have to be partitioned carefully between different applications. The new cores also support a new sub-module called Task Manager to support two different context thread executions. The driver currently supports the AM65xx SoC

Signed-off-by: Keerthy j-keerthy@ti.com Signed-off-by: Suman Anna s-anna@ti.com Signed-off-by: Murali Karicheri m-karicheri2@ti.com Signed-off-by: Roger Quadros rogerq@ti.com Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- drivers/remoteproc/Kconfig | 11 + drivers/remoteproc/Makefile | 1 + drivers/remoteproc/pru_rproc.c | 461 +++++++++++++++++++++++++++++++++ 3 files changed, 473 insertions(+) create mode 100644 drivers/remoteproc/pru_rproc.c

diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig index 7c2e4804b5..24e536463b 100644 --- a/drivers/remoteproc/Kconfig +++ b/drivers/remoteproc/Kconfig @@ -81,4 +81,15 @@ config REMOTEPROC_TI_POWER help Say 'y' here to add support for TI power processors such as those found on certain TI keystone and OMAP generation SoCs. + +config REMOTEPROC_TI_PRU + bool "Support for TI's K3 based PRU remoteproc driver" + select REMOTEPROC + depends on DM + depends on TI_PRUSS + depends on ARCH_K3 + depends on OF_CONTROL + help + Say 'y' here to add support for TI' K3 remoteproc driver. + endmenu diff --git a/drivers/remoteproc/Makefile b/drivers/remoteproc/Makefile index 69ae7bd1e8..f0e83451d6 100644 --- a/drivers/remoteproc/Makefile +++ b/drivers/remoteproc/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_REMOTEPROC_TI_K3_ARM64) += ti_k3_arm64_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_DSP) += ti_k3_dsp_rproc.o obj-$(CONFIG_REMOTEPROC_TI_K3_R5F) += ti_k3_r5f_rproc.o obj-$(CONFIG_REMOTEPROC_TI_POWER) += ti_power_proc.o +obj-$(CONFIG_REMOTEPROC_TI_PRU) += pru_rproc.o diff --git a/drivers/remoteproc/pru_rproc.c b/drivers/remoteproc/pru_rproc.c new file mode 100644 index 0000000000..924070a76b --- /dev/null +++ b/drivers/remoteproc/pru_rproc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PRU-RTU remoteproc driver for various SoCs + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + * Keerthy j-keerthy@ti.com + */ + +#include <common.h> +#include <dm.h> +#include <elf.h> +#include <dm/of_access.h> +#include <remoteproc.h> +#include <errno.h> +#include <clk.h> +#include <reset.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <power-domain.h> +#include <linux/pruss_driver.h> +#include <dm/device_compat.h> + +/* PRU_ICSS_PRU_CTRL registers */ +#define PRU_CTRL_CTRL 0x0000 +#define PRU_CTRL_STS 0x0004 +#define PRU_CTRL_WAKEUP_EN 0x0008 +#define PRU_CTRL_CYCLE 0x000C +#define PRU_CTRL_STALL 0x0010 +#define PRU_CTRL_CTBIR0 0x0020 +#define PRU_CTRL_CTBIR1 0x0024 +#define PRU_CTRL_CTPPR0 0x0028 +#define PRU_CTRL_CTPPR1 0x002C + +/* CTRL register bit-fields */ +#define CTRL_CTRL_SOFT_RST_N BIT(0) +#define CTRL_CTRL_EN BIT(1) +#define CTRL_CTRL_SLEEPING BIT(2) +#define CTRL_CTRL_CTR_EN BIT(3) +#define CTRL_CTRL_SINGLE_STEP BIT(8) +#define CTRL_CTRL_RUNSTATE BIT(15) + +#define RPROC_FLAGS_SHIFT 16 +#define RPROC_FLAGS_NONE 0 +#define RPROC_FLAGS_ELF_PHDR BIT(0 + RPROC_FLAGS_SHIFT) +#define RPROC_FLAGS_ELF_SHDR BIT(1 + RPROC_FLAGS_SHIFT) + +/** + * enum pru_mem - PRU core memory range identifiers + */ +enum pru_mem { + PRU_MEM_IRAM = 0, + PRU_MEM_CTRL, + PRU_MEM_DEBUG, + PRU_MEM_MAX, +}; + +struct pru_privdata { + phys_addr_t pru_iram; + phys_addr_t pru_ctrl; + phys_addr_t pru_debug; + fdt_size_t pru_iramsz; + fdt_size_t pru_ctrlsz; + fdt_size_t pru_debugsz; + const char *fw_name; + u32 iram_da; + u32 pdram_da; + u32 sdram_da; + u32 shrdram_da; + u32 bootaddr; + int id; + struct pruss *prusspriv; +}; + +static inline u32 pru_control_read_reg(struct pru_privdata *pru, unsigned int reg) +{ + return readl(pru->pru_ctrl + reg); +} + +static inline +void pru_control_write_reg(struct pru_privdata *pru, unsigned int reg, u32 val) +{ + writel(val, pru->pru_ctrl + reg); +} + +static inline +void pru_control_set_reg(struct pru_privdata *pru, unsigned int reg, + u32 mask, u32 set) +{ + u32 val; + + val = pru_control_read_reg(pru, reg); + val &= ~mask; + val |= (set & mask); + pru_control_write_reg(pru, reg, val); +} + +/** + * pru_rproc_set_ctable() - set the constant table index for the PRU + * @rproc: the rproc instance of the PRU + * @c: constant table index to set + * @addr: physical address to set it to + */ +static int pru_rproc_set_ctable(struct pru_privdata *pru, enum pru_ctable_idx c, u32 addr) +{ + unsigned int reg; + u32 mask, set; + u16 idx; + u16 idx_mask; + + /* pointer is 16 bit and index is 8-bit so mask out the rest */ + idx_mask = (c >= PRU_C28) ? 0xFFFF : 0xFF; + + /* ctable uses bit 8 and upwards only */ + idx = (addr >> 8) & idx_mask; + + /* configurable ctable (i.e. C24) starts at PRU_CTRL_CTBIR0 */ + reg = PRU_CTRL_CTBIR0 + 4 * (c >> 1); + mask = idx_mask << (16 * (c & 1)); + set = idx << (16 * (c & 1)); + + pru_control_set_reg(pru, reg, mask, set); + + return 0; +} + +/** + * pru_start() - start the pru processor + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_start(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + pru_rproc_set_ctable(priv, PRU_C28, 0x100 << 8); + + val = CTRL_CTRL_EN | ((priv->bootaddr >> 2) << 16); + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +/** + * pru_stop() - Stop pru processor + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_stop(struct udevice *dev) +{ + struct pru_privdata *priv; + int val = 0; + + priv = dev_get_priv(dev); + + val = readl(priv->pru_ctrl + PRU_CTRL_CTRL); + val &= ~CTRL_CTRL_EN; + writel(val, priv->pru_ctrl + PRU_CTRL_CTRL); + + return 0; +} + +/** + * pru_init() - Initialize the remote processor + * @dev: rproc device pointer + * + * Return: 0 if all went ok, else return appropriate error + */ +static int pru_init(struct udevice *dev) +{ + return 0; +} + +/* + * Convert PRU device address (data spaces only) to kernel virtual address + * + * Each PRU has access to all data memories within the PRUSS, accessible at + * different ranges. So, look through both its primary and secondary Data + * RAMs as well as any shared Data RAM to convert a PRU device address to + * kernel virtual address. Data RAM0 is primary Data RAM for PRU0 and Data + * RAM1 is primary Data RAM for PRU1. + */ +static void *pru_d_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + phys_addr_t dram0, dram1, shrdram2; + u32 dram0sz, dram1sz, shrdram2sz; + + if (len <= 0) + return NULL; + + dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].pa; + dram1 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa; + shrdram2 = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].pa; + dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM0].size; + dram1sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size; + shrdram2sz = priv->prusspriv->mem_regions[PRUSS_MEM_SHRD_RAM2].size; + + /* PRU1 has its local RAM addresses reversed */ + if (priv->id == 1) { + dram1 = dram0; + dram1sz = dram0sz; + + dram0 = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].pa; + dram0sz = priv->prusspriv->mem_regions[PRUSS_MEM_DRAM1].size; + } + + if (da >= priv->pdram_da && da + len <= priv->pdram_da + dram0sz) { + offset = da - priv->pdram_da; + pa = (__force void *)(dram0 + offset); + } else if (da >= priv->sdram_da && + da + len <= priv->sdram_da + dram1sz) { + offset = da - priv->sdram_da; + pa = (__force void *)(dram1 + offset); + } else if (da >= priv->shrdram_da && + da + len <= priv->shrdram_da + shrdram2sz) { + offset = da - priv->shrdram_da; + pa = (__force void *)(shrdram2 + offset); + } + + return pa; +} + +/* + * Convert PRU device address (instruction space) to kernel virtual address + * + * A PRU does not have an unified address space. Each PRU has its very own + * private Instruction RAM, and its device address is identical to that of + * its primary Data RAM device address. + */ +static void *pru_i_da_to_pa(struct pru_privdata *priv, u32 da, int len) +{ + u32 offset; + void *pa = NULL; + + if (len <= 0) + return NULL; + + if (da >= priv->iram_da && + da + len <= priv->iram_da + priv->pru_iramsz) { + offset = da - priv->iram_da; + pa = (__force void *)(priv->pru_iram + offset); + } + + return pa; +} + +/* PRU-specific address translator */ +static void *pru_da_to_pa(struct pru_privdata *priv, u64 da, int len, u32 flags) +{ + void *pa; + u32 exec_flag; + + exec_flag = ((flags & RPROC_FLAGS_ELF_SHDR) ? flags & SHF_EXECINSTR : + ((flags & RPROC_FLAGS_ELF_PHDR) ? flags & PF_X : 0)); + + if (exec_flag) + pa = pru_i_da_to_pa(priv, da, len); + else + pa = pru_d_da_to_pa(priv, da, len); + + return pa; +} + +/* + * Custom memory copy implementation for ICSSG PRU/RTU Cores + * + * The ICSSG PRU/RTU cores have a memory copying issue with IRAM memories, that + * is not seen on previous generation SoCs. The data is reflected properly in + * the IRAM memories only for integer (4-byte) copies. Any unaligned copies + * result in all the other pre-existing bytes zeroed out within that 4-byte + * boundary, thereby resulting in wrong text/code in the IRAMs. Also, the + * IRAM memory port interface does not allow any 8-byte copies (as commonly + * used by ARM64 memcpy implementation) and throws an exception. The DRAM + * memory ports do not show this behavior. Use this custom copying function + * to properly load the PRU/RTU firmware images on all memories for simplicity. + * + * TODO: Improve the function to deal with additional corner cases like + * unaligned copy sizes or sub-integer trailing bytes when the need arises. + */ +static int pru_rproc_memcpy(void *dest, void *src, size_t count) +{ + const int *s = src; + int *d = dest; + int size = count / 4; + int *tmp_src = NULL; + + /* limited to 4-byte aligned addresses and copy sizes */ + if ((long)dest % 4 || count % 4) + return -EINVAL; + + /* src offsets in ELF firmware image can be non-aligned */ + if ((long)src % 4) { + tmp_src = malloc(count); + if (!tmp_src) + return -ENOMEM; + + memcpy(tmp_src, src, count); + s = tmp_src; + } + + while (size--) + *d++ = *s++; + + kfree(tmp_src); + + return 0; +} + +/** + * pru_load() - Load pru firmware + * @dev: corresponding k3 remote processor device + * @addr: Address on the RAM from which firmware is to be loaded + * @size: Size of the pru firmware in bytes + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_load(struct udevice *dev, ulong addr, ulong size) +{ + struct pru_privdata *priv; + Elf32_Ehdr *ehdr; + Elf32_Phdr *phdr; + int i, ret = 0; + + priv = dev_get_priv(dev); + + ehdr = (Elf32_Ehdr *)addr; + phdr = (Elf32_Phdr *)(addr + ehdr->e_phoff); + + /* go through the available ELF segments */ + for (i = 0; i < ehdr->e_phnum; i++, phdr++) { + u32 da = phdr->p_paddr; + u32 memsz = phdr->p_memsz; + u32 filesz = phdr->p_filesz; + u32 offset = phdr->p_offset; + void *ptr; + + if (phdr->p_type != PT_LOAD) + continue; + + dev_dbg(dev, "phdr: type %d da 0x%x memsz 0x%x filesz 0x%x\n", + phdr->p_type, da, memsz, filesz); + + if (filesz > memsz) { + dev_dbg(dev, "bad phdr filesz 0x%x memsz 0x%x\n", + filesz, memsz); + ret = -EINVAL; + break; + } + + if (offset + filesz > size) { + dev_dbg(dev, "truncated fw: need 0x%x avail 0x%zx\n", + offset + filesz, size); + ret = -EINVAL; + break; + } + + /* grab the kernel address for this device address */ + ptr = pru_da_to_pa(priv, da, memsz, + RPROC_FLAGS_ELF_PHDR | phdr->p_flags); + if (!ptr) { + dev_dbg(dev, "bad phdr da 0x%x mem 0x%x\n", da, memsz); + ret = -EINVAL; + break; + } + + /* skip the memzero logic performed by remoteproc ELF loader */ + if (!phdr->p_filesz) + continue; + + ret = pru_rproc_memcpy(ptr, + (void *)addr + phdr->p_offset, filesz); + if (ret) { + dev_dbg(dev, "PRU custom memory copy failed for da 0x%x memsz 0x%x\n", + da, memsz); + break; + } + } + + priv->bootaddr = ehdr->e_entry; + + return ret; +} + +static const struct dm_rproc_ops pru_ops = { + .init = pru_init, + .start = pru_start, + .stop = pru_stop, + .load = pru_load, +}; + +static void pru_set_id(struct pru_privdata *priv, struct udevice *dev) +{ + u32 mask2 = 0x38000; + + if (device_is_compatible(dev, "ti,am654-rtu")) + mask2 = 0x6000; + + if (device_is_compatible(dev, "ti,am654-tx-pru")) + mask2 = 0xc000; + + if ((priv->pru_iram & mask2) == mask2) + priv->id = 1; + else + priv->id = 0; +} + +/** + * pru_probe() - Basic probe + * @dev: corresponding k3 remote processor device + * + * Return: 0 if all goes good, else appropriate error message. + */ +static int pru_probe(struct udevice *dev) +{ + struct pru_privdata *priv; + ofnode node; + + node = dev_ofnode(dev); + + priv = dev_get_priv(dev); + priv->prusspriv = dev_get_priv(dev->parent); + + priv->pru_iram = devfdt_get_addr_size_index(dev, PRU_MEM_IRAM, + &priv->pru_iramsz); + priv->pru_ctrl = devfdt_get_addr_size_index(dev, PRU_MEM_CTRL, + &priv->pru_ctrlsz); + priv->pru_debug = devfdt_get_addr_size_index(dev, PRU_MEM_DEBUG, + &priv->pru_debugsz); + + priv->iram_da = 0; + priv->pdram_da = 0; + priv->sdram_da = 0x2000; + priv->shrdram_da = 0x10000; + + pru_set_id(priv, dev); + + return 0; +} + +static const struct udevice_id pru_ids[] = { + { .compatible = "ti,am654-pru"}, + { .compatible = "ti,am654-rtu"}, + { .compatible = "ti,am654-tx-pru" }, + {} +}; + +U_BOOT_DRIVER(pru) = { + .name = "pru", + .of_match = pru_ids, + .id = UCLASS_REMOTEPROC, + .ops = &pru_ops, + .probe = pru_probe, + .priv_auto = sizeof(struct pru_privdata), +};

Add the DT nodes for the ICSSG0, ICSSG1 and ICSSG2 processor subsystems that are present on the K3 AM65x SoCs. The three ICSSGs are identical to each other for the most part, with the ICSSG2 supporting slightly enhanced features for supporting SGMII PRU Ethernet. Each ICSSG instance is represented by a PRUSS subsystem node. These nodes are enabled by default.

DT nodes are fetch from Linux 5.13 Kernel.

Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/dts/k3-am65-main.dtsi | 463 +++++++++++++++++++ arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 72 +++ 2 files changed, 535 insertions(+)

diff --git a/arch/arm/dts/k3-am65-main.dtsi b/arch/arm/dts/k3-am65-main.dtsi index cabdba85e0..669484b0dd 100644 --- a/arch/arm/dts/k3-am65-main.dtsi +++ b/arch/arm/dts/k3-am65-main.dtsi @@ -926,4 +926,467 @@ clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; clock-names = "tbclk", "fck"; }; + + icssg0: icssg@b000000 { + compatible = "ti,am654-icssg"; + reg = <0x00 0xb000000 0x00 0x80000>; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0xb000000 0x80000>; + + icssg0_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg0_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg0_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 62 19>, /* icssg0_core_clk */ + <&k3_clks 62 3>; /* icssg0_iclk */ + assigned-clocks = <&icssg0_coreclk_mux>; + assigned-clock-parents = <&k3_clks 62 3>; + }; + + icssg0_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 62 10>, /* icssg0_iep_clk */ + <&icssg0_coreclk_mux>; /* core_clk */ + assigned-clocks = <&icssg0_iepclk_mux>; + assigned-clock-parents = <&icssg0_coreclk_mux>; + }; + }; + }; + + icssg0_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg0_iepclk_mux>; + }; + + icssg0_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg0_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg0_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru0_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_0-fw"; + }; + + rtu0_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_0-fw"; + }; + + tx_pru0_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_0-fw"; + }; + + pru0_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru0_1-fw"; + }; + + rtu0_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu0_1-fw"; + }; + + tx_pru0_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru0_1-fw"; + }; + + icssg0_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 62 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + + icssg1: icssg@b100000 { + compatible = "ti,am654-icssg"; + reg = <0x00 0xb100000 0x00 0x80000>; + power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0xb100000 0x80000>; + + icssg1_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg1_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg1_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 63 19>, /* icssg1_core_clk */ + <&k3_clks 63 3>; /* icssg1_iclk */ + assigned-clocks = <&icssg1_coreclk_mux>; + assigned-clock-parents = <&k3_clks 63 3>; + }; + + icssg1_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 63 10>, /* icssg1_iep_clk */ + <&icssg1_coreclk_mux>; /* core_clk */ + assigned-clocks = <&icssg1_iepclk_mux>; + assigned-clock-parents = <&icssg1_coreclk_mux>; + }; + }; + }; + + icssg1_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg1_iepclk_mux>; + }; + + icssg1_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg1_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg1_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru1_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru1_0-fw"; + }; + + rtu1_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu1_0-fw"; + }; + + tx_pru1_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru1_0-fw"; + }; + + pru1_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru1_1-fw"; + }; + + rtu1_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu1_1-fw"; + }; + + tx_pru1_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru1_1-fw"; + }; + + icssg1_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 63 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + + icssg2: icssg@b200000 { + compatible = "ti,am654-icssg"; + reg = <0x00 0xb200000 0x00 0x80000>; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0xb200000 0x80000>; + + icssg2_mem: memories@0 { + reg = <0x0 0x2000>, + <0x2000 0x2000>, + <0x10000 0x10000>; + reg-names = "dram0", "dram1", + "shrdram2"; + }; + + icssg2_cfg: cfg@26000 { + compatible = "ti,pruss-cfg", "syscon"; + reg = <0x26000 0x200>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x26000 0x2000>; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + icssg2_coreclk_mux: coreclk-mux@3c { + reg = <0x3c>; + #clock-cells = <0>; + clocks = <&k3_clks 64 19>, /* icssg1_core_clk */ + <&k3_clks 64 3>; /* icssg1_iclk */ + assigned-clocks = <&icssg2_coreclk_mux>; + assigned-clock-parents = <&k3_clks 64 3>; + }; + + icssg2_iepclk_mux: iepclk-mux@30 { + reg = <0x30>; + #clock-cells = <0>; + clocks = <&k3_clks 64 10>, /* icssg1_iep_clk */ + <&icssg2_coreclk_mux>; /* core_clk */ + assigned-clocks = <&icssg2_iepclk_mux>; + assigned-clock-parents = <&icssg2_coreclk_mux>; + }; + }; + }; + + icssg2_iep0: iep@2e000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2e000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + + icssg2_iep1: iep@2f000 { + compatible = "ti,am654-icss-iep"; + reg = <0x2f000 0x1000>; + clocks = <&icssg2_iepclk_mux>; + }; + + icssg2_mii_rt: mii-rt@32000 { + compatible = "ti,pruss-mii", "syscon"; + reg = <0x32000 0x100>; + }; + + icssg2_mii_g_rt: mii-g-rt@33000 { + compatible = "ti,pruss-mii-g", "syscon"; + reg = <0x33000 0x1000>; + }; + + icssg2_intc: interrupt-controller@20000 { + compatible = "ti,icssg-intc"; + reg = <0x20000 0x2000>; + interrupt-controller; + #interrupt-cells = <3>; + interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host_intr0", "host_intr1", + "host_intr2", "host_intr3", + "host_intr4", "host_intr5", + "host_intr6", "host_intr7"; + }; + + pru2_0: pru@34000 { + compatible = "ti,am654-pru"; + reg = <0x34000 0x4000>, + <0x22000 0x100>, + <0x22400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru2_0-fw"; + }; + + rtu2_0: rtu@4000 { + compatible = "ti,am654-rtu"; + reg = <0x4000 0x2000>, + <0x23000 0x100>, + <0x23400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu2_0-fw"; + }; + + tx_pru2_0: txpru@a000 { + compatible = "ti,am654-tx-pru"; + reg = <0xa000 0x1800>, + <0x25000 0x100>, + <0x25400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru2_0-fw"; + }; + + pru2_1: pru@38000 { + compatible = "ti,am654-pru"; + reg = <0x38000 0x4000>, + <0x24000 0x100>, + <0x24400 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-pru2_1-fw"; + }; + + rtu2_1: rtu@6000 { + compatible = "ti,am654-rtu"; + reg = <0x6000 0x2000>, + <0x23800 0x100>, + <0x23c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-rtu2_1-fw"; + }; + + tx_pru2_1: txpru@c000 { + compatible = "ti,am654-tx-pru"; + reg = <0xc000 0x1800>, + <0x25800 0x100>, + <0x25c00 0x100>; + reg-names = "iram", "control", "debug"; + firmware-name = "am65x-txpru2_1-fw"; + }; + + icssg2_mdio: mdio@32400 { + compatible = "ti,davinci_mdio"; + reg = <0x32400 0x100>; + clocks = <&k3_clks 64 3>; + clock-names = "fck"; + #address-cells = <1>; + #size-cells = <0>; + bus_freq = <1000000>; + status = "disabled"; + }; + }; + }; diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index 77b7d3f452..df850a2edb 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -4,3 +4,75 @@ */

#include "k3-am654-r5-base-board-u-boot.dtsi" + +&pru0_0 { + remoteproc-name = "pru0_0"; +}; + +&rtu0_0 { + remoteproc-name = "rtu0_0"; +}; + +&tx_pru0_0 { + remoteproc-name = "tx_pru0_0"; +}; + +&pru0_1 { + remoteproc-name = "pru0_1"; +}; + +&rtu0_1 { + remoteproc-name = "rtu0_1"; +}; + +&tx_pru0_1 { + remoteproc-name = "tx_pru0_1"; +}; + +&pru1_0 { + remoteproc-name = "pru1_0"; +}; + +&rtu1_0 { + remoteproc-name = "rtu1_0"; +}; + +&tx_pru1_0 { + remoteproc-name = "tx_pru1_0"; +}; + +&pru1_1 { + remoteproc-name = "pru1_1"; +}; + +&rtu1_1 { + remoteproc-name = "rtu1_1"; +}; + +&tx_pru1_1 { + remoteproc-name = "tx_pru1_1"; +}; + +&pru2_0 { + remoteproc-name = "pru2_0"; +}; + +&rtu2_0 { + remoteproc-name = "rtu2_0"; +}; + +&tx_pru2_0 { + remoteproc-name = "tx_pru2_0"; +}; + +&pru2_1 { + remoteproc-name = "pru2_1"; +}; + +&rtu2_1 { + remoteproc-name = "rtu2_1"; +}; + +&tx_pru2_1 { + remoteproc-name = "tx_pru2_1"; +};