MPC8315ERDB boards features PCI-E x1 and Mini PCI-E x1 ports. Let's support them.

Signed-off-by: Anton Vorontsov avorontsov@ru.mvista.com --- board/freescale/mpc8315erdb/mpc8315erdb.c | 52 +++++++++++++++++++++++++++++ include/configs/MPC8315ERDB.h | 21 +++++++++++ 2 files changed, 73 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index ea4b04f..f80b0ba 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -30,6 +30,7 @@ #include <pci.h> #include <mpc83xx.h> #include <netdev.h> +#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -95,12 +96,45 @@ static struct pci_region pci_regions[] = { } };

+static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +static struct pci_region pcie_regions_1[] = { + { + .bus_start = CONFIG_SYS_PCIE2_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS, + .size = CONFIG_SYS_PCIE2_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE2_IO_BASE, + .phys_start = CONFIG_SYS_PCIE2_IO_PHYS, + .size = CONFIG_SYS_PCIE2_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + void pci_init_board(void) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; + volatile sysconf83xx_t *sysconf = &immr->sysconf; volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; + volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; + struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; int warmboot;

/* Enable all 3 PCI_CLK_OUTPUTs. */ @@ -119,6 +153,24 @@ void pci_init_board(void) warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;

mpc83xx_pci_init(1, reg, warmboot); + + /* Configure the clock for PCIE controller */ + clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, + SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + out_be32(&sysconf->pecr2, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); + out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(2, pcie_reg, warmboot); }

#if defined(CONFIG_OF_BOARD_SETUP) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index add65f0..909353d 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -308,8 +308,29 @@ #define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 #define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000

+#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +#define CONFIG_SYS_PCIE2_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 +#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 + #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ +#define CONFIG_83XX_GENERIC_PCIE 1

#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */