[U-Boot] [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write
From: Tang Yuantian Yuantian.Tang@nxp.com
By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register.
Signed-off-by: Tang Yuantian yuantian.tang@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 6c42387..80fdca5 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -213,10 +213,12 @@ int sata_init(void) ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); + out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
ahci_init((void __iomem *)CONFIG_SYS_SATA1); scsi_scan(0);
On 12/01/2016 01:20 AM, yuantian.tang@nxp.com wrote:
From: Tang Yuantian Yuantian.Tang@nxp.com
By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register.
How about ls1043a, ls1046a? You didn't check SVR.
York
Hi York,
For chasis2 platforms, like ls1043a and ls1046a, similar patch has been merged already.
Patch information:
commit 4de6ce1594fcff6fa9e626d094fa922f4889e167 Author: Tang Yuantian Yuantian.Tang@nxp.com Date: Mon Aug 8 15:07:20 2016
armv8: fsl-lsch2: enable snoopable sata read and write
By default the SATA IP on the ls1043a/ls1046a SoCs does not generating coherent/snoopable transactions. This patch enable it in the SCFG_SNPCNFGCR register along with sata axicc register. In addition, the dma-coherent property must be set on the SATA controller nodes.
Signed-off-by: Tang Yuantian yuantian.tang@nxp.com [York Sun: Reformatted commit message] Reviewed-by: York Sun york.sun@nxp.com
Regards, Yuantian
-----Original Message----- From: york sun Sent: Thursday, January 05, 2017 3:38 AM To: Y.T. Tang yuantian.tang@nxp.com; albert.u.boot@aribaud.net Cc: u-boot@lists.denx.de Subject: Re: [PATCH] armv8: fsl-lsch3: enable snoopable sata read and write
On 12/01/2016 01:20 AM, yuantian.tang@nxp.com wrote:
From: Tang Yuantian Yuantian.Tang@nxp.com
By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register.
How about ls1043a, ls1046a? You didn't check SVR.
York
On 01/04/2017 08:47 PM, Y.T. Tang wrote:
Hi York,
For chasis2 platforms, like ls1043a and ls1046a, similar patch has been merged already.
Ah! I see them in a wider range. You have them under #elif defined(CONFIG_FSL_LSCH2). It isn't visible in this patch.
York
On 12/01/2016 01:20 AM, yuantian.tang@nxp.com wrote:
From: Tang Yuantian Yuantian.Tang@nxp.com
By default the SATA IP on the ls208Xa SoCs does not generating coherent/snoopable transactions. This patch enable it in the sata axicc register.
Signed-off-by: Tang Yuantian yuantian.tang@nxp.com
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York
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