Pierre Savary wrote:

Thanks a lot for your patch. I will test it next week.

Sorry, that patch was manually constructed. I forgot about include/asm-arm/arch-at91sam926x/at91sam9261.h which includes the pin definitions used by the MCI controller. An ancillary patch for this file is appended below. Of course it is useful only for AT91SAM9261 based boards.

Note that Atmel used different conventions for defining AT91SAM9261 and AT91SAM9260/AT91SAM9263 hardware (at least for GPIO pin) definitions. This will cause problems in applying the previously posted u-boot-at91sam9261-mmc-v4.patch for boards not based on the AT91SAM9261 (i.e. AT91SAM9260/AT91SAM9263).

Note that I added the MMC v4.x code without access to the spec. All I had was a MoviNAND manual, which assumes access to the MMC v4.x spec. (Note that the final CMD1 arg. is the correct and recommended value for MoviNAND chips by their field eng.) The patch included a lot of commented out (/* */ & '#if 0') code used to help me understand MMC v4.x, at least well enough to get the MoviNAND working reliably.

I never did get multi-block read or write working; The code for it is included in the previous sent patch. As I mentioned before, I also didn't get 4 bit MMC working, but the code for that is _not_ included in the patch anyway.

The Linux MMC code enables 4 bit for AT91SAM9260/AT91SAM9263 and only 1 bit for AT91SAM9261. Does anyone know why? I'd really like to get 4 bit transfers working on the 9261 via U-Boot.

I may try to put together a better patch using an earlier version of my U-Boot code as a basis. I'm not so sure my previously sent patch will apply as cleanly as I had thought.

Have you ever tested your U-Boot with 4GB or 8GB moviNAND?

No.

Sincerely,

Ken Fuchs

u-boot-at9261-mci-gpio-pins.patch =================================

svn diff -r21 Index: include/asm-arm/arch-at91sam926x/at91sam9261.h =================================================================== --- include/asm-arm/arch-at91sam926x/at91sam9261.h (revision 21) +++ include/asm-arm/arch-at91sam926x/at91sam9261.h (working copy) @@ -17,6 +17,10 @@ * Generated : AT91 SW Application Group 03/30/2005 (17:05:06) * * ------------------------------------------------------------------------ ---- + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added numerous GPIO pin definitions for custom AT91SAM9261 board. + * */ #ifndef AT91SAM9261_H #define AT91SAM9261_H @@ -1330,8 +1334,10 @@ /* ************************************************************************ ***** */ #define AT91C_PIO_PA0 ((unsigned int) 1 << 0) /* Pin Controlled by PA0 */ #define AT91C_PA0_MISO0 ((unsigned int) AT91C_PIO_PA0) /* SPI0 Master In Slave */ +#define AT91C_PA0_MCDA0 ((unsigned int) AT91C_PIO_PA0) /* MMC NAND MCDA0 */ #define AT91C_PIO_PA1 ((unsigned int) 1 << 1) /* Pin Controlled by PA1 */ #define AT91C_PA1_MOSI0 ((unsigned int) AT91C_PIO_PA1) /* SPI0 Master Out Slave */ +#define AT91C_PA1_MCCDA ((unsigned int) AT91C_PIO_PA1) /* MMC NAND MCCDA */ #define AT91C_PIO_PA10 ((unsigned int) 1 << 10) /* Pin Controlled by PA10 */ #define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) /* DBGU Debug Transmit Data */ #define AT91C_PA10_LFON ((unsigned int) AT91C_PIO_PA10) @@ -1346,6 +1352,7 @@ #define AT91C_PA16_NPCS15 ((unsigned int) AT91C_PIO_PA16) /* GPIO: SPI1 CS5 */ #define AT91C_PIO_PA2 ((unsigned int) 1 << 2) /* Pin Controlled by PA2 */ #define AT91C_PA2_SPCK0 ((unsigned int) AT91C_PIO_PA2) /* SPI0 Serial Clock */ +#define AT91C_PA2_MCCK ((unsigned int) AT91C_PIO_PA2) /* MMC NAND MCCK */ #define AT91C_PIO_PA23 ((unsigned int) 1 << 23) /* Pin Controlled by PA23 */ #define AT91C_PA23_NPCS14 ((unsigned int) AT91C_PIO_PA23) /* GPIO: SPI1 CS4 */ #define AT91C_PIO_PA24 ((unsigned int) 1 << 24) /* Pin Controlled by PA24 */ @@ -1358,10 +1365,13 @@ #define AT91C_PA3_NPCS00 ((unsigned int) AT91C_PIO_PA3) /* SPI0 Peripheral Chip Select 0 */ #define AT91C_PIO_PA4 ((unsigned int) 1 << 4) /* Pin Controlled by PA4 */ #define AT91C_PA4_NPCS01 ((unsigned int) AT91C_PIO_PA4) /* SPI0 Peripheral Chip Select 1 */ +#define AT91C_PA4_MCDA1 ((unsigned int) AT91C_PIO_PA4) /* MMC NAND MCDA1 */ #define AT91C_PIO_PA5 ((unsigned int) 1 << 5) /* Pin Controlled by PA5 */ #define AT91C_PA5_NPCS02 ((unsigned int) AT91C_PIO_PA5) /* SPI0 Peripheral Chip Select 2 */ +#define AT91C_PA5_MCDA2 ((unsigned int) AT91C_PIO_PA5) /* MMC NAND MCDA2 */ #define AT91C_PIO_PA6 ((unsigned int) 1 << 6) /* Pin Controlled by PA6 */ #define AT91C_PA6_NPCS03 ((unsigned int) AT91C_PIO_PA6) /* SPI0 Peripheral Chip Select 3 */ +#define AT91C_PA6_MCDA3 ((unsigned int) AT91C_PIO_PA6) /* MMC NAND MCDA3 */ #define AT91C_PIO_PA9 ((unsigned int) 1 << 9) /* Pin Controlled by PA9 */ #define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) /* DBGU Debug Receive Data */ #define AT91C_PIO_PB0 ((unsigned int) 1 << 0) /* Pin Controlled by PB0 */