The patch changes PCIe dts node status to 'disabled' if the corresponding controller is disabled according to serdes protocol.

Signed-off-by: Minghuan Lian Minghuan.Lian@freescale.com --- arch/arm/include/asm/arch-ls102xa/config.h | 3 ++ arch/arm/include/asm/pcie_layerscape.h | 13 ++++++++ board/freescale/ls1021aqds/ls1021aqds.c | 5 +++ board/freescale/ls1021atwr/ls1021atwr.c | 5 +++ drivers/pci/Makefile | 1 + drivers/pci/pcie_layerscape.c | 51 ++++++++++++++++++++++++++++++ include/configs/ls1021aqds.h | 8 +++++ include/configs/ls1021atwr.h | 7 ++++ 8 files changed, 93 insertions(+) create mode 100644 arch/arm/include/asm/pcie_layerscape.h create mode 100644 drivers/pci/pcie_layerscape.c

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index f2c9687..9fd0b2c 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -49,6 +49,9 @@

#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)

+#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000) +#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000) + #ifdef CONFIG_DDR_SPD #define CONFIG_SYS_FSL_DDR_BE #define CONFIG_VERY_BIG_RAM diff --git a/arch/arm/include/asm/pcie_layerscape.h b/arch/arm/include/asm/pcie_layerscape.h new file mode 100644 index 0000000..fb08578 --- /dev/null +++ b/arch/arm/include/asm/pcie_layerscape.h @@ -0,0 +1,13 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __PCIE_LAYERSCAPE_H_ +#define __PCIE_LAYERSCAPE_H_ + +void pci_init_board(void); +void ft_pcie_setup(void *blob, bd_t *bd); + +#endif diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 5fafc85..fccf6b6 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -10,6 +10,7 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -243,6 +244,10 @@ int board_init(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif }

u8 flash_read8(void *addr) diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 50d5640..0b548eb 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -10,6 +10,7 @@ #include <asm/arch/immap_ls102xa.h> #include <asm/arch/clock.h> #include <asm/arch/fsl_serdes.h> +#include <asm/pcie_layerscape.h> #include <mmc.h> #include <fsl_esdhc.h> #include <fsl_ifc.h> @@ -293,6 +294,10 @@ int misc_init_r(void) void ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); + +#ifdef CONFIG_PCIE_LAYERSCAPE + ft_pcie_setup(blob, bd); +#endif }

u8 flash_read8(void *addr) diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index e73a498..e525ceb 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_SH7751_PCI) +=pci_sh7751.o obj-$(CONFIG_SH7780_PCI) +=pci_sh7780.o obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o obj-$(CONFIG_WINBOND_83C553) += w83c553f.o +obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o diff --git a/drivers/pci/pcie_layerscape.c b/drivers/pci/pcie_layerscape.c new file mode 100644 index 0000000..291c249 --- /dev/null +++ b/drivers/pci/pcie_layerscape.c @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Freescale Semiconductor, Inc. + * Layerscape PCIe driver + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/fsl_serdes.h> +#include <pci.h> +#include <asm/io.h> +#include <asm/pcie_layerscape.h> + +#ifdef CONFIG_OF_BOARD_SETUP +#include <libfdt.h> +#include <fdt_support.h> + +static void ft_pcie_ls_setup(void *blob, const char *pci_compat, + unsigned long ctrl_addr, enum srds_prtcl dev) +{ + int off; + + off = fdt_node_offset_by_compat_reg(blob, pci_compat, + (phys_addr_t)ctrl_addr); + if (off < 0) + return; + + if (!is_serdes_configured(dev)) + fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); +} + +void ft_pcie_setup(void *blob, bd_t *bd) +{ + #ifdef CONFIG_PCIE1 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE1_ADDR, PCIE1); + #endif + + #ifdef CONFIG_PCIE2 + ft_pcie_ls_setup(blob, FSL_PCIE_COMPAT, CONFIG_SYS_PCIE2_ADDR, PCIE2); + #endif +} + +#else +void ft_pcie_setup(void *blob, bd_t *bd) +{ +} +#endif + +void pci_init_board(void) +{ +} diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d1f6ea7..5544b81 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -318,6 +318,14 @@ unsigned long get_board_ddr_clk(void); #endif

#endif + +/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 3c73af8..15873a9 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -220,6 +220,13 @@ #define CONFIG_HAS_ETH2 #endif

+/* PCIe */ +#define CONFIG_PCI /* Enable PCI/PCIE */ +#define CONFIG_PCIE1 /* PCIE controler 1 */ +#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" + #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_MII