[U-Boot] [PATCH 1/4] rockchip: arm64: rk3399: revise timeout-handling for DRAM PHY lock
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 216a26c..4dd84e2 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -5,6 +5,7 @@ * * Adapted from coreboot. */ + #include <common.h> #include <clk.h> #include <dm.h> @@ -19,6 +20,7 @@ #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <linux/err.h> +#include <time.h>
DECLARE_GLOBAL_DATA_PTR; struct chan_info { @@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret; + const ulong timeout_ms = 200;
/* * work around controller bug: @@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
/* Wating for PHY and DRAM init complete */ - tmp = 0; - while (!(readl(&denali_ctl[203]) & (1 << 3))) { - mdelay(10); - tmp++; - if (tmp > 10) + tmp = get_timer(0); + do { + if (get_timer(tmp) > timeout_ms) { + error("DRAM (%s): phy failed to lock within %ld ms\n", + __func__, timeout_ms); return -ETIME; - } + } + } while (!(readl(&denali_ctl[203]) & (1 << 3))); + debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit);
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866), if the PCB layout permits and appropriate memory timings are used.
This changes the sanity checks to allow a DTS to request DDR3-1866 operation.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com ---
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 4dd84e2..0b87fcf 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -1090,7 +1090,7 @@ static int sdram_init(struct dram_info *dram,
debug("Starting SDRAM initialization...\n");
- if ((dramtype == DDR3 && ddr_freq > 800) || + if ((dramtype == DDR3 && ddr_freq > 933) || (dramtype == LPDDR3 && ddr_freq > 933) || (dramtype == LPDDR4 && ddr_freq > 800)) { debug("SDRAM frequency is to high!");
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866), if the PCB layout permits and appropriate memory timings are used.
This changes the sanity checks to allow a DTS to request DDR3-1866 operation.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Simon Glass sjg@chromium.org
Philipp,
On 06/01/2017 12:16 AM, Philipp Tomsich wrote:
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866), if the PCB layout permits and appropriate memory timings are used.
This changes the sanity checks to allow a DTS to request DDR3-1866 operation.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 4dd84e2..0b87fcf 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -1090,7 +1090,7 @@ static int sdram_init(struct dram_info *dram,
debug("Starting SDRAM initialization...\n");
- if ((dramtype == DDR3 && ddr_freq > 800) ||
- if ((dramtype == DDR3 && ddr_freq > 933) || (dramtype == LPDDR3 && ddr_freq > 933) || (dramtype == LPDDR4 && ddr_freq > 800)) { debug("SDRAM frequency is to high!");
Philipp,
On 06/01/2017 12:16 AM, Philipp Tomsich wrote:
The RK3399 is capable of driving DDR3 at 933MHz (i.e. DDR3-1866), if the PCB layout permits and appropriate memory timings are used.
This changes the sanity checks to allow a DTS to request DDR3-1866 operation.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com Tested-by: Klaus Goger klaus.goger@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
Applied to u-boot-rockchip, thanks!
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built with the DDR3-1866 option.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 1537 ++++++++++++++++++++++++++++++ 1 file changed, 1537 insertions(+) create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
diff --git a/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi new file mode 100644 index 0000000..80e946e --- /dev/null +++ b/arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi @@ -0,0 +1,1537 @@ +/* + * (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&dmc { + rockchip,sdram-params = < + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80181219 + 0x17050a03 + 0x00000002 + 0x00006456 + 0x0000004c + 0x00000000 + 0x1 + 0xa + 0x3 + 0x2 + 0x1 + 0x0 + 0xf + 0xf + 1 + 0x80181219 + 0x17050a03 + 0x00000002 + 0x00006456 + 0x0000004c + 0x00000000 + 933 + 3 + 2 + 9 + 1 + 0x00000600 + 0x00000000 + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x00000000 + 0x0000000a + 0x00000000 + 0x00000000 + 0x01000000 + 0x00000000 + 0x00000101 + 0x00020100 + 0x0002d976 + 0x00071fa6 + 0x02000200 + 0x091a0200 + 0x00091a00 + 0x0400091a + 0x2c060004 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On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built with the DDR3-1866 option.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 1537 ++++++++++++++++++++++++++++++ 1 file changed, 1537 insertions(+) create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
Reviewed-by: Simon Glass sjg@chromium.org
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
With the validation done for DDR3-1866 (i.e. 933 MHz bus clock), we can now add the timings (rk3399-sdram-ddr3-1866.dtsi) for boards built with the DDR3-1866 option.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi | 1537 ++++++++++++++++++++++++++++++ 1 file changed, 1537 insertions(+) create mode 100644 arch/arm/dts/rk3399-sdram-ddr3-1866.dtsi
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
The RK3399-Q7 has multiple build-options for its DRAM configuration, including the timing of the DRAM components populated.
While DDR3-1600 is the standard configuration, custom-configurations are available with DDR3-1333 (for a further cost-optimisation) and with DDR3-1866 (as a premium option).
To simplify our test automation (without the need to maintain 3 different defconfigs) and customer evaluation, we make this selectable via Kconfig.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com ---
arch/arm/dts/rk3399-puma.dts | 8 +++++++ board/theobroma-systems/puma_rk3399/Kconfig | 37 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)
diff --git a/arch/arm/dts/rk3399-puma.dts b/arch/arm/dts/rk3399-puma.dts index fca14d3..41d32eb 100644 --- a/arch/arm/dts/rk3399-puma.dts +++ b/arch/arm/dts/rk3399-puma.dts @@ -8,7 +8,15 @@
#include <dt-bindings/pwm/pwm.h> #include "rk3399.dtsi" +#if defined(CONFIG_SYS_TSD_PUMA_DDR3_1333) +#include "rk3399-sdram-ddr3-1333.dtsi" +#elif defined(CONFIG_SYS_TSD_PUMA_DDR3_1600) #include "rk3399-sdram-ddr3-1600.dtsi" +#elif defined(CONFIG_SYS_TSD_PUMA_DDR3_1866) +#include "rk3399-sdram-ddr3-1866.dtsi" +#else +#error "Unknown memory timing configuration for the RK3399-Q7" +#endif
/ { model = "Theobroma Systems RK3399-Q7 SoM"; diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig index a645590..1773648 100644 --- a/board/theobroma-systems/puma_rk3399/Kconfig +++ b/board/theobroma-systems/puma_rk3399/Kconfig @@ -12,4 +12,41 @@ config SYS_CONFIG_NAME config BOARD_SPECIFIC_OPTIONS # dummy def_bool y
+if SPL + +choice + prompt "RK3399-Q7 DRAM timings" + default SYS_TSD_PUMA_DDR3_1600 + help + The RK3399-Q7 module is orderable in multiple memory + configurations, which may also differ in the timings used. + + DDR3-1600 is the standard configuration, but both DDR3-1333 + (for potential cost-optimisation) and DDR3-1866 (as a + premium option) are fully validated in the design. + + The setting of this option is used to select the appropriate + timings for inclusion in the device tree controlling DRAM + initialisation during the board-initialisation performed by + the SPL stage. + +config SYS_TSD_PUMA_DDR3_1333 + bool "DDR3-1333 timings" + help + Use DDR3-1333 timings for the DRAM setup of the RK3399-Q7. + +config SYS_TSD_PUMA_DDR3_1600 + bool "DDR3-1600 timings" + help + Use DDR3-1600 timings for the DRAM setup of the RK3399-Q7. + +config SYS_TSD_PUMA_DDR3_1866 + bool "DDR3-1866 timings" + help + Use DDR3-1866 timings for the DRAM setup of the RK3399-Q7. + +endchoice + +endif + endif
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The RK3399-Q7 has multiple build-options for its DRAM configuration, including the timing of the DRAM components populated.
While DDR3-1600 is the standard configuration, custom-configurations are available with DDR3-1333 (for a further cost-optimisation) and with DDR3-1866 (as a premium option).
To simplify our test automation (without the need to maintain 3 different defconfigs) and customer evaluation, we make this selectable via Kconfig.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-puma.dts | 8 +++++++ board/theobroma-systems/puma_rk3399/Kconfig | 37 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Hi Philipp,
On 1 June 2017 at 20:55, Simon Glass sjg@chromium.org wrote:
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
The RK3399-Q7 has multiple build-options for its DRAM configuration, including the timing of the DRAM components populated.
While DDR3-1600 is the standard configuration, custom-configurations are available with DDR3-1333 (for a further cost-optimisation) and with DDR3-1866 (as a premium option).
To simplify our test automation (without the need to maintain 3 different defconfigs) and customer evaluation, we make this selectable via Kconfig.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/dts/rk3399-puma.dts | 8 +++++++ board/theobroma-systems/puma_rk3399/Kconfig | 37 +++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Unfortunately this break various boards including firefly-rk3288.
Instead of the #ifdef can you please add a separate .dts for each variant, with each including a .dtsi with the rest of it?
Regards, Simon
Philipp,
On 06/01/2017 12:16 AM, Philipp Tomsich wrote:
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
Reviewed-by: Kever Yang kever.yang@rock-chips.com
Thanks, - Kever
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c index 216a26c..4dd84e2 100644 --- a/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/sdram_rk3399.c @@ -5,6 +5,7 @@
- Adapted from coreboot.
*/
- #include <common.h> #include <clk.h> #include <dm.h>
@@ -19,6 +20,7 @@ #include <asm/arch/grf_rk3399.h> #include <asm/arch/hardware.h> #include <linux/err.h> +#include <time.h>
DECLARE_GLOBAL_DATA_PTR; struct chan_info { @@ -506,6 +508,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, u32 tmp, tmp1, tmp2; u32 pwrup_srefresh_exit; int ret;
const ulong timeout_ms = 200;
/*
- work around controller bug:
@@ -588,13 +591,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel, clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
/* Wating for PHY and DRAM init complete */
- tmp = 0;
- while (!(readl(&denali_ctl[203]) & (1 << 3))) {
mdelay(10);tmp++;if (tmp > 10)
- tmp = get_timer(0);
- do {
if (get_timer(tmp) > timeout_ms) {error("DRAM (%s): phy failed to lock within %ld ms\n",__func__, timeout_ms); return -ETIME;
- }
}} while (!(readl(&denali_ctl[203]) & (1 << 3)));
debug("DRAM (%s): phy locked after %ld ms\n", __func__, get_timer(tmp));
clrsetbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT, pwrup_srefresh_exit);
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On 31 May 2017 at 10:16, Philipp Tomsich philipp.tomsich@theobroma-systems.com wrote:
Revise the loop watching for a timeout on obtaining a DRAM PHY lock to clearly state a timeout in milliseconds and use get_timer (based on the ARMv8 architected timer) to detect a timeout.
Signed-off-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com
arch/arm/mach-rockchip/rk3399/sdram_rk3399.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Applied to u-boot-rockchip, thanks!
participants (4)
-
Kever Yang -
Philipp Tomsich -
Simon Glass -
sjg＠google.com