[U-Boot] [PATCH v3 01/11] m68k: add basic set of devicetrees
This patch adds a basic group of devicetrees, one for each cpu family, including actually just uart and dspi devices, since these are the drivers supporting devicetree (support added in this patch-set).
Acked-by: Jagan Teki jagan@amarulasolutions.com Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - add mcf54xx.dtsi and mcf537x.dtsi Changes for v3: - none --- arch/m68k/dts/mcf5208.dtsi | 36 ++++++++ arch/m68k/dts/mcf5227x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf523x.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5249.dtsi | 38 ++++++++ arch/m68k/dts/mcf5253.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5271.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5272.dtsi | 38 ++++++++ arch/m68k/dts/mcf5275.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5282.dtsi | 44 ++++++++++ arch/m68k/dts/mcf5301x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf5307.dtsi | 39 +++++++++ arch/m68k/dts/mcf5329.dtsi | 36 ++++++++ arch/m68k/dts/mcf537x.dtsi | 36 ++++++++ arch/m68k/dts/mcf5441x.dtsi | 87 +++++++++++++++++++ arch/m68k/dts/mcf5445x.dtsi | 48 ++++++++++ arch/m68k/dts/mcf54xx.dtsi | 40 +++++++++ doc/device-tree-bindings/serial/mcf-uart.txt | 19 ++++ doc/device-tree-bindings/spi/spi-mcf-dspi.txt | 30 +++++++ 18 files changed, 763 insertions(+) create mode 100644 arch/m68k/dts/mcf5208.dtsi create mode 100644 arch/m68k/dts/mcf5227x.dtsi create mode 100644 arch/m68k/dts/mcf523x.dtsi create mode 100644 arch/m68k/dts/mcf5249.dtsi create mode 100644 arch/m68k/dts/mcf5253.dtsi create mode 100644 arch/m68k/dts/mcf5271.dtsi create mode 100644 arch/m68k/dts/mcf5272.dtsi create mode 100644 arch/m68k/dts/mcf5275.dtsi create mode 100644 arch/m68k/dts/mcf5282.dtsi create mode 100644 arch/m68k/dts/mcf5301x.dtsi create mode 100644 arch/m68k/dts/mcf5307.dtsi create mode 100644 arch/m68k/dts/mcf5329.dtsi create mode 100644 arch/m68k/dts/mcf537x.dtsi create mode 100644 arch/m68k/dts/mcf5441x.dtsi create mode 100644 arch/m68k/dts/mcf5445x.dtsi create mode 100644 arch/m68k/dts/mcf54xx.dtsi create mode 100644 doc/device-tree-bindings/serial/mcf-uart.txt create mode 100644 doc/device-tree-bindings/spi/spi-mcf-dspi.txt
diff --git a/arch/m68k/dts/mcf5208.dtsi b/arch/m68k/dts/mcf5208.dtsi new file mode 100644 index 0000000000..558d8bf41a --- /dev/null +++ b/arch/m68k/dts/mcf5208.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5208"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5227x.dtsi b/arch/m68k/dts/mcf5227x.dtsi new file mode 100644 index 0000000000..8c95edddb6 --- /dev/null +++ b/arch/m68k/dts/mcf5227x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5227x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf523x.dtsi b/arch/m68k/dts/mcf523x.dtsi new file mode 100644 index 0000000000..9e79d472ec --- /dev/null +++ b/arch/m68k/dts/mcf523x.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf523x"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5249.dtsi b/arch/m68k/dts/mcf5249.dtsi new file mode 100644 index 0000000000..248b3dc68b --- /dev/null +++ b/arch/m68k/dts/mcf5249.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5249"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5253.dtsi b/arch/m68k/dts/mcf5253.dtsi new file mode 100644 index 0000000000..3bde2d6202 --- /dev/null +++ b/arch/m68k/dts/mcf5253.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5253"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart3: uart@c00 { + compatible = "fsl,mcf-uart"; + reg = <0xc00 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5271.dtsi b/arch/m68k/dts/mcf5271.dtsi new file mode 100644 index 0000000000..29355528d0 --- /dev/null +++ b/arch/m68k/dts/mcf5271.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5271"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5272.dtsi b/arch/m68k/dts/mcf5272.dtsi new file mode 100644 index 0000000000..a56117728b --- /dev/null +++ b/arch/m68k/dts/mcf5272.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5272"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@100 { + compatible = "fsl,mcf-uart"; + reg = <0x100 0x40>; + status = "disabled"; + }; + + uart1: uart@140 { + compatible = "fsl,mcf-uart"; + reg = <0x140 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5275.dtsi b/arch/m68k/dts/mcf5275.dtsi new file mode 100644 index 0000000000..b375609d4a --- /dev/null +++ b/arch/m68k/dts/mcf5275.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5275"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5282.dtsi b/arch/m68k/dts/mcf5282.dtsi new file mode 100644 index 0000000000..3ad1be7bb5 --- /dev/null +++ b/arch/m68k/dts/mcf5282.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5282"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + ipsbar: ipsbar@4000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x40000000 0x40000000>; + reg = <0x40000000 0x40000000>; + + uart0: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + + uart1: uart@240 { + compatible = "fsl,mcf-uart"; + reg = <0x240 0x40>; + status = "disabled"; + }; + + uart2: uart@280 { + compatible = "fsl,mcf-uart"; + reg = <0x280 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5301x.dtsi b/arch/m68k/dts/mcf5301x.dtsi new file mode 100644 index 0000000000..0891e4dfd5 --- /dev/null +++ b/arch/m68k/dts/mcf5301x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5301x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5307.dtsi b/arch/m68k/dts/mcf5307.dtsi new file mode 100644 index 0000000000..e199cf9991 --- /dev/null +++ b/arch/m68k/dts/mcf5307.dtsi @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5307"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + /* MBAR */ + mbar: mbar@10000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x10000000 0x10000>; + reg = <0x10000000 0x10000>; + + uart0: uart@1c0 { + compatible = "fsl,mcf-uart"; + reg = <0x1c0 0x40>; + status = "disabled"; + }; + + uart1: uart@200 { + compatible = "fsl,mcf-uart"; + reg = <0x200 0x40>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5329.dtsi b/arch/m68k/dts/mcf5329.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf5329.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf537x.dtsi b/arch/m68k/dts/mcf537x.dtsi new file mode 100644 index 0000000000..aeaa6430af --- /dev/null +++ b/arch/m68k/dts/mcf537x.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5329"; + + aliases { + serial0 = &uart0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5441x.dtsi b/arch/m68k/dts/mcf5441x.dtsi new file mode 100644 index 0000000000..71b392adc3 --- /dev/null +++ b/arch/m68k/dts/mcf5441x.dtsi @@ -0,0 +1,87 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5441x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + uart3: uart@fc06c000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc06c000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi1: dspi@fc03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc03c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi2: dspi@ec038000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec038000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + + dspi3: dspi@ec03c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xec03c00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf5445x.dtsi b/arch/m68k/dts/mcf5445x.dtsi new file mode 100644 index 0000000000..ccbee29a6c --- /dev/null +++ b/arch/m68k/dts/mcf5445x.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf5445x"; + + aliases { + serial0 = &uart0; + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; + + uart1: uart@fc064000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc064000 0x40>; + status = "disabled"; + }; + + uart2: uart@fc068000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc068000 0x40>; + status = "disabled"; + }; + + dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; +}; diff --git a/arch/m68k/dts/mcf54xx.dtsi b/arch/m68k/dts/mcf54xx.dtsi new file mode 100644 index 0000000000..537bb424f3 --- /dev/null +++ b/arch/m68k/dts/mcf54xx.dtsi @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/ { + compatible = "fsl,mcf54x5"; + + aliases { + /* TO DO, clarify on serial, this SoC seems to have SPC and + * no UARTS. + */ + spi0 = &dspi0; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + mbar: mbar@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x00000000 0x80000000 0x10000>; + reg = <0x80000000 0x10000>; + + dspi0: dspi@8a00 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8a00 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + status = "disabled"; + }; + }; + }; +}; diff --git a/doc/device-tree-bindings/serial/mcf-uart.txt b/doc/device-tree-bindings/serial/mcf-uart.txt new file mode 100644 index 0000000000..d73f764c01 --- /dev/null +++ b/doc/device-tree-bindings/serial/mcf-uart.txt @@ -0,0 +1,19 @@ +Freescale ColdFire UART + +Required properties: +- compatible : should be "fsl,mcf-uart" +- reg: start address and size of the registers + +Example: + +soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + + uart0: uart@fc060000 { + compatible = "fsl,mcf-uart"; + reg = <0xfc060000 0x40>; + status = "disabled"; + }; +}; diff --git a/doc/device-tree-bindings/spi/spi-mcf-dspi.txt b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt new file mode 100644 index 0000000000..860eb8ac85 --- /dev/null +++ b/doc/device-tree-bindings/spi/spi-mcf-dspi.txt @@ -0,0 +1,30 @@ +Freescale ColdFire DSPI controller + +Required properties: +- compatible : "fsl,mcf-dspi" +- #address-cells: <1>, as required by generic SPI binding +- #size-cells: <0>, also as required by generic SPI binding +- reg : offset and length of the register set for the device + +Optional properties: +- spi-max-frequency : max supported spi frequency +- num-cs : the number of the chipselect signals +- spi-mode: spi motorola mode, 0 to 3 +- ctar-params: CTAR0 to 7 register configuration, as an array + of 8 integer fields for each register, where each register + is defined as: <fmsz, pcssck, pasc, pdt, cssck, asc, dt, br>. + +Example: + +dspi0: dspi@fc05c000 { + compatible = "fsl,mcf-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xfc05c000 0x100>; + spi-max-frequency = <50000000>; + num-cs = <4>; + spi-mode = <0>; + ctar-fields = <7, 0, 0, 0, 0, 0, 1, 6>, + <7, 0, 0, 0, 0, 0, 1, 6>, + <7, 0, 0, 0, 0, 0, 1, 6>; +};
This patch adds cf_spi DM Kconfig option.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - re-put SOFT_SPI in place, options are out of alphabetical order --- drivers/spi/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 1df6876e9b..363f702a80 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -87,6 +87,12 @@ config CADENCE_QSPI used to access the SPI NOR flash on platforms embedding this Cadence IP core.
+config CF_SPI + bool "ColdFire SPI driver" + help + Enable the ColdFire SPI driver. This driver can be used on + some m68k SoCs. + config DESIGNWARE_SPI bool "Designware SPI driver" help
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds cf_spi DM Kconfig option.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- re-put SOFT_SPI in place, options are out of alphabetical order
drivers/spi/Kconfig | 6 ++++++ 1 file changed, 6 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
Converting to driver model and removes non-dm code.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - removed non DM code part - add default setup of CTAR registers - add DT CTAR register setup support Changes for v3: - changed commit head - removed spi_slave reference - add #ifdefs for the case OF_PLATDATA is used --- drivers/spi/cf_spi.c | 517 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 29 ++ 2 files changed, 352 insertions(+), 194 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 522631cbbf..bc6a156df9 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,25 @@ * * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) + * + * Support for DM and DT, non-DM code removed. + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + * + * TODO: fsl_dspi.c should work as a driver for the DSPI module. */
#include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> +#include <asm/io.h>
-struct cf_spi_slave { - struct spi_slave slave; +struct coldfire_spi_priv { + struct dspi *regs; uint baudrate; + int mode; int charbit; };
@@ -38,14 +47,30 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{ - return container_of(slave, struct cf_spi_slave, slave); -} +#define MCF_DSPI_MAX_CTAR_REGS 8
-static void cfspi_init(void) +/* Default values */ +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000 +#define MCF_DSPI_DEFAULT_MAX_CS 4 +#define MCF_DSPI_DEFAULT_MODE 0 + +#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \ + DSPI_CTAR_PCSSCK_1CLK | \ + DSPI_CTAR_PASC(0) | \ + DSPI_CTAR_PDT(0) | \ + DSPI_CTAR_CSSCK(0) | \ + DSPI_CTAR_ASC(0) | \ + DSPI_CTAR_DT(1) | \ + DSPI_CTAR_BR(6)) + +static void __spi_init(struct coldfire_spi_priv *cfspi) { - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + struct dspi *dspi = cfspi->regs; + int i; + + /* Default CTARs */ + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) + writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]);
cfspi_port_conf(); /* port configuration */
@@ -53,128 +78,9 @@ static void cfspi_init(void) DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | DSPI_MCR_CRXF | DSPI_MCR_CTXF; - - /* Default setting in platform configuration */ -#ifdef CONFIG_SYS_DSPI_CTAR0 - dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR1 - dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR2 - dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR3 - dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR4 - dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR5 - dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR6 - dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6; -#endif -#ifdef CONFIG_SYS_DSPI_CTAR7 - dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7; -#endif -} - -static void cfspi_tx(u32 ctrl, u16 data) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->sr & 0x0000F000) >= 4) ; - - dspi->tfr = (ctrl | data); }
-static u16 cfspi_rx(void) -{ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; - - while ((dspi->sr & 0x000000F0) == 0) ; - - return (dspi->rfr & 0xFFFF); -} - -static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout, - void *din, ulong flags) -{ - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); - u16 *spi_rd16 = NULL, *spi_wr16 = NULL; - u8 *spi_rd = NULL, *spi_wr = NULL; - static u32 ctrl = 0; - uint len = bitlen >> 3; - - if (cfslave->charbit == 16) { - bitlen >>= 1; - spi_wr16 = (u16 *) dout; - spi_rd16 = (u16 *) din; - } else { - spi_wr = (u8 *) dout; - spi_rd = (u8 *) din; - } - - if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) - ctrl |= DSPI_TFR_CONT; - - ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16); - - if (len > 1) { - int tmp_len = len - 1; - while (tmp_len--) { - if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16++); - else - cfspi_tx(ctrl, *spi_wr++); - cfspi_rx(); - } - - if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16++ = cfspi_rx(); - else - *spi_rd++ = cfspi_rx(); - } - } - - len = 1; /* remaining byte */ - } - - if ((flags & SPI_XFER_END) == SPI_XFER_END) - ctrl &= ~DSPI_TFR_CONT; - - if (len) { - if (dout != NULL) { - if (cfslave->charbit == 16) - cfspi_tx(ctrl, *spi_wr16); - else - cfspi_tx(ctrl, *spi_wr); - cfspi_rx(); - } - - if (din != NULL) { - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - if (cfslave->charbit == 16) - *spi_rd16 = cfspi_rx(); - else - *spi_rd = cfspi_rx(); - } - } else { - /* dummy read */ - cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL); - cfspi_rx(); - } - - return 0; -} - -static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, - uint mode) +int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus) { /* * bit definition for mode: @@ -189,7 +95,7 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, * 11 - 8: Delay after transfer scaler * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST */ - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI; + struct dspi *dspi = cfspi->regs; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8, @@ -199,56 +105,38 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed; - u32 bus_setup = 0; + u32 bus_setup; + + /* Read current setup */ + bus_setup = readl(&dspi->ctar[bus]);
tmp = (prescaler[3] * scaler[15]); /* Maximum and minimum baudrate it can handle */ - if ((cfslave->baudrate > (gd->bus_clk >> 1)) || - (cfslave->baudrate < (gd->bus_clk / tmp))) { + if ((cfspi->baudrate > (gd->bus_clk >> 1)) || + (cfspi->baudrate < (gd->bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp)); - return NULL; + return -1; }
/* Activate Double Baud when it exceed 1/4 the bus clk */ - if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) || - (cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { + if ((bus_setup & DSPI_CTAR_DBR) || + (cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
- if (mode & SPI_CPOL) - bus_setup |= DSPI_CTAR_CPOL; - if (mode & SPI_CPHA) - bus_setup |= DSPI_CTAR_CPHA; - if (mode & SPI_LSB_FIRST) - bus_setup |= DSPI_CTAR_LSBFE; - /* Overwrite default value set in platform configuration file */ - if (mode & SPI_MODE_MOD) { - - if ((mode & 0xF0000000) == 0) - bus_setup |= - dspi->ctar[cfslave->slave.bus] & 0x78000000; - else - bus_setup |= ((mode & 0xF0000000) >> 1); - + if (cfspi->mode & SPI_MODE_MOD) { /* * Check to see if it is enabled by default in platform * config, or manual setting passed by mode parameter */ - if (mode & SPI_DBLRATE) { + if (cfspi->mode & SPI_DBLRATE) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; } - bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */ - bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */ - } else - bus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0); - - cfslave->charbit = - ((dspi->ctar[cfslave->slave.bus] & 0x78000000) == - 0x78000000) ? 16 : 8; + }
pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int); @@ -259,10 +147,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr);
- if (tmp > cfslave->baudrate) - diff = tmp - cfslave->baudrate; + if (tmp > cfspi->baudrate) + diff = tmp - cfspi->baudrate; else - diff = cfslave->baudrate - tmp; + diff = cfspi->baudrate - tmp;
if (diff < bestmatch) { bestmatch = diff; @@ -271,65 +159,306 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, } } } + + bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f)); bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j)); - dspi->ctar[cfslave->slave.bus] = bus_setup; + writel(bus_setup, &dspi->ctar[bus]); + + return 0; +} + +static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus) +{ + struct dspi *dspi = cfspi->regs; + u32 bus_setup = 0; + + if (cfspi->mode & SPI_CPOL) + bus_setup |= DSPI_CTAR_CPOL; + if (cfspi->mode & SPI_CPHA) + bus_setup |= DSPI_CTAR_CPHA; + if (cfspi->mode & SPI_LSB_FIRST) + bus_setup |= DSPI_CTAR_LSBFE; + + /* Overwrite default value set in platform configuration file */ + if (cfspi->mode & SPI_MODE_MOD) { + if ((cfspi->mode & 0xF0000000) == 0) + bus_setup |= + readl(&dspi->ctar[bus]) & 0x78000000; + else + bus_setup |= ((cfspi->mode & 0xF0000000) >> 1); + + /* PSCSCK, PASC, PDT */ + bus_setup |= (cfspi->mode & 0x0FC00000) >> 4; + /* CSSCK, ASC, DT */ + bus_setup |= (cfspi->mode & 0x000FFF00) >> 4; + } else { + bus_setup |= (readl(&dspi->ctar[bus]) & 0x78FCFFF0); + } + + cfspi->charbit = + ((readl(&dspi->ctar[bus]) & 0x78000000) == 0x78000000) ? 16 : 8;
- return &cfslave->slave; + setbits_be32(&dspi->ctar[bus], bus_setup); + + return 0; } -#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static inline void __cfspi_tx(struct coldfire_spi_priv *cfspi, + u32 ctrl, u16 data) { - if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8))) - return 1; - else - return 0; + while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 4) + ; + + writel(ctrl | data, &cfspi->regs->tfr); +} + +static inline u16 __cfspi_rx(struct coldfire_spi_priv *cfspi) +{ + while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0) + ; + + return readw(&cfspi->regs->rfr); +} + +static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen, + const void *dout, void *din, ulong flags) +{ + u16 *spi_rd16 = NULL, *spi_wr16 = NULL; + u8 *spi_rd = NULL, *spi_wr = NULL; + static u32 ctrl; + uint len = bitlen >> 3; + + if (cfspi->charbit == 16) { + bitlen >>= 1; + spi_wr16 = (u16 *)dout; + spi_rd16 = (u16 *)din; + } else { + spi_wr = (u8 *)dout; + spi_rd = (u8 *)din; + } + + if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN) + ctrl |= DSPI_TFR_CONT; + + ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16); + + if (len > 1) { + int tmp_len = len - 1; + + while (tmp_len--) { + if (dout) { + if (cfspi->charbit == 16) + __cfspi_tx(cfspi, ctrl, *spi_wr16++); + else + __cfspi_tx(cfspi, ctrl, *spi_wr++); + __cfspi_rx(cfspi); + } + + if (din) { + __cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16++ = __cfspi_rx(cfspi); + else + *spi_rd++ = __cfspi_rx(cfspi); + } + } + + len = 1; /* remaining byte */ + } + + if ((flags & SPI_XFER_END) == SPI_XFER_END) + ctrl &= ~DSPI_TFR_CONT; + + if (len) { + if (dout) { + if (cfspi->charbit == 16) + __cfspi_tx(cfspi, ctrl, *spi_wr16); + else + __cfspi_tx(cfspi, ctrl, *spi_wr); + __cfspi_rx(cfspi); + } + + if (din) { + __cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + if (cfspi->charbit == 16) + *spi_rd16 = __cfspi_rx(cfspi); + else + *spi_rd = __cfspi_rx(cfspi); + } + } else { + /* dummy read */ + __cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL); + __cfspi_rx(cfspi); + } + + return 0; }
void spi_init(void) { - cfspi_init(); }
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static int coldfire_spi_claim_bus(struct udevice *dev) +{ + struct udevice *bus = dev->parent; + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev); + + return cfspi_claim_bus(bus->seq, slave_plat->cs); +} + +static int coldfire_spi_release_bus(struct udevice *dev) { - struct cf_spi_slave *cfslave; + struct udevice *bus = dev->parent; + struct dm_spi_slave_platdata *slave_plat = + dev_get_parent_platdata(dev);
- if (!spi_cs_is_valid(bus, cs)) - return NULL; + cfspi_release_bus(bus->seq, slave_plat->cs);
- cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs); - if (!cfslave) - return NULL; + return 0; +}
- cfslave->baudrate = max_hz; +static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen, + const void *dout, void *din, + unsigned long flags) +{ + struct udevice *bus = dev_get_parent(dev); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
- /* specific setup */ - return cfspi_setup_slave(cfslave, mode); + return __spi_xfer(cfspi, slave_plat->cs, bitlen, dout, din, flags); }
-void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) { - struct cf_spi_slave *cfslave = to_cf_spi_slave(slave); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + cfspi->baudrate = max_hz;
- free(cfslave); + return __spi_set_speed(cfspi, bus->seq); }
-int spi_claim_bus(struct spi_slave *slave) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) { - return cfspi_claim_bus(slave->bus, slave->cs); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + + cfspi->mode = mode; + + return __spi_set_mode(cfspi, bus->seq); }
-void spi_release_bus(struct spi_slave *slave) +static int coldfire_spi_probe(struct udevice *bus) { - cfspi_release_bus(slave->bus, slave->cs); + struct coldfire_spi_platdata *plat = dev_get_platdata(bus); + struct coldfire_spi_priv *cfspi = dev_get_priv(bus); + int i; + + cfspi->regs = (struct dspi *)plat->regs_addr; + + cfspi->baudrate = plat->speed_hz; + cfspi->mode = plat->mode; + + for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) { + unsigned int ctar = 0; + + if (plat->ctar[i][0] == 0) + break; + + ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) | + DSPI_CTAR_PCSSCK(plat->ctar[i][1]) | + DSPI_CTAR_PASC(plat->ctar[i][2]) | + DSPI_CTAR_PDT(plat->ctar[i][3]) | + DSPI_CTAR_CSSCK(plat->ctar[i][4]) | + DSPI_CTAR_ASC(plat->ctar[i][5]) | + DSPI_CTAR_DT(plat->ctar[i][6]) | + DSPI_CTAR_BR(plat->ctar[i][7]); + + writel(ctar, &cfspi->regs->ctar[i]); + } + + __spi_init(cfspi); + + return 0; }
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, - void *din, unsigned long flags) +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus) { - return cfspi_xfer(slave, bitlen, dout, din, flags); + fdt_addr_t addr; + struct coldfire_spi_platdata *plat = bus->platdata; + const void *blob = gd->fdt_blob; + int node = dev_of_offset(bus); + int *ctar, len; + + addr = devfdt_get_addr(bus); + if (addr == FDT_ADDR_T_NONE) { + debug("DSPI: Can't get base address or size\n"); + return -ENOMEM; + } + plat->regs_addr = addr; + + plat->num_cs = fdtdec_get_int(blob, node, "num-cs", + MCF_DSPI_DEFAULT_MAX_CS); + + plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency", + MCF_DSPI_DEFAULT_SCK_FREQ); + + plat->mode = fdtdec_get_int(blob, node, "spi-mode", + MCF_DSPI_DEFAULT_MODE); + + memset(plat->ctar, 0, sizeof(plat->ctar)); + + ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len); + + if (ctar && len) { + int i, q, ctar_regs; + + ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS; + + if (ctar_regs > MAX_CTAR_REGS) + ctar_regs = MAX_CTAR_REGS; + + for (i = 0; i < ctar_regs; i++) { + for (q = 0; q < MAX_CTAR_FIELDS; q++) + plat->ctar[i][q] = *ctar++; + } + } + + debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n", + (void *)plat->regs_addr, + plat->speed_hz, plat->num_cs, plat->mode); + + return 0; } -#endif /* CONFIG_CMD_SPI */ +#endif + +static const struct dm_spi_ops coldfire_spi_ops = { + .claim_bus = coldfire_spi_claim_bus, + .release_bus = coldfire_spi_release_bus, + .xfer = coldfire_spi_xfer, + .set_speed = coldfire_spi_set_speed, + .set_mode = coldfire_spi_set_mode, +}; + +#if !CONFIG_IS_ENABLED(OF_PLATDATA) +static const struct udevice_id coldfire_spi_ids[] = { + { .compatible = "fsl,mcf-dspi" }, + { } +}; +#endif + +U_BOOT_DRIVER(coldfire_spi) = { + .name = "spi_coldfire", + .id = UCLASS_SPI, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .of_match = coldfire_spi_ids, +#endif + .probe = coldfire_spi_probe, + .ops = &coldfire_spi_ops, + .platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata), +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata, +#endif + .priv_auto_alloc_size = sizeof(struct coldfire_spi_priv), +}; +#endif /* CONFIG_CF_DSPI */ diff --git a/include/dm/platform_data/spi_coldfire.h b/include/dm/platform_data/spi_coldfire.h new file mode 100644 index 0000000000..8ad8eaedfd --- /dev/null +++ b/include/dm/platform_data/spi_coldfire.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (c) 2018 Angelo Dureghello angelo@sysam.it + */ + +#ifndef __spi_coldfire_h +#define __spi_coldfire_h + +#define MAX_CTAR_REGS 8 +#define MAX_CTAR_FIELDS 8 + +/* + * struct coldfire_spi_platdata - information about a coldfire spi module + * + * @regs_addr: base address for module registers + * @speed_hz: default SCK frequency + * @mode: default SPI mode + * @num_cs: number of DSPI chipselect signals + */ +struct coldfire_spi_platdata { + fdt_addr_t regs_addr; + uint speed_hz; + uint mode; + uint num_cs; + uint ctar[MAX_CTAR_REGS][MAX_CTAR_FIELDS]; +}; + +#endif /* __spi_coldfire_h */ +
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
Converting to driver model and removes non-dm code.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- removed non DM code part
- add default setup of CTAR registers
- add DT CTAR register setup support
Changes for v3:
- changed commit head
- removed spi_slave reference
- add #ifdefs for the case OF_PLATDATA is used
drivers/spi/cf_spi.c | 517 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 29 ++ 2 files changed, 352 insertions(+), 194 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h
This is a big tricky to review, but it looks right to me.
Reviewed-by: Simon Glass sjg@chromium.org
On Sun, Oct 14, 2018 at 1:00 PM Angelo Dureghello angelo@sysam.it wrote:
Converting to driver model and removes non-dm code.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- removed non DM code part
- add default setup of CTAR registers
- add DT CTAR register setup support
Changes for v3:
- changed commit head
- removed spi_slave reference
- add #ifdefs for the case OF_PLATDATA is used
drivers/spi/cf_spi.c | 517 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 29 ++ 2 files changed, 352 insertions(+), 194 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 522631cbbf..bc6a156df9 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,25 @@
- Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
- TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- Support for DM and DT, non-DM code removed.
- Copyright (C) 2018 Angelo Dureghello angelo@sysam.it
*/
- TODO: fsl_dspi.c should work as a driver for the DSPI module.
#include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> +#include <asm/io.h>
-struct cf_spi_slave {
struct spi_slave slave;+struct coldfire_spi_priv {
struct dspi *regs; uint baudrate;int mode; int charbit;};
@@ -38,14 +47,30 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{
return container_of(slave, struct cf_spi_slave, slave);-} +#define MCF_DSPI_MAX_CTAR_REGS 8
-static void cfspi_init(void) +/* Default values */ +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000 +#define MCF_DSPI_DEFAULT_MAX_CS 4 +#define MCF_DSPI_DEFAULT_MODE 0
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \DSPI_CTAR_PASC(0) | \DSPI_CTAR_PDT(0) | \DSPI_CTAR_CSSCK(0) | \DSPI_CTAR_ASC(0) | \DSPI_CTAR_DT(1) | \DSPI_CTAR_BR(6))+static void __spi_init(struct coldfire_spi_priv *cfspi) {
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs;int i;/* Default CTARs */for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]); cfspi_port_conf(); /* port configuration */@@ -53,128 +78,9 @@ static void cfspi_init(void) DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | DSPI_MCR_CRXF | DSPI_MCR_CTXF;
/* Default setting in platform configuration */-#ifdef CONFIG_SYS_DSPI_CTAR0
dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR1
dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR2
dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR3
dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR4
dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR5
dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR6
dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR7
dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;-#endif -}
-static void cfspi_tx(u32 ctrl, u16 data) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x0000F000) >= 4) ;dspi->tfr = (ctrl | data);}
-static u16 cfspi_rx(void) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x000000F0) == 0) ;return (dspi->rfr & 0xFFFF);-}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
void *din, ulong flags)-{
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl = 0;uint len = bitlen >> 3;if (cfslave->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *) dout;spi_rd16 = (u16 *) din;} else {spi_wr = (u8 *) dout;spi_rd = (u8 *) din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16++);elsecfspi_tx(ctrl, *spi_wr++);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16++ = cfspi_rx();else*spi_rd++ = cfspi_rx();}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16);elsecfspi_tx(ctrl, *spi_wr);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16 = cfspi_rx();else*spi_rd = cfspi_rx();}} else {/* dummy read */cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);cfspi_rx();}return 0;-}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
uint mode)+int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus) { /* * bit definition for mode: @@ -189,7 +95,7 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, * 11 - 8: Delay after transfer scaler * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST */
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8,@@ -199,56 +105,38 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
u32 bus_setup = 0;
u32 bus_setup;/* Read current setup */bus_setup = readl(&dspi->ctar[bus]); tmp = (prescaler[3] * scaler[15]); /* Maximum and minimum baudrate it can handle */
if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||(cfslave->baudrate < (gd->bus_clk / tmp))) {
if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||(cfspi->baudrate < (gd->bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
return NULL;
return -1; } /* Activate Double Baud when it exceed 1/4 the bus clk */
if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||(cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
if ((bus_setup & DSPI_CTAR_DBR) ||(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
if (mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (mode & SPI_MODE_MOD) {if ((mode & 0xF0000000) == 0)bus_setup |=dspi->ctar[cfslave->slave.bus] & 0x78000000;elsebus_setup |= ((mode & 0xF0000000) >> 1);
if (cfspi->mode & SPI_MODE_MOD) { /* * Check to see if it is enabled by default in platform * config, or manual setting passed by mode parameter */
if (mode & SPI_DBLRATE) {
if (cfspi->mode & SPI_DBLRATE) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */} elsebus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);cfslave->charbit =((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==0x78000000) ? 16 : 8;
} pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int);@@ -259,10 +147,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr);
if (tmp > cfslave->baudrate)diff = tmp - cfslave->baudrate;
if (tmp > cfspi->baudrate)diff = tmp - cfspi->baudrate; else
diff = cfslave->baudrate - tmp;
diff = cfspi->baudrate - tmp; if (diff < bestmatch) { bestmatch = diff;@@ -271,65 +159,306 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, } } }
bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f)); bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
dspi->ctar[cfslave->slave.bus] = bus_setup;
writel(bus_setup, &dspi->ctar[bus]);return 0;+}
+static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus) +{
struct dspi *dspi = cfspi->regs;u32 bus_setup = 0;if (cfspi->mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (cfspi->mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (cfspi->mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (cfspi->mode & SPI_MODE_MOD) {if ((cfspi->mode & 0xF0000000) == 0)bus_setup |=readl(&dspi->ctar[bus]) & 0x78000000;elsebus_setup |= ((cfspi->mode & 0xF0000000) >> 1);/* PSCSCK, PASC, PDT */bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;/* CSSCK, ASC, DT */bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;} else {bus_setup |= (readl(&dspi->ctar[bus]) & 0x78FCFFF0);}cfspi->charbit =((readl(&dspi->ctar[bus]) & 0x78000000) == 0x78000000) ? 16 : 8;
return &cfslave->slave;
setbits_be32(&dspi->ctar[bus], bus_setup);return 0;} -#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static inline void __cfspi_tx(struct coldfire_spi_priv *cfspi,
u32 ctrl, u16 data){
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))return 1;elsereturn 0;
while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 4);writel(ctrl | data, &cfspi->regs->tfr);+}
+static inline u16 __cfspi_rx(struct coldfire_spi_priv *cfspi) +{
while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0);return readw(&cfspi->regs->rfr);+}
Use wait_for bit calls instead of infine loops.
+static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen,
no need for __ we don't have non-dm code
const void *dout, void *din, ulong flags)+{
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl;uint len = bitlen >> 3;if (cfspi->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *)dout;spi_rd16 = (u16 *)din;} else {spi_wr = (u8 *)dout;spi_rd = (u8 *)din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16);
macros?
if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16++);else__cfspi_tx(cfspi, ctrl, *spi_wr++);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);
same here?
if (cfspi->charbit == 16)*spi_rd16++ = __cfspi_rx(cfspi);else*spi_rd++ = __cfspi_rx(cfspi);}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)
Why we need to check the macro again flags & SPI_XFER_END enogh?
ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16);else__cfspi_tx(cfspi, ctrl, *spi_wr);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);if (cfspi->charbit == 16)*spi_rd16 = __cfspi_rx(cfspi);else*spi_rd = __cfspi_rx(cfspi);}} else {/* dummy read */__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);__cfspi_rx(cfspi);
same here, no __
}return 0;}
void spi_init(void) {
cfspi_init();}
remove spi_init if not used, can be another patch.
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)+static int coldfire_spi_claim_bus(struct udevice *dev) +{
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);return cfspi_claim_bus(bus->seq, slave_plat->cs);+}
+static int coldfire_spi_release_bus(struct udevice *dev) {
struct cf_spi_slave *cfslave;
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);
if (!spi_cs_is_valid(bus, cs))return NULL;
cfspi_release_bus(bus->seq, slave_plat->cs);
cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);if (!cfslave)return NULL;
return 0;+}
cfslave->baudrate = max_hz;+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din,unsigned long flags)+{
struct udevice *bus = dev_get_parent(dev);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
/* specific setup */return cfspi_setup_slave(cfslave, mode);
return __spi_xfer(cfspi, slave_plat->cs, bitlen, dout, din, flags);}
-void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) {
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->baudrate = max_hz;
free(cfslave);
return __spi_set_speed(cfspi, bus->seq);
no __ and do it withough function.
}
-int spi_claim_bus(struct spi_slave *slave) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) {
return cfspi_claim_bus(slave->bus, slave->cs);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->mode = mode;return __spi_set_mode(cfspi, bus->seq);
same here.
}
-void spi_release_bus(struct spi_slave *slave) +static int coldfire_spi_probe(struct udevice *bus) {
cfspi_release_bus(slave->bus, slave->cs);
struct coldfire_spi_platdata *plat = dev_get_platdata(bus);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);int i;cfspi->regs = (struct dspi *)plat->regs_addr;cfspi->baudrate = plat->speed_hz;cfspi->mode = plat->mode;for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {unsigned int ctar = 0;if (plat->ctar[i][0] == 0)break;ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |DSPI_CTAR_PASC(plat->ctar[i][2]) |DSPI_CTAR_PDT(plat->ctar[i][3]) |DSPI_CTAR_CSSCK(plat->ctar[i][4]) |DSPI_CTAR_ASC(plat->ctar[i][5]) |DSPI_CTAR_DT(plat->ctar[i][6]) |DSPI_CTAR_BR(plat->ctar[i][7]);writel(ctar, &cfspi->regs->ctar[i]);}__spi_init(cfspi);
no __
return 0;}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
valid check is #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus) {
return cfspi_xfer(slave, bitlen, dout, din, flags);
fdt_addr_t addr;struct coldfire_spi_platdata *plat = bus->platdata;const void *blob = gd->fdt_blob;int node = dev_of_offset(bus);int *ctar, len;addr = devfdt_get_addr(bus);if (addr == FDT_ADDR_T_NONE) {debug("DSPI: Can't get base address or size\n");
no need this debug.
return -ENOMEM;}plat->regs_addr = addr;plat->num_cs = fdtdec_get_int(blob, node, "num-cs",MCF_DSPI_DEFAULT_MAX_CS);plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",MCF_DSPI_DEFAULT_SCK_FREQ);plat->mode = fdtdec_get_int(blob, node, "spi-mode",MCF_DSPI_DEFAULT_MODE);memset(plat->ctar, 0, sizeof(plat->ctar));ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);if (ctar && len) {int i, q, ctar_regs;ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;if (ctar_regs > MAX_CTAR_REGS)ctar_regs = MAX_CTAR_REGS;for (i = 0; i < ctar_regs; i++) {for (q = 0; q < MAX_CTAR_FIELDS; q++)plat->ctar[i][q] = *ctar++;}}debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",(void *)plat->regs_addr,plat->speed_hz, plat->num_cs, plat->mode);return 0;} -#endif /* CONFIG_CMD_SPI */ +#endif
+static const struct dm_spi_ops coldfire_spi_ops = {
.claim_bus = coldfire_spi_claim_bus,.release_bus = coldfire_spi_release_bus,.xfer = coldfire_spi_xfer,.set_speed = coldfire_spi_set_speed,.set_mode = coldfire_spi_set_mode,+};
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
group this check related code at once.
+static const struct udevice_id coldfire_spi_ids[] = {
{ .compatible = "fsl,mcf-dspi" },{ }+}; +#endif
+U_BOOT_DRIVER(coldfire_spi) = {
.name = "spi_coldfire",.id = UCLASS_SPI,+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,+#endif
.probe = coldfire_spi_probe,.ops = &coldfire_spi_ops,.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,+#endif
group it above ifdef and move in once place.
.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),+}; +#endif /* CONFIG_CF_DSPI */
I think we don't need this.
Apart from above, there are extern functions in this driver which are using spi code in arch area so better to move here or handle via respective drivers.
Hi Jagan,
was in the middle of a job switch recently, now i am looking back into the list. Seen your reminder, will fix the points in short.
Regards, Angelo
On Tue, Oct 23, 2018 at 04:58:22PM +0530, Jagan Teki wrote:
On Sun, Oct 14, 2018 at 1:00 PM Angelo Dureghello angelo@sysam.it wrote:
Converting to driver model and removes non-dm code.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- removed non DM code part
- add default setup of CTAR registers
- add DT CTAR register setup support
Changes for v3:
- changed commit head
- removed spi_slave reference
- add #ifdefs for the case OF_PLATDATA is used
drivers/spi/cf_spi.c | 517 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 29 ++ 2 files changed, 352 insertions(+), 194 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 522631cbbf..bc6a156df9 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,25 @@
- Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
- TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- Support for DM and DT, non-DM code removed.
- Copyright (C) 2018 Angelo Dureghello angelo@sysam.it
*/
- TODO: fsl_dspi.c should work as a driver for the DSPI module.
#include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> +#include <asm/io.h>
-struct cf_spi_slave {
struct spi_slave slave;+struct coldfire_spi_priv {
struct dspi *regs; uint baudrate;int mode; int charbit;};
@@ -38,14 +47,30 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{
return container_of(slave, struct cf_spi_slave, slave);-} +#define MCF_DSPI_MAX_CTAR_REGS 8
-static void cfspi_init(void) +/* Default values */ +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000 +#define MCF_DSPI_DEFAULT_MAX_CS 4 +#define MCF_DSPI_DEFAULT_MODE 0
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \DSPI_CTAR_PASC(0) | \DSPI_CTAR_PDT(0) | \DSPI_CTAR_CSSCK(0) | \DSPI_CTAR_ASC(0) | \DSPI_CTAR_DT(1) | \DSPI_CTAR_BR(6))+static void __spi_init(struct coldfire_spi_priv *cfspi) {
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs;int i;/* Default CTARs */for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]); cfspi_port_conf(); /* port configuration */@@ -53,128 +78,9 @@ static void cfspi_init(void) DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | DSPI_MCR_CRXF | DSPI_MCR_CTXF;
/* Default setting in platform configuration */-#ifdef CONFIG_SYS_DSPI_CTAR0
dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR1
dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR2
dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR3
dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR4
dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR5
dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR6
dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR7
dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;-#endif -}
-static void cfspi_tx(u32 ctrl, u16 data) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x0000F000) >= 4) ;dspi->tfr = (ctrl | data);}
-static u16 cfspi_rx(void) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x000000F0) == 0) ;return (dspi->rfr & 0xFFFF);-}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
void *din, ulong flags)-{
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl = 0;uint len = bitlen >> 3;if (cfslave->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *) dout;spi_rd16 = (u16 *) din;} else {spi_wr = (u8 *) dout;spi_rd = (u8 *) din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16++);elsecfspi_tx(ctrl, *spi_wr++);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16++ = cfspi_rx();else*spi_rd++ = cfspi_rx();}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16);elsecfspi_tx(ctrl, *spi_wr);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16 = cfspi_rx();else*spi_rd = cfspi_rx();}} else {/* dummy read */cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);cfspi_rx();}return 0;-}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
uint mode)+int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus) { /* * bit definition for mode: @@ -189,7 +95,7 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, * 11 - 8: Delay after transfer scaler * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST */
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8,@@ -199,56 +105,38 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
u32 bus_setup = 0;
u32 bus_setup;/* Read current setup */bus_setup = readl(&dspi->ctar[bus]); tmp = (prescaler[3] * scaler[15]); /* Maximum and minimum baudrate it can handle */
if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||(cfslave->baudrate < (gd->bus_clk / tmp))) {
if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||(cfspi->baudrate < (gd->bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
return NULL;
return -1; } /* Activate Double Baud when it exceed 1/4 the bus clk */
if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||(cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
if ((bus_setup & DSPI_CTAR_DBR) ||(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
if (mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (mode & SPI_MODE_MOD) {if ((mode & 0xF0000000) == 0)bus_setup |=dspi->ctar[cfslave->slave.bus] & 0x78000000;elsebus_setup |= ((mode & 0xF0000000) >> 1);
if (cfspi->mode & SPI_MODE_MOD) { /* * Check to see if it is enabled by default in platform * config, or manual setting passed by mode parameter */
if (mode & SPI_DBLRATE) {
if (cfspi->mode & SPI_DBLRATE) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */} elsebus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);cfslave->charbit =((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==0x78000000) ? 16 : 8;
} pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int);@@ -259,10 +147,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr);
if (tmp > cfslave->baudrate)diff = tmp - cfslave->baudrate;
if (tmp > cfspi->baudrate)diff = tmp - cfspi->baudrate; else
diff = cfslave->baudrate - tmp;
diff = cfspi->baudrate - tmp; if (diff < bestmatch) { bestmatch = diff;@@ -271,65 +159,306 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, } } }
bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f)); bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
dspi->ctar[cfslave->slave.bus] = bus_setup;
writel(bus_setup, &dspi->ctar[bus]);return 0;+}
+static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus) +{
struct dspi *dspi = cfspi->regs;u32 bus_setup = 0;if (cfspi->mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (cfspi->mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (cfspi->mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (cfspi->mode & SPI_MODE_MOD) {if ((cfspi->mode & 0xF0000000) == 0)bus_setup |=readl(&dspi->ctar[bus]) & 0x78000000;elsebus_setup |= ((cfspi->mode & 0xF0000000) >> 1);/* PSCSCK, PASC, PDT */bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;/* CSSCK, ASC, DT */bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;} else {bus_setup |= (readl(&dspi->ctar[bus]) & 0x78FCFFF0);}cfspi->charbit =((readl(&dspi->ctar[bus]) & 0x78000000) == 0x78000000) ? 16 : 8;
return &cfslave->slave;
setbits_be32(&dspi->ctar[bus], bus_setup);return 0;} -#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static inline void __cfspi_tx(struct coldfire_spi_priv *cfspi,
u32 ctrl, u16 data){
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))return 1;elsereturn 0;
while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 4);writel(ctrl | data, &cfspi->regs->tfr);+}
+static inline u16 __cfspi_rx(struct coldfire_spi_priv *cfspi) +{
while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0);return readw(&cfspi->regs->rfr);+}
Use wait_for bit calls instead of infine loops.
+static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen,
no need for __ we don't have non-dm code
const void *dout, void *din, ulong flags)+{
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl;uint len = bitlen >> 3;if (cfspi->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *)dout;spi_rd16 = (u16 *)din;} else {spi_wr = (u8 *)dout;spi_rd = (u8 *)din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16);macros?
if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16++);else__cfspi_tx(cfspi, ctrl, *spi_wr++);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);same here?
if (cfspi->charbit == 16)*spi_rd16++ = __cfspi_rx(cfspi);else*spi_rd++ = __cfspi_rx(cfspi);}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)Why we need to check the macro again flags & SPI_XFER_END enogh?
ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16);else__cfspi_tx(cfspi, ctrl, *spi_wr);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);if (cfspi->charbit == 16)*spi_rd16 = __cfspi_rx(cfspi);else*spi_rd = __cfspi_rx(cfspi);}} else {/* dummy read */__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);__cfspi_rx(cfspi);same here, no __
}return 0;}
void spi_init(void) {
cfspi_init();}
remove spi_init if not used, can be another patch.
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)+static int coldfire_spi_claim_bus(struct udevice *dev) +{
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);return cfspi_claim_bus(bus->seq, slave_plat->cs);+}
+static int coldfire_spi_release_bus(struct udevice *dev) {
struct cf_spi_slave *cfslave;
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);
if (!spi_cs_is_valid(bus, cs))return NULL;
cfspi_release_bus(bus->seq, slave_plat->cs);
cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);if (!cfslave)return NULL;
return 0;+}
cfslave->baudrate = max_hz;+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din,unsigned long flags)+{
struct udevice *bus = dev_get_parent(dev);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
/* specific setup */return cfspi_setup_slave(cfslave, mode);
return __spi_xfer(cfspi, slave_plat->cs, bitlen, dout, din, flags);}
-void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) {
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->baudrate = max_hz;
free(cfslave);
return __spi_set_speed(cfspi, bus->seq);no __ and do it withough function.
}
-int spi_claim_bus(struct spi_slave *slave) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) {
return cfspi_claim_bus(slave->bus, slave->cs);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->mode = mode;return __spi_set_mode(cfspi, bus->seq);same here.
}
-void spi_release_bus(struct spi_slave *slave) +static int coldfire_spi_probe(struct udevice *bus) {
cfspi_release_bus(slave->bus, slave->cs);
struct coldfire_spi_platdata *plat = dev_get_platdata(bus);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);int i;cfspi->regs = (struct dspi *)plat->regs_addr;cfspi->baudrate = plat->speed_hz;cfspi->mode = plat->mode;for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {unsigned int ctar = 0;if (plat->ctar[i][0] == 0)break;ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |DSPI_CTAR_PASC(plat->ctar[i][2]) |DSPI_CTAR_PDT(plat->ctar[i][3]) |DSPI_CTAR_CSSCK(plat->ctar[i][4]) |DSPI_CTAR_ASC(plat->ctar[i][5]) |DSPI_CTAR_DT(plat->ctar[i][6]) |DSPI_CTAR_BR(plat->ctar[i][7]);writel(ctar, &cfspi->regs->ctar[i]);}__spi_init(cfspi);no __
return 0;}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
valid check is #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus) {
return cfspi_xfer(slave, bitlen, dout, din, flags);
fdt_addr_t addr;struct coldfire_spi_platdata *plat = bus->platdata;const void *blob = gd->fdt_blob;int node = dev_of_offset(bus);int *ctar, len;addr = devfdt_get_addr(bus);if (addr == FDT_ADDR_T_NONE) {debug("DSPI: Can't get base address or size\n");no need this debug.
return -ENOMEM;}plat->regs_addr = addr;plat->num_cs = fdtdec_get_int(blob, node, "num-cs",MCF_DSPI_DEFAULT_MAX_CS);plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",MCF_DSPI_DEFAULT_SCK_FREQ);plat->mode = fdtdec_get_int(blob, node, "spi-mode",MCF_DSPI_DEFAULT_MODE);memset(plat->ctar, 0, sizeof(plat->ctar));ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);if (ctar && len) {int i, q, ctar_regs;ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;if (ctar_regs > MAX_CTAR_REGS)ctar_regs = MAX_CTAR_REGS;for (i = 0; i < ctar_regs; i++) {for (q = 0; q < MAX_CTAR_FIELDS; q++)plat->ctar[i][q] = *ctar++;}}debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",(void *)plat->regs_addr,plat->speed_hz, plat->num_cs, plat->mode);return 0;} -#endif /* CONFIG_CMD_SPI */ +#endif
+static const struct dm_spi_ops coldfire_spi_ops = {
.claim_bus = coldfire_spi_claim_bus,.release_bus = coldfire_spi_release_bus,.xfer = coldfire_spi_xfer,.set_speed = coldfire_spi_set_speed,.set_mode = coldfire_spi_set_mode,+};
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
group this check related code at once.
+static const struct udevice_id coldfire_spi_ids[] = {
{ .compatible = "fsl,mcf-dspi" },{ }+}; +#endif
+U_BOOT_DRIVER(coldfire_spi) = {
.name = "spi_coldfire",.id = UCLASS_SPI,+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,+#endif
.probe = coldfire_spi_probe,.ops = &coldfire_spi_ops,.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,+#endif
group it above ifdef and move in once place.
.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),+}; +#endif /* CONFIG_CF_DSPI */
I think we don't need this.
Apart from above, there are extern functions in this driver which are using spi code in arch area so better to move here or handle via respective drivers.
Hi Jagan,
still sorry for the delay, fixed all the points except 2, ready to send patch v4, please read below.
On Tue, Oct 23, 2018 at 04:58:22PM +0530, Jagan Teki wrote:
On Sun, Oct 14, 2018 at 1:00 PM Angelo Dureghello angelo@sysam.it wrote:
Converting to driver model and removes non-dm code.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- removed non DM code part
- add default setup of CTAR registers
- add DT CTAR register setup support
Changes for v3:
- changed commit head
- removed spi_slave reference
- add #ifdefs for the case OF_PLATDATA is used
drivers/spi/cf_spi.c | 517 +++++++++++++++--------- include/dm/platform_data/spi_coldfire.h | 29 ++ 2 files changed, 352 insertions(+), 194 deletions(-) create mode 100644 include/dm/platform_data/spi_coldfire.h
diff --git a/drivers/spi/cf_spi.c b/drivers/spi/cf_spi.c index 522631cbbf..bc6a156df9 100644 --- a/drivers/spi/cf_spi.c +++ b/drivers/spi/cf_spi.c @@ -6,16 +6,25 @@
- Copyright (C) 2004-2009 Freescale Semiconductor, Inc.
- TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- Support for DM and DT, non-DM code removed.
- Copyright (C) 2018 Angelo Dureghello angelo@sysam.it
*/
- TODO: fsl_dspi.c should work as a driver for the DSPI module.
#include <common.h> +#include <dm.h> +#include <dm/platform_data/spi_coldfire.h> #include <spi.h> #include <malloc.h> #include <asm/immap.h> +#include <asm/io.h>
-struct cf_spi_slave {
struct spi_slave slave;+struct coldfire_spi_priv {
struct dspi *regs; uint baudrate;int mode; int charbit;};
@@ -38,14 +47,30 @@ DECLARE_GLOBAL_DATA_PTR; #define SPI_MODE_MOD 0x00200000 #define SPI_DBLRATE 0x00100000
-static inline struct cf_spi_slave *to_cf_spi_slave(struct spi_slave *slave) -{
return container_of(slave, struct cf_spi_slave, slave);-} +#define MCF_DSPI_MAX_CTAR_REGS 8
-static void cfspi_init(void) +/* Default values */ +#define MCF_DSPI_DEFAULT_SCK_FREQ 10000000 +#define MCF_DSPI_DEFAULT_MAX_CS 4 +#define MCF_DSPI_DEFAULT_MODE 0
+#define MCF_DSPI_DEFAULT_CTAR (DSPI_CTAR_TRSZ(7) | \
DSPI_CTAR_PCSSCK_1CLK | \DSPI_CTAR_PASC(0) | \DSPI_CTAR_PDT(0) | \DSPI_CTAR_CSSCK(0) | \DSPI_CTAR_ASC(0) | \DSPI_CTAR_DT(1) | \DSPI_CTAR_BR(6))
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs;int i;/* Default CTARs */for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++)writel(MCF_DSPI_DEFAULT_CTAR, &dspi->ctar[i]); cfspi_port_conf(); /* port configuration */@@ -53,128 +78,9 @@ static void cfspi_init(void) DSPI_MCR_CSIS5 | DSPI_MCR_CSIS4 | DSPI_MCR_CSIS3 | DSPI_MCR_CSIS2 | DSPI_MCR_CSIS1 | DSPI_MCR_CSIS0 | DSPI_MCR_CRXF | DSPI_MCR_CTXF;
/* Default setting in platform configuration */-#ifdef CONFIG_SYS_DSPI_CTAR0
dspi->ctar[0] = CONFIG_SYS_DSPI_CTAR0;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR1
dspi->ctar[1] = CONFIG_SYS_DSPI_CTAR1;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR2
dspi->ctar[2] = CONFIG_SYS_DSPI_CTAR2;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR3
dspi->ctar[3] = CONFIG_SYS_DSPI_CTAR3;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR4
dspi->ctar[4] = CONFIG_SYS_DSPI_CTAR4;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR5
dspi->ctar[5] = CONFIG_SYS_DSPI_CTAR5;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR6
dspi->ctar[6] = CONFIG_SYS_DSPI_CTAR6;-#endif -#ifdef CONFIG_SYS_DSPI_CTAR7
dspi->ctar[7] = CONFIG_SYS_DSPI_CTAR7;-#endif -}
-static void cfspi_tx(u32 ctrl, u16 data) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x0000F000) >= 4) ;dspi->tfr = (ctrl | data);}
-static u16 cfspi_rx(void) -{
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;while ((dspi->sr & 0x000000F0) == 0) ;return (dspi->rfr & 0xFFFF);-}
-static int cfspi_xfer(struct spi_slave *slave, uint bitlen, const void *dout,
void *din, ulong flags)-{
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl = 0;uint len = bitlen >> 3;if (cfslave->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *) dout;spi_rd16 = (u16 *) din;} else {spi_wr = (u8 *) dout;spi_rd = (u8 *) din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << slave->cs) << 16);if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16++);elsecfspi_tx(ctrl, *spi_wr++);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16++ = cfspi_rx();else*spi_rd++ = cfspi_rx();}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout != NULL) {if (cfslave->charbit == 16)cfspi_tx(ctrl, *spi_wr16);elsecfspi_tx(ctrl, *spi_wr);cfspi_rx();}if (din != NULL) {cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);if (cfslave->charbit == 16)*spi_rd16 = cfspi_rx();else*spi_rd = cfspi_rx();}} else {/* dummy read */cfspi_tx(ctrl, CONFIG_SPI_IDLE_VAL);cfspi_rx();}return 0;-}
-static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave,
uint mode)+int __spi_set_speed(struct coldfire_spi_priv *cfspi, uint bus) { /* * bit definition for mode: @@ -189,7 +95,7 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, * 11 - 8: Delay after transfer scaler * 7 - 0: SPI_CPHA, SPI_CPOL, SPI_LSB_FIRST */
volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
struct dspi *dspi = cfspi->regs; int prescaler[] = { 2, 3, 5, 7 }; int scaler[] = { 2, 4, 6, 8,@@ -199,56 +105,38 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, }; int i, j, pbrcnt, brcnt, diff, tmp, dbr = 0; int best_i, best_j, bestmatch = 0x7FFFFFFF, baud_speed;
u32 bus_setup = 0;
u32 bus_setup;/* Read current setup */bus_setup = readl(&dspi->ctar[bus]); tmp = (prescaler[3] * scaler[15]); /* Maximum and minimum baudrate it can handle */
if ((cfslave->baudrate > (gd->bus_clk >> 1)) ||(cfslave->baudrate < (gd->bus_clk / tmp))) {
if ((cfspi->baudrate > (gd->bus_clk >> 1)) ||(cfspi->baudrate < (gd->bus_clk / tmp))) { printf("Exceed baudrate limitation: Max %d - Min %d\n", (int)(gd->bus_clk >> 1), (int)(gd->bus_clk / tmp));
return NULL;
return -1; } /* Activate Double Baud when it exceed 1/4 the bus clk */
if ((CONFIG_SYS_DSPI_CTAR0 & DSPI_CTAR_DBR) ||(cfslave->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) {
if ((bus_setup & DSPI_CTAR_DBR) ||(cfspi->baudrate > (gd->bus_clk / (prescaler[0] * scaler[0])))) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
if (mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (mode & SPI_MODE_MOD) {if ((mode & 0xF0000000) == 0)bus_setup |=dspi->ctar[cfslave->slave.bus] & 0x78000000;elsebus_setup |= ((mode & 0xF0000000) >> 1);
if (cfspi->mode & SPI_MODE_MOD) { /* * Check to see if it is enabled by default in platform * config, or manual setting passed by mode parameter */
if (mode & SPI_DBLRATE) {
if (cfspi->mode & SPI_DBLRATE) { bus_setup |= DSPI_CTAR_DBR; dbr = 1; }
bus_setup |= (mode & 0x0FC00000) >> 4; /* PSCSCK, PASC, PDT */bus_setup |= (mode & 0x000FFF00) >> 4; /* CSSCK, ASC, DT */} elsebus_setup |= (dspi->ctar[cfslave->slave.bus] & 0x78FCFFF0);cfslave->charbit =((dspi->ctar[cfslave->slave.bus] & 0x78000000) ==0x78000000) ? 16 : 8;
} pbrcnt = sizeof(prescaler) / sizeof(int); brcnt = sizeof(scaler) / sizeof(int);@@ -259,10 +147,10 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, for (j = 0; j < brcnt; j++) { tmp = (baud_speed / scaler[j]) * (1 + dbr);
if (tmp > cfslave->baudrate)diff = tmp - cfslave->baudrate;
if (tmp > cfspi->baudrate)diff = tmp - cfspi->baudrate; else
diff = cfslave->baudrate - tmp;
diff = cfspi->baudrate - tmp; if (diff < bestmatch) { bestmatch = diff;@@ -271,65 +159,306 @@ static struct spi_slave *cfspi_setup_slave(struct cf_spi_slave *cfslave, } } }
bus_setup &= ~(DSPI_CTAR_PBR(0x03) | DSPI_CTAR_BR(0x0f)); bus_setup |= (DSPI_CTAR_PBR(best_i) | DSPI_CTAR_BR(best_j));
dspi->ctar[cfslave->slave.bus] = bus_setup;
writel(bus_setup, &dspi->ctar[bus]);return 0;+}
+static int __spi_set_mode(struct coldfire_spi_priv *cfspi, uint bus) +{
struct dspi *dspi = cfspi->regs;u32 bus_setup = 0;if (cfspi->mode & SPI_CPOL)bus_setup |= DSPI_CTAR_CPOL;if (cfspi->mode & SPI_CPHA)bus_setup |= DSPI_CTAR_CPHA;if (cfspi->mode & SPI_LSB_FIRST)bus_setup |= DSPI_CTAR_LSBFE;/* Overwrite default value set in platform configuration file */if (cfspi->mode & SPI_MODE_MOD) {if ((cfspi->mode & 0xF0000000) == 0)bus_setup |=readl(&dspi->ctar[bus]) & 0x78000000;elsebus_setup |= ((cfspi->mode & 0xF0000000) >> 1);/* PSCSCK, PASC, PDT */bus_setup |= (cfspi->mode & 0x0FC00000) >> 4;/* CSSCK, ASC, DT */bus_setup |= (cfspi->mode & 0x000FFF00) >> 4;} else {bus_setup |= (readl(&dspi->ctar[bus]) & 0x78FCFFF0);}cfspi->charbit =((readl(&dspi->ctar[bus]) & 0x78000000) == 0x78000000) ? 16 : 8;
return &cfslave->slave;
setbits_be32(&dspi->ctar[bus], bus_setup);return 0;} -#endif /* CONFIG_CF_DSPI */
-#ifdef CONFIG_CMD_SPI -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +static inline void __cfspi_tx(struct coldfire_spi_priv *cfspi,
u32 ctrl, u16 data){
if (((cs >= 0) && (cs < 8)) && ((bus >= 0) && (bus < 8)))return 1;elsereturn 0;
while ((readl(&cfspi->regs->sr) & 0x0000F000) >= 4);writel(ctrl | data, &cfspi->regs->tfr);+}
+static inline u16 __cfspi_rx(struct coldfire_spi_priv *cfspi) +{
while ((readl(&cfspi->regs->sr) & 0x000000F0) == 0);return readw(&cfspi->regs->rfr);+}
Use wait_for bit calls instead of infine loops.
Seems i cannot use wait_for_bits for both the above cases.
The first case is a fifo level check ( >= 4) (on the other hand, it was also wrong as a chek, so fixed it), while the second case waits for at least one bit to 1, and so wait_for_bit can't apply too.
+static int __spi_xfer(struct coldfire_spi_priv *cfspi, uint cs, uint bitlen,
no need for __ we don't have non-dm code
done
const void *dout, void *din, ulong flags)+{
u16 *spi_rd16 = NULL, *spi_wr16 = NULL;u8 *spi_rd = NULL, *spi_wr = NULL;static u32 ctrl;uint len = bitlen >> 3;if (cfspi->charbit == 16) {bitlen >>= 1;spi_wr16 = (u16 *)dout;spi_rd16 = (u16 *)din;} else {spi_wr = (u8 *)dout;spi_rd = (u8 *)din;}if ((flags & SPI_XFER_BEGIN) == SPI_XFER_BEGIN)ctrl |= DSPI_TFR_CONT;ctrl = (ctrl & 0xFF000000) | ((1 << cs) << 16);macros?
done
if (len > 1) {int tmp_len = len - 1;while (tmp_len--) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16++);else__cfspi_tx(cfspi, ctrl, *spi_wr++);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);same here?
done
if (cfspi->charbit == 16)*spi_rd16++ = __cfspi_rx(cfspi);else*spi_rd++ = __cfspi_rx(cfspi);}}len = 1; /* remaining byte */}if ((flags & SPI_XFER_END) == SPI_XFER_END)Why we need to check the macro again flags & SPI_XFER_END enogh?
fixed
ctrl &= ~DSPI_TFR_CONT;if (len) {if (dout) {if (cfspi->charbit == 16)__cfspi_tx(cfspi, ctrl, *spi_wr16);else__cfspi_tx(cfspi, ctrl, *spi_wr);__cfspi_rx(cfspi);}if (din) {__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);if (cfspi->charbit == 16)*spi_rd16 = __cfspi_rx(cfspi);else*spi_rd = __cfspi_rx(cfspi);}} else {/* dummy read */__cfspi_tx(cfspi, ctrl, CONFIG_SPI_IDLE_VAL);__cfspi_rx(cfspi);same here, no __
done
}return 0;}
void spi_init(void) {
cfspi_init();}
remove spi_init if not used, can be another patch.
still cannot remove spi_init, left empty, but anyway moved cfspi_init() code inside _probe() and removed cfspi_init().
-struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)+static int coldfire_spi_claim_bus(struct udevice *dev) +{
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);return cfspi_claim_bus(bus->seq, slave_plat->cs);+}
+static int coldfire_spi_release_bus(struct udevice *dev) {
struct cf_spi_slave *cfslave;
struct udevice *bus = dev->parent;struct dm_spi_slave_platdata *slave_plat =dev_get_parent_platdata(dev);
if (!spi_cs_is_valid(bus, cs))return NULL;
cfspi_release_bus(bus->seq, slave_plat->cs);
cfslave = spi_alloc_slave(struct cf_spi_slave, bus, cs);if (!cfslave)return NULL;
return 0;+}
cfslave->baudrate = max_hz;+static int coldfire_spi_xfer(struct udevice *dev, unsigned int bitlen,
const void *dout, void *din,unsigned long flags)+{
struct udevice *bus = dev_get_parent(dev);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
/* specific setup */return cfspi_setup_slave(cfslave, mode);
return __spi_xfer(cfspi, slave_plat->cs, bitlen, dout, din, flags);}
-void spi_free_slave(struct spi_slave *slave) +static int coldfire_spi_set_speed(struct udevice *bus, uint max_hz) {
struct cf_spi_slave *cfslave = to_cf_spi_slave(slave);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->baudrate = max_hz;
free(cfslave);
return __spi_set_speed(cfspi, bus->seq);no __ and do it withough function.
}
-int spi_claim_bus(struct spi_slave *slave) +static int coldfire_spi_set_mode(struct udevice *bus, uint mode) {
return cfspi_claim_bus(slave->bus, slave->cs);
struct coldfire_spi_priv *cfspi = dev_get_priv(bus);cfspi->mode = mode;return __spi_set_mode(cfspi, bus->seq);same here.
done
}
-void spi_release_bus(struct spi_slave *slave) +static int coldfire_spi_probe(struct udevice *bus) {
cfspi_release_bus(slave->bus, slave->cs);
struct coldfire_spi_platdata *plat = dev_get_platdata(bus);struct coldfire_spi_priv *cfspi = dev_get_priv(bus);int i;cfspi->regs = (struct dspi *)plat->regs_addr;cfspi->baudrate = plat->speed_hz;cfspi->mode = plat->mode;for (i = 0; i < MCF_DSPI_MAX_CTAR_REGS; i++) {unsigned int ctar = 0;if (plat->ctar[i][0] == 0)break;ctar = DSPI_CTAR_TRSZ(plat->ctar[i][0]) |DSPI_CTAR_PCSSCK(plat->ctar[i][1]) |DSPI_CTAR_PASC(plat->ctar[i][2]) |DSPI_CTAR_PDT(plat->ctar[i][3]) |DSPI_CTAR_CSSCK(plat->ctar[i][4]) |DSPI_CTAR_ASC(plat->ctar[i][5]) |DSPI_CTAR_DT(plat->ctar[i][6]) |DSPI_CTAR_BR(plat->ctar[i][7]);writel(ctar, &cfspi->regs->ctar[i]);}__spi_init(cfspi);no __
done
return 0;}
-int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
void *din, unsigned long flags)+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
valid check is #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA)
done
+static int coldfire_dspi_ofdata_to_platdata(struct udevice *bus) {
return cfspi_xfer(slave, bitlen, dout, din, flags);
fdt_addr_t addr;struct coldfire_spi_platdata *plat = bus->platdata;const void *blob = gd->fdt_blob;int node = dev_of_offset(bus);int *ctar, len;addr = devfdt_get_addr(bus);if (addr == FDT_ADDR_T_NONE) {debug("DSPI: Can't get base address or size\n");no need this debug.
done
return -ENOMEM;}plat->regs_addr = addr;plat->num_cs = fdtdec_get_int(blob, node, "num-cs",MCF_DSPI_DEFAULT_MAX_CS);plat->speed_hz = fdtdec_get_int(blob, node, "spi-max-frequency",MCF_DSPI_DEFAULT_SCK_FREQ);plat->mode = fdtdec_get_int(blob, node, "spi-mode",MCF_DSPI_DEFAULT_MODE);memset(plat->ctar, 0, sizeof(plat->ctar));ctar = (int *)fdt_getprop(blob, node, "ctar-params", &len);if (ctar && len) {int i, q, ctar_regs;ctar_regs = len / sizeof(unsigned int) / MAX_CTAR_FIELDS;if (ctar_regs > MAX_CTAR_REGS)ctar_regs = MAX_CTAR_REGS;for (i = 0; i < ctar_regs; i++) {for (q = 0; q < MAX_CTAR_FIELDS; q++)plat->ctar[i][q] = *ctar++;}}debug("DSPI: regs=%pa, max-frequency=%d, num-cs=%d, mode=%d\n",(void *)plat->regs_addr,plat->speed_hz, plat->num_cs, plat->mode);return 0;} -#endif /* CONFIG_CMD_SPI */ +#endif
+static const struct dm_spi_ops coldfire_spi_ops = {
.claim_bus = coldfire_spi_claim_bus,.release_bus = coldfire_spi_release_bus,.xfer = coldfire_spi_xfer,.set_speed = coldfire_spi_set_speed,.set_mode = coldfire_spi_set_mode,+};
+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
group this check related code at once.
done
+static const struct udevice_id coldfire_spi_ids[] = {
{ .compatible = "fsl,mcf-dspi" },{ }+}; +#endif
+U_BOOT_DRIVER(coldfire_spi) = {
.name = "spi_coldfire",.id = UCLASS_SPI,+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.of_match = coldfire_spi_ids,+#endif
.probe = coldfire_spi_probe,.ops = &coldfire_spi_ops,.platdata_auto_alloc_size = sizeof(struct coldfire_spi_platdata),+#if !CONFIG_IS_ENABLED(OF_PLATDATA)
.ofdata_to_platdata = coldfire_dspi_ofdata_to_platdata,+#endif
group it above ifdef and move in once place.
done
.priv_auto_alloc_size = sizeof(struct coldfire_spi_priv),+}; +#endif /* CONFIG_CF_DSPI */
I think we don't need this.
done
Apart from above, there are extern functions in this driver which are using spi code in arch area so better to move here or handle via respective drivers.
I had a look but proper place for those 3 functions seems
/u-boot-coldfire/arch/m68k/cpu/mcf5445x/cpu_init.c
since there are some cpu sub-family #ifdef checks there. Just let me know, i can move them here anyway.
Regards, Angelo
This patch adds devicetree support to the mcfuart.c driver and removes non DM code.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - remove non DM code Changes for v3: - none --- drivers/serial/mcfuart.c | 106 +++++++++++---------------------------- 1 file changed, 28 insertions(+), 78 deletions(-)
diff --git a/drivers/serial/mcfuart.c b/drivers/serial/mcfuart.c index 1371049de2..066e5a18d8 100644 --- a/drivers/serial/mcfuart.c +++ b/drivers/serial/mcfuart.c @@ -5,6 +5,9 @@ * * Modified to add device model (DM) support * (C) Copyright 2015 Angelo Dureghello angelo@sysam.it + * + * Modified to add DM and fdt support, removed non DM code + * (C) Copyright 2018 Angelo Dureghello angelo@sysam.it */
/* @@ -78,83 +81,6 @@ static void mcf_serial_setbrg_common(uart_t *uart, int baudrate) writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr); }
-#ifndef CONFIG_DM_SERIAL - -static int mcf_serial_init(void) -{ - uart_t *uart_base; - int port_idx; - - uart_base = (uart_t *)CONFIG_SYS_UART_BASE; - port_idx = CONFIG_SYS_UART_PORT; - - return mcf_serial_init_common(uart_base, port_idx, gd->baudrate); -} - -static void mcf_serial_putc(const char c) -{ - uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; - - if (c == '\n') - serial_putc('\r'); - - /* Wait for last character to go. */ - while (!(readb(&uart->usr) & UART_USR_TXRDY)) - ; - - writeb(c, &uart->utb); -} - -static int mcf_serial_getc(void) -{ - uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; - - /* Wait for a character to arrive. */ - while (!(readb(&uart->usr) & UART_USR_RXRDY)) - ; - - return readb(&uart->urb); -} - -static void mcf_serial_setbrg(void) -{ - uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; - - mcf_serial_setbrg_common(uart, gd->baudrate); -} - -static int mcf_serial_tstc(void) -{ - uart_t *uart = (uart_t *)CONFIG_SYS_UART_BASE; - - return readb(&uart->usr) & UART_USR_RXRDY; -} - -static struct serial_device mcf_serial_drv = { - .name = "mcf_serial", - .start = mcf_serial_init, - .stop = NULL, - .setbrg = mcf_serial_setbrg, - .putc = mcf_serial_putc, - .puts = default_serial_puts, - .getc = mcf_serial_getc, - .tstc = mcf_serial_tstc, -}; - -void mcf_serial_initialize(void) -{ - serial_register(&mcf_serial_drv); -} - -__weak struct serial_device *default_serial_console(void) -{ - return &mcf_serial_drv; -} - -#endif - -#ifdef CONFIG_DM_SERIAL - static int coldfire_serial_probe(struct udevice *dev) { struct coldfire_serial_platdata *plat = dev->platdata; @@ -212,6 +138,23 @@ static int coldfire_serial_pending(struct udevice *dev, bool input) return 0; }
+static int coldfire_ofdata_to_platdata(struct udevice *dev) +{ + struct coldfire_serial_platdata *plat = dev_get_platdata(dev); + fdt_addr_t addr_base; + + addr_base = devfdt_get_addr(dev); + if (addr_base == FDT_ADDR_T_NONE) + return -ENODEV; + + plat->base = (uint32_t)addr_base; + + plat->port = dev->seq; + plat->baudrate = gd->baudrate; + + return 0; +} + static const struct dm_serial_ops coldfire_serial_ops = { .putc = coldfire_serial_putc, .pending = coldfire_serial_pending, @@ -219,11 +162,18 @@ static const struct dm_serial_ops coldfire_serial_ops = { .setbrg = coldfire_serial_setbrg, };
+static const struct udevice_id coldfire_serial_ids[] = { + { .compatible = "fsl,mcf-uart" }, + { } +}; + U_BOOT_DRIVER(serial_coldfire) = { .name = "serial_coldfire", .id = UCLASS_SERIAL, + .of_match = coldfire_serial_ids, + .ofdata_to_platdata = coldfire_ofdata_to_platdata, + .platdata_auto_alloc_size = sizeof(struct coldfire_serial_platdata), .probe = coldfire_serial_probe, .ops = &coldfire_serial_ops, .flags = DM_FLAG_PRE_RELOC, }; -#endif
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds devicetree support to the mcfuart.c driver and removes non DM code.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- remove non DM code
Changes for v3:
- none
drivers/serial/mcfuart.c | 106 +++++++++++---------------------------- 1 file changed, 28 insertions(+), 78 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Does this not break the build bisectability? If it does, you might need to make a config change here too.
This patch adds missing CONFIG_MCFUART to Kconfig.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - better Kconfig help Changes for v3: - none --- drivers/serial/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 597db4b9cb..1ebeaa3936 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -520,6 +520,15 @@ config MVEBU_A3700_UART Choose this option to add support for UART driver on the Marvell Armada 3700 SoC. The base address is configured via DT.
+config MCFUART + bool "Freescale ColdFire UART support" + default n + help + Choose this option to add support for UART driver on the ColdFire + SoC's family. The serial communication channel provides a full-duplex + asynchronous/synchronous receiver and transmitter deriving an + operating frequency from the internal bus clock or an external clock. + config MXC_UART bool "IMX serial port support" depends on MX5 || MX6
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds missing CONFIG_MCFUART to Kconfig.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- better Kconfig help
Changes for v3:
- none
drivers/serial/Kconfig | 9 +++++++++ 1 file changed, 9 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
(you don't need 'default n')
This patch adds fdt support to the m68k architecture.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - add OF_CONTROL, DM and DM_SERIAL as default config options for all cpu families Changes for v3: - none --- arch/Kconfig | 1 + arch/m68k/Kconfig | 33 +++++++++++++++++++++++++++++++++ arch/m68k/cpu/u-boot.lds | 2 ++ 3 files changed, 36 insertions(+)
diff --git a/arch/Kconfig b/arch/Kconfig index 1f2f407d64..569216eadd 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -28,6 +28,7 @@ config M68K select HAVE_PRIVATE_LIBGCC select SYS_BOOT_GET_CMDLINE select SYS_BOOT_GET_KBD + select SUPPORT_OF_CONTROL
config MICROBLAZE bool "MicroBlaze architecture" diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig index 1f6df5c870..fef108105b 100644 --- a/arch/m68k/Kconfig +++ b/arch/m68k/Kconfig @@ -6,36 +6,69 @@ config SYS_ARCH
# processor family config MCF520x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF52x2 + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF523x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF530x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF5301x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF532x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF537x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF5441x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF5445x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF5227x + select OF_CONTROL + select DM + select DM_SERIAL bool
config MCF547x_8x + select OF_CONTROL + select DM + select DM_SERIAL bool
# processor type diff --git a/arch/m68k/cpu/u-boot.lds b/arch/m68k/cpu/u-boot.lds index 96451208e5..e61630db20 100644 --- a/arch/m68k/cpu/u-boot.lds +++ b/arch/m68k/cpu/u-boot.lds @@ -75,6 +75,8 @@ SECTIONS . = ALIGN(256); __init_end = .;
+ _end = .; + __bss_start = .; .bss (NOLOAD) : {
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds fdt support to the m68k architecture.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- add OF_CONTROL, DM and DM_SERIAL as default config options for all cpu families
Changes for v3:
- none
arch/Kconfig | 1 + arch/m68k/Kconfig | 33 +++++++++++++++++++++++++++++++++ arch/m68k/cpu/u-boot.lds | 2 ++ 3 files changed, 36 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
This patch adds basic dts files for all the m68k boards.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - none --- arch/m68k/dts/M5208EVBE.dts | 22 +++++++ arch/m68k/dts/M52277EVB.dts | 25 ++++++++ arch/m68k/dts/M52277EVB_stmicro.dts | 22 +++++++ arch/m68k/dts/M5235EVB.dts | 22 +++++++ arch/m68k/dts/M5235EVB_Flash32.dts | 22 +++++++ arch/m68k/dts/M5249EVB.dts | 22 +++++++ arch/m68k/dts/M5253DEMO.dts | 22 +++++++ arch/m68k/dts/M5272C3.dts | 22 +++++++ arch/m68k/dts/M5275EVB.dts | 22 +++++++ arch/m68k/dts/M5282EVB.dts | 22 +++++++ arch/m68k/dts/M53017EVB.dts | 22 +++++++ arch/m68k/dts/M5329AFEE.dts | 22 +++++++ arch/m68k/dts/M5329BFEE.dts | 22 +++++++ arch/m68k/dts/M5373EVB.dts | 22 +++++++ arch/m68k/dts/M54418TWR.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_mii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_rmii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_serial_mii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_serial_rmii.dts | 25 ++++++++ arch/m68k/dts/M54451EVB.dts | 25 ++++++++ arch/m68k/dts/M54451EVB_stmicro.dts | 25 ++++++++ arch/m68k/dts/M54455EVB.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_a66.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_i66.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_intel.dts | 26 +++++++++ arch/m68k/dts/M54455EVB_stm33.dts | 25 ++++++++ arch/m68k/dts/M5475AFE.dts | 13 +++++ arch/m68k/dts/M5475BFE.dts | 13 +++++ arch/m68k/dts/M5475CFE.dts | 13 +++++ arch/m68k/dts/M5475DFE.dts | 13 +++++ arch/m68k/dts/M5475EFE.dts | 13 +++++ arch/m68k/dts/M5475FFE.dts | 13 +++++ arch/m68k/dts/M5475GFE.dts | 13 +++++ arch/m68k/dts/M5485AFE.dts | 17 ++++++ arch/m68k/dts/M5485BFE.dts | 17 ++++++ arch/m68k/dts/M5485CFE.dts | 17 ++++++ arch/m68k/dts/M5485DFE.dts | 17 ++++++ arch/m68k/dts/M5485EFE.dts | 17 ++++++ arch/m68k/dts/M5485FFE.dts | 17 ++++++ arch/m68k/dts/M5485GFE.dts | 17 ++++++ arch/m68k/dts/M5485HFE.dts | 17 ++++++ arch/m68k/dts/Makefile | 58 +++++++++++++++++++ arch/m68k/dts/amcore.dts | 22 +++++++ arch/m68k/dts/astro_mcf5373l.dts | 22 +++++++ arch/m68k/dts/cobra5272.dts | 22 +++++++ arch/m68k/dts/eb_cpu5282.dts | 22 +++++++ arch/m68k/dts/eb_cpu5282_internal.dts | 22 +++++++ arch/m68k/dts/stmark2.dts | 34 +++++++++++ 49 files changed, 1066 insertions(+) create mode 100644 arch/m68k/dts/M5208EVBE.dts create mode 100644 arch/m68k/dts/M52277EVB.dts create mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts create mode 100644 arch/m68k/dts/M5235EVB.dts create mode 100644 arch/m68k/dts/M5235EVB_Flash32.dts create mode 100644 arch/m68k/dts/M5249EVB.dts create mode 100644 arch/m68k/dts/M5253DEMO.dts create mode 100644 arch/m68k/dts/M5272C3.dts create mode 100644 arch/m68k/dts/M5275EVB.dts create mode 100644 arch/m68k/dts/M5282EVB.dts create mode 100644 arch/m68k/dts/M53017EVB.dts create mode 100644 arch/m68k/dts/M5329AFEE.dts create mode 100644 arch/m68k/dts/M5329BFEE.dts create mode 100644 arch/m68k/dts/M5373EVB.dts create mode 100644 arch/m68k/dts/M54418TWR.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_rmii.dts create mode 100644 arch/m68k/dts/M54451EVB.dts create mode 100644 arch/m68k/dts/M54451EVB_stmicro.dts create mode 100644 arch/m68k/dts/M54455EVB.dts create mode 100644 arch/m68k/dts/M54455EVB_a66.dts create mode 100644 arch/m68k/dts/M54455EVB_i66.dts create mode 100644 arch/m68k/dts/M54455EVB_intel.dts create mode 100644 arch/m68k/dts/M54455EVB_stm33.dts create mode 100644 arch/m68k/dts/M5475AFE.dts create mode 100644 arch/m68k/dts/M5475BFE.dts create mode 100644 arch/m68k/dts/M5475CFE.dts create mode 100644 arch/m68k/dts/M5475DFE.dts create mode 100644 arch/m68k/dts/M5475EFE.dts create mode 100644 arch/m68k/dts/M5475FFE.dts create mode 100644 arch/m68k/dts/M5475GFE.dts create mode 100644 arch/m68k/dts/M5485AFE.dts create mode 100644 arch/m68k/dts/M5485BFE.dts create mode 100644 arch/m68k/dts/M5485CFE.dts create mode 100644 arch/m68k/dts/M5485DFE.dts create mode 100644 arch/m68k/dts/M5485EFE.dts create mode 100644 arch/m68k/dts/M5485FFE.dts create mode 100644 arch/m68k/dts/M5485GFE.dts create mode 100644 arch/m68k/dts/M5485HFE.dts create mode 100644 arch/m68k/dts/Makefile create mode 100644 arch/m68k/dts/amcore.dts create mode 100644 arch/m68k/dts/astro_mcf5373l.dts create mode 100644 arch/m68k/dts/cobra5272.dts create mode 100644 arch/m68k/dts/eb_cpu5282.dts create mode 100644 arch/m68k/dts/eb_cpu5282_internal.dts create mode 100644 arch/m68k/dts/stmark2.dts
diff --git a/arch/m68k/dts/M5208EVBE.dts b/arch/m68k/dts/M5208EVBE.dts new file mode 100644 index 0000000000..e78513f3b8 --- /dev/null +++ b/arch/m68k/dts/M5208EVBE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5208.dtsi" + +/ { + model = "Freescale M5208EVBE"; + compatible = "fsl,M5208EVBE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M52277EVB.dts b/arch/m68k/dts/M52277EVB.dts new file mode 100644 index 0000000000..a2210c8811 --- /dev/null +++ b/arch/m68k/dts/M52277EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5227x.dtsi" + +/ { + model = "Freescale M52277EVB"; + compatible = "fsl,M52277EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M52277EVB_stmicro.dts b/arch/m68k/dts/M52277EVB_stmicro.dts new file mode 100644 index 0000000000..5fd3ca5efd --- /dev/null +++ b/arch/m68k/dts/M52277EVB_stmicro.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5227x.dtsi" + +/ { + model = "Freescale M52277_stmicro"; + compatible = "fsl,M52277_stmicro"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5235EVB.dts b/arch/m68k/dts/M5235EVB.dts new file mode 100644 index 0000000000..1a32539323 --- /dev/null +++ b/arch/m68k/dts/M5235EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf523x.dtsi" + +/ { + model = "Freescale M5235EVB"; + compatible = "fsl,M5235EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5235EVB_Flash32.dts b/arch/m68k/dts/M5235EVB_Flash32.dts new file mode 100644 index 0000000000..fcbffb23f5 --- /dev/null +++ b/arch/m68k/dts/M5235EVB_Flash32.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf523x.dtsi" + +/ { + model = "Freescale M5235EVB_Flash32"; + compatible = "fsl,M5235EVB_Flash32"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5249EVB.dts b/arch/m68k/dts/M5249EVB.dts new file mode 100644 index 0000000000..b2a1be9090 --- /dev/null +++ b/arch/m68k/dts/M5249EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5249.dtsi" + +/ { + model = "Freescale M5249EVB"; + compatible = "fsl,M5249EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5253DEMO.dts b/arch/m68k/dts/M5253DEMO.dts new file mode 100644 index 0000000000..7ebaa9a2e0 --- /dev/null +++ b/arch/m68k/dts/M5253DEMO.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5253.dtsi" + +/ { + model = "Freescale M5253DEMO"; + compatible = "fsl,M5253DEMO"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5272C3.dts b/arch/m68k/dts/M5272C3.dts new file mode 100644 index 0000000000..6efb8a4cc5 --- /dev/null +++ b/arch/m68k/dts/M5272C3.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5272.dtsi" + +/ { + model = "Freescale M5272C3"; + compatible = "fsl,M5272C3"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5275EVB.dts b/arch/m68k/dts/M5275EVB.dts new file mode 100644 index 0000000000..cd9eb7d145 --- /dev/null +++ b/arch/m68k/dts/M5275EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5275.dtsi" + +/ { + model = "Freescale M5275EVB"; + compatible = "fsl,M5275EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5282EVB.dts b/arch/m68k/dts/M5282EVB.dts new file mode 100644 index 0000000000..9527caafc2 --- /dev/null +++ b/arch/m68k/dts/M5282EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "Freescale M5282EVB"; + compatible = "fsl,M5282EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M53017EVB.dts b/arch/m68k/dts/M53017EVB.dts new file mode 100644 index 0000000000..b267488e0f --- /dev/null +++ b/arch/m68k/dts/M53017EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5301x.dtsi" + +/ { + model = "Freescale M53017EVB"; + compatible = "fsl,M53017EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5329AFEE.dts b/arch/m68k/dts/M5329AFEE.dts new file mode 100644 index 0000000000..7d121d68e7 --- /dev/null +++ b/arch/m68k/dts/M5329AFEE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5329.dtsi" + +/ { + model = "Freescale M5329AFEE"; + compatible = "fsl,M5329AFEE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5329BFEE.dts b/arch/m68k/dts/M5329BFEE.dts new file mode 100644 index 0000000000..cd087b6ea6 --- /dev/null +++ b/arch/m68k/dts/M5329BFEE.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5329.dtsi" + +/ { + model = "Freescale M5329BFEE"; + compatible = "fsl,M5329BFEE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M5373EVB.dts b/arch/m68k/dts/M5373EVB.dts new file mode 100644 index 0000000000..930f911d4a --- /dev/null +++ b/arch/m68k/dts/M5373EVB.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf537x.dtsi" + +/ { + model = "Freescale M5373EVB"; + compatible = "fsl,M5373EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/M54418TWR.dts b/arch/m68k/dts/M54418TWR.dts new file mode 100644 index 0000000000..7765c7abbb --- /dev/null +++ b/arch/m68k/dts/M54418TWR.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR"; + compatible = "fsl,M54418TWR"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_mii.dts b/arch/m68k/dts/M54418TWR_nand_mii.dts new file mode 100644 index 0000000000..9b1cb85325 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_mii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_mii"; + compatible = "fsl,M54418TWR_nand_mii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii.dts b/arch/m68k/dts/M54418TWR_nand_rmii.dts new file mode 100644 index 0000000000..824a66af48 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_rmii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_rmii"; + compatible = "fsl,M54418TWR_nand_rmii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts new file mode 100644 index 0000000000..74fa197ea9 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_nand_rmii_lowfreq"; + compatible = "fsl,M54418TWR_nand_rmii_lowfreq"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_mii.dts b/arch/m68k/dts/M54418TWR_serial_mii.dts new file mode 100644 index 0000000000..22f27b5612 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_serial_mii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_serial_mii"; + compatible = "fsl,M54418TWR_serial_mii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54418TWR_serial_rmii.dts b/arch/m68k/dts/M54418TWR_serial_rmii.dts new file mode 100644 index 0000000000..0ddefd9da2 --- /dev/null +++ b/arch/m68k/dts/M54418TWR_serial_rmii.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Freescale M54418TWR_serial_rmii"; + compatible = "fsl,M54418TWR_serial_rmii"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54451EVB.dts b/arch/m68k/dts/M54451EVB.dts new file mode 100644 index 0000000000..b57bfea2cb --- /dev/null +++ b/arch/m68k/dts/M54451EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54451EVB"; + compatible = "fsl,M54451EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54451EVB_stmicro.dts b/arch/m68k/dts/M54451EVB_stmicro.dts new file mode 100644 index 0000000000..9a088e16d0 --- /dev/null +++ b/arch/m68k/dts/M54451EVB_stmicro.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54451EVB_stmicro"; + compatible = "fsl,M54451EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB.dts b/arch/m68k/dts/M54455EVB.dts new file mode 100644 index 0000000000..dd11181033 --- /dev/null +++ b/arch/m68k/dts/M54455EVB.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB"; + compatible = "fsl,M54455EVB"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_a66.dts b/arch/m68k/dts/M54455EVB_a66.dts new file mode 100644 index 0000000000..70d544b72d --- /dev/null +++ b/arch/m68k/dts/M54455EVB_a66.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_a66"; + compatible = "fsl,M54455EVB_a66"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_i66.dts b/arch/m68k/dts/M54455EVB_i66.dts new file mode 100644 index 0000000000..b37a87213f --- /dev/null +++ b/arch/m68k/dts/M54455EVB_i66.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_i66"; + compatible = "fsl,M54455EVB_i66"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M54455EVB_intel.dts b/arch/m68k/dts/M54455EVB_intel.dts new file mode 100644 index 0000000000..c92228fc8b --- /dev/null +++ b/arch/m68k/dts/M54455EVB_intel.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_intel"; + compatible = "fsl,M5275EVB_intel"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; + diff --git a/arch/m68k/dts/M54455EVB_stm33.dts b/arch/m68k/dts/M54455EVB_stm33.dts new file mode 100644 index 0000000000..9e467f94a1 --- /dev/null +++ b/arch/m68k/dts/M54455EVB_stm33.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5445x.dtsi" + +/ { + model = "Freescale M54455EVB_stm33"; + compatible = "fsl,M5275EVB_stm33"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + status = "okay"; +}; diff --git a/arch/m68k/dts/M5475AFE.dts b/arch/m68k/dts/M5475AFE.dts new file mode 100644 index 0000000000..0c0a79befa --- /dev/null +++ b/arch/m68k/dts/M5475AFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475AFE"; + compatible = "fsl,M5475AFE"; +}; + diff --git a/arch/m68k/dts/M5475BFE.dts b/arch/m68k/dts/M5475BFE.dts new file mode 100644 index 0000000000..c4d14097cd --- /dev/null +++ b/arch/m68k/dts/M5475BFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475BFE"; + compatible = "fsl,M5475BFE"; +}; + diff --git a/arch/m68k/dts/M5475CFE.dts b/arch/m68k/dts/M5475CFE.dts new file mode 100644 index 0000000000..4c92c332ba --- /dev/null +++ b/arch/m68k/dts/M5475CFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475CFE"; + compatible = "fsl,M5475CFE"; +}; + diff --git a/arch/m68k/dts/M5475DFE.dts b/arch/m68k/dts/M5475DFE.dts new file mode 100644 index 0000000000..c41c1b3c12 --- /dev/null +++ b/arch/m68k/dts/M5475DFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475DFE"; + compatible = "fsl,M5475DFE"; +}; + diff --git a/arch/m68k/dts/M5475EFE.dts b/arch/m68k/dts/M5475EFE.dts new file mode 100644 index 0000000000..5a920b241a --- /dev/null +++ b/arch/m68k/dts/M5475EFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475EFE"; + compatible = "fsl,M5475EFE"; +}; + diff --git a/arch/m68k/dts/M5475FFE.dts b/arch/m68k/dts/M5475FFE.dts new file mode 100644 index 0000000000..d312a6ae8d --- /dev/null +++ b/arch/m68k/dts/M5475FFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475FFE"; + compatible = "fsl,M5475FFE"; +}; + diff --git a/arch/m68k/dts/M5475GFE.dts b/arch/m68k/dts/M5475GFE.dts new file mode 100644 index 0000000000..9e794dafa6 --- /dev/null +++ b/arch/m68k/dts/M5475GFE.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5475GFE"; + compatible = "fsl,M5475GFE"; +}; + diff --git a/arch/m68k/dts/M5485AFE.dts b/arch/m68k/dts/M5485AFE.dts new file mode 100644 index 0000000000..3466751174 --- /dev/null +++ b/arch/m68k/dts/M5485AFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485AFE"; + compatible = "fsl,M5485AFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485BFE.dts b/arch/m68k/dts/M5485BFE.dts new file mode 100644 index 0000000000..6d48795a4d --- /dev/null +++ b/arch/m68k/dts/M5485BFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485BFE"; + compatible = "fsl,M5485BFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485CFE.dts b/arch/m68k/dts/M5485CFE.dts new file mode 100644 index 0000000000..d1a7d9d383 --- /dev/null +++ b/arch/m68k/dts/M5485CFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485CFE"; + compatible = "fsl,M5485CFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485DFE.dts b/arch/m68k/dts/M5485DFE.dts new file mode 100644 index 0000000000..7c362e26e5 --- /dev/null +++ b/arch/m68k/dts/M5485DFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485DFE"; + compatible = "fsl,M5485DFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485EFE.dts b/arch/m68k/dts/M5485EFE.dts new file mode 100644 index 0000000000..4c688dce2b --- /dev/null +++ b/arch/m68k/dts/M5485EFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485EFE"; + compatible = "fsl,M5485EFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485FFE.dts b/arch/m68k/dts/M5485FFE.dts new file mode 100644 index 0000000000..87ec2c543d --- /dev/null +++ b/arch/m68k/dts/M5485FFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485FFE"; + compatible = "fsl,M5485FFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485GFE.dts b/arch/m68k/dts/M5485GFE.dts new file mode 100644 index 0000000000..9f67e5516b --- /dev/null +++ b/arch/m68k/dts/M5485GFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485GFE"; + compatible = "fsl,M5485GFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/M5485HFE.dts b/arch/m68k/dts/M5485HFE.dts new file mode 100644 index 0000000000..2eb2213d78 --- /dev/null +++ b/arch/m68k/dts/M5485HFE.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf54xx.dtsi" + +/ { + model = "Freescale M5485HFE"; + compatible = "fsl,M5485HFE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + diff --git a/arch/m68k/dts/Makefile b/arch/m68k/dts/Makefile new file mode 100644 index 0000000000..53a53d6dc8 --- /dev/null +++ b/arch/m68k/dts/Makefile @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: GPL-2.0+ + +dtb-$(CONFIG_TARGET_M52277EVB) += M52277EVB.dtb \ + M52277EVB_stmicro.dtb +dtb-$(CONFIG_TARGET_M5235EVB) += M5235EVB.dtb \ + M5235EVB_Flash32.dtb +dtb-$(CONFIG_TARGET_COBRA5272) += cobra5272.dtb +dtb-$(CONFIG_TARGET_EB_CPU5282) += eb_cpu5282.dtb \ + eb_cpu5282_internal.dtb +dtb-$(CONFIG_TARGET_M5208EVBE) += M5208EVBE.dtb +dtb-$(CONFIG_TARGET_M5249EVB) += M5249EVB.dtb +dtb-$(CONFIG_TARGET_M5253DEMO) += M5253DEMO.dtb +dtb-$(CONFIG_TARGET_M5272C3) += M5272C3.dtb +dtb-$(CONFIG_TARGET_M5275EVB) += M5275EVB.dtb +dtb-$(CONFIG_TARGET_M5282EVB) += M5282EVB.dtb +dtb-$(CONFIG_TARGET_ASTRO_MCF5373L) += astro_mcf5373l.dtb +dtb-$(CONFIG_TARGET_M53017EVB) += M53017EVB.dtb +dtb-$(CONFIG_TARGET_M5373EVB) += M5373EVB.dtb +dtb-$(CONFIG_TARGET_M54418TWR) += M54418TWR.dtb \ + M54418TWR_nand_mii.dtb \ + M54418TWR_nand_rmii.dtb \ + M54418TWR_serial_mii.dtb \ + M54418TWR_serial_rmii.dtb \ + M54418TWR_nand_rmii_lowfreq.dtb +dtb-$(CONFIG_TARGET_M54451EVB) += M54451EVB.dtb \ + M54451EVB_stmicro.dtb +dtb-$(CONFIG_TARGET_M54455EVB) += M54455EVB.dtb \ + M54455EVB_intel.dtb \ + M54455EVB_stm33.dtb \ + M54455EVB_a66.dtb \ + M54455EVB_i66.dtb +dtb-$(CONFIG_TARGET_AMCORE) += amcore.dtb +dtb-$(CONFIG_TARGET_STMARK2) += stmark2.dtb +dtb-$(CONFIG_TARGET_M5475EVB) += M5475AFE.dtb \ + M5475BFE.dtb \ + M5475CFE.dtb \ + M5475DFE.dtb \ + M5475EFE.dtb \ + M5475FFE.dtb \ + M5475GFE.dtb +dtb-$(CONFIG_TARGET_M5485EVB) += M5485AFE.dtb \ + M5485BFE.dtb \ + M5485CFE.dtb \ + M5485DFE.dtb \ + M5485EFE.dtb \ + M5485FFE.dtb \ + M5485GFE.dtb \ + M5485HFE.dtb + +targets += $(dtb-y) + +DTC_FLAGS += -R 4 -p 0x1000 + +PHONY += dtbs +dtbs: $(addprefix $(obj)/, $(dtb-y)) + @: + +clean-files := *.dtb diff --git a/arch/m68k/dts/amcore.dts b/arch/m68k/dts/amcore.dts new file mode 100644 index 0000000000..c21fb8ff79 --- /dev/null +++ b/arch/m68k/dts/amcore.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5307.dtsi" + +/ { + model = "Sysam AMCORE"; + compatible = "sysam,AMCORE"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/astro_mcf5373l.dts b/arch/m68k/dts/astro_mcf5373l.dts new file mode 100644 index 0000000000..1b1a46ac2d --- /dev/null +++ b/arch/m68k/dts/astro_mcf5373l.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf537x.dtsi" + +/ { + model = "Astro mcf5373l"; + compatible = "astro,mcf5373l"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/cobra5272.dts b/arch/m68k/dts/cobra5272.dts new file mode 100644 index 0000000000..f3b74975de --- /dev/null +++ b/arch/m68k/dts/cobra5272.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5272.dtsi" + +/ { + model = "Cobra 5272"; + compatible = "cobra,M5272"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/eb_cpu5282.dts b/arch/m68k/dts/eb_cpu5282.dts new file mode 100644 index 0000000000..4641e9cb56 --- /dev/null +++ b/arch/m68k/dts/eb_cpu5282.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "BuS eb_cpuM5282"; + compatible = "bus,eb_cpuM5282"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/eb_cpu5282_internal.dts b/arch/m68k/dts/eb_cpu5282_internal.dts new file mode 100644 index 0000000000..0acb7935f4 --- /dev/null +++ b/arch/m68k/dts/eb_cpu5282_internal.dts @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5282.dtsi" + +/ { + model = "BuS eb_cpu5282_internals"; + compatible = "bus,eb_cpu5282_internals"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + diff --git a/arch/m68k/dts/stmark2.dts b/arch/m68k/dts/stmark2.dts new file mode 100644 index 0000000000..fd8ce4fa35 --- /dev/null +++ b/arch/m68k/dts/stmark2.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Angelo Dureghello angelo@sysam.it + */ + +/dts-v1/; +/include/ "mcf5441x.dtsi" + +/ { + model = "Sysam stmark2"; + compatible = "sysam,stmark2"; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&dspi0 { + spi-mode = <3>; + status = "okay"; + + flash: is25lp128@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + spi-max-frequency = <60000000>; + reg = <1>; + }; +};
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds basic dts files for all the m68k boards.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- none
arch/m68k/dts/M5208EVBE.dts | 22 +++++++ arch/m68k/dts/M52277EVB.dts | 25 ++++++++ arch/m68k/dts/M52277EVB_stmicro.dts | 22 +++++++ arch/m68k/dts/M5235EVB.dts | 22 +++++++ arch/m68k/dts/M5235EVB_Flash32.dts | 22 +++++++ arch/m68k/dts/M5249EVB.dts | 22 +++++++ arch/m68k/dts/M5253DEMO.dts | 22 +++++++ arch/m68k/dts/M5272C3.dts | 22 +++++++ arch/m68k/dts/M5275EVB.dts | 22 +++++++ arch/m68k/dts/M5282EVB.dts | 22 +++++++ arch/m68k/dts/M53017EVB.dts | 22 +++++++ arch/m68k/dts/M5329AFEE.dts | 22 +++++++ arch/m68k/dts/M5329BFEE.dts | 22 +++++++ arch/m68k/dts/M5373EVB.dts | 22 +++++++ arch/m68k/dts/M54418TWR.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_mii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_rmii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_serial_mii.dts | 25 ++++++++ arch/m68k/dts/M54418TWR_serial_rmii.dts | 25 ++++++++ arch/m68k/dts/M54451EVB.dts | 25 ++++++++ arch/m68k/dts/M54451EVB_stmicro.dts | 25 ++++++++ arch/m68k/dts/M54455EVB.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_a66.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_i66.dts | 25 ++++++++ arch/m68k/dts/M54455EVB_intel.dts | 26 +++++++++ arch/m68k/dts/M54455EVB_stm33.dts | 25 ++++++++ arch/m68k/dts/M5475AFE.dts | 13 +++++ arch/m68k/dts/M5475BFE.dts | 13 +++++ arch/m68k/dts/M5475CFE.dts | 13 +++++ arch/m68k/dts/M5475DFE.dts | 13 +++++ arch/m68k/dts/M5475EFE.dts | 13 +++++ arch/m68k/dts/M5475FFE.dts | 13 +++++ arch/m68k/dts/M5475GFE.dts | 13 +++++ arch/m68k/dts/M5485AFE.dts | 17 ++++++ arch/m68k/dts/M5485BFE.dts | 17 ++++++ arch/m68k/dts/M5485CFE.dts | 17 ++++++ arch/m68k/dts/M5485DFE.dts | 17 ++++++ arch/m68k/dts/M5485EFE.dts | 17 ++++++ arch/m68k/dts/M5485FFE.dts | 17 ++++++ arch/m68k/dts/M5485GFE.dts | 17 ++++++ arch/m68k/dts/M5485HFE.dts | 17 ++++++ arch/m68k/dts/Makefile | 58 +++++++++++++++++++ arch/m68k/dts/amcore.dts | 22 +++++++ arch/m68k/dts/astro_mcf5373l.dts | 22 +++++++ arch/m68k/dts/cobra5272.dts | 22 +++++++ arch/m68k/dts/eb_cpu5282.dts | 22 +++++++ arch/m68k/dts/eb_cpu5282_internal.dts | 22 +++++++ arch/m68k/dts/stmark2.dts | 34 +++++++++++ 49 files changed, 1066 insertions(+) create mode 100644 arch/m68k/dts/M5208EVBE.dts create mode 100644 arch/m68k/dts/M52277EVB.dts create mode 100644 arch/m68k/dts/M52277EVB_stmicro.dts create mode 100644 arch/m68k/dts/M5235EVB.dts create mode 100644 arch/m68k/dts/M5235EVB_Flash32.dts create mode 100644 arch/m68k/dts/M5249EVB.dts create mode 100644 arch/m68k/dts/M5253DEMO.dts create mode 100644 arch/m68k/dts/M5272C3.dts create mode 100644 arch/m68k/dts/M5275EVB.dts create mode 100644 arch/m68k/dts/M5282EVB.dts create mode 100644 arch/m68k/dts/M53017EVB.dts create mode 100644 arch/m68k/dts/M5329AFEE.dts create mode 100644 arch/m68k/dts/M5329BFEE.dts create mode 100644 arch/m68k/dts/M5373EVB.dts create mode 100644 arch/m68k/dts/M54418TWR.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii.dts create mode 100644 arch/m68k/dts/M54418TWR_nand_rmii_lowfreq.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_mii.dts create mode 100644 arch/m68k/dts/M54418TWR_serial_rmii.dts create mode 100644 arch/m68k/dts/M54451EVB.dts create mode 100644 arch/m68k/dts/M54451EVB_stmicro.dts create mode 100644 arch/m68k/dts/M54455EVB.dts create mode 100644 arch/m68k/dts/M54455EVB_a66.dts create mode 100644 arch/m68k/dts/M54455EVB_i66.dts create mode 100644 arch/m68k/dts/M54455EVB_intel.dts create mode 100644 arch/m68k/dts/M54455EVB_stm33.dts create mode 100644 arch/m68k/dts/M5475AFE.dts create mode 100644 arch/m68k/dts/M5475BFE.dts create mode 100644 arch/m68k/dts/M5475CFE.dts create mode 100644 arch/m68k/dts/M5475DFE.dts create mode 100644 arch/m68k/dts/M5475EFE.dts create mode 100644 arch/m68k/dts/M5475FFE.dts create mode 100644 arch/m68k/dts/M5475GFE.dts create mode 100644 arch/m68k/dts/M5485AFE.dts create mode 100644 arch/m68k/dts/M5485BFE.dts create mode 100644 arch/m68k/dts/M5485CFE.dts create mode 100644 arch/m68k/dts/M5485DFE.dts create mode 100644 arch/m68k/dts/M5485EFE.dts create mode 100644 arch/m68k/dts/M5485FFE.dts create mode 100644 arch/m68k/dts/M5485GFE.dts create mode 100644 arch/m68k/dts/M5485HFE.dts create mode 100644 arch/m68k/dts/Makefile create mode 100644 arch/m68k/dts/amcore.dts create mode 100644 arch/m68k/dts/astro_mcf5373l.dts create mode 100644 arch/m68k/dts/cobra5272.dts create mode 100644 arch/m68k/dts/eb_cpu5282.dts create mode 100644 arch/m68k/dts/eb_cpu5282_internal.dts create mode 100644 arch/m68k/dts/stmark2.dts
Reviewed-by: Simon Glass sjg@chromium.org
Growing of binary size asks for long assembly jumps.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - none --- arch/m68k/cpu/mcf547x_8x/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/m68k/cpu/mcf547x_8x/start.S b/arch/m68k/cpu/mcf547x_8x/start.S index 7cb5db7ff0..4dd57bf39c 100644 --- a/arch/m68k/cpu/mcf547x_8x/start.S +++ b/arch/m68k/cpu/mcf547x_8x/start.S @@ -131,7 +131,8 @@ _start: * then (and always) gd struct space will be reserved */ move.l %sp, -(%sp) - bsr board_init_f_alloc_reserve + move.l #board_init_f_alloc_reserve, %a1 + jsr (%a1)
/* update stack and frame-pointers */ move.l %d0, %sp @@ -139,7 +140,8 @@ _start:
/* initialize reserved area */ move.l %d0, -(%sp) - bsr board_init_f_init_reserve + move.l #board_init_f_init_reserve, %a1 + jsr (%a1)
/* run low-level CPU init code (from flash) */ jbsr cpu_init_f
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
Growing of binary size asks for long assembly jumps.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- none
arch/m68k/cpu/mcf547x_8x/start.S | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Enable DT usage for all m68k boards. To provide a working single binary, the dts has been kept as embedded.
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - none --- configs/M5208EVBE_defconfig | 2 ++ configs/M52277EVB_defconfig | 2 ++ configs/M52277EVB_stmicro_defconfig | 2 ++ configs/M5235EVB_Flash32_defconfig | 2 ++ configs/M5235EVB_defconfig | 2 ++ configs/M5249EVB_defconfig | 2 ++ configs/M5253DEMO_defconfig | 2 ++ configs/M5272C3_defconfig | 2 ++ configs/M5275EVB_defconfig | 3 +++ configs/M5282EVB_defconfig | 2 ++ configs/M53017EVB_defconfig | 2 ++ configs/M5329AFEE_defconfig | 2 ++ configs/M5329BFEE_defconfig | 2 ++ configs/M5373EVB_defconfig | 2 ++ configs/M54418TWR_defconfig | 2 ++ configs/M54418TWR_nand_mii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_lowfreq_defconfig | 2 ++ configs/M54418TWR_serial_mii_defconfig | 2 ++ configs/M54418TWR_serial_rmii_defconfig | 2 ++ configs/M54451EVB_defconfig | 2 ++ configs/M54451EVB_stmicro_defconfig | 2 ++ configs/M54455EVB_a66_defconfig | 2 ++ configs/M54455EVB_defconfig | 2 ++ configs/M54455EVB_i66_defconfig | 2 ++ configs/M54455EVB_intel_defconfig | 2 ++ configs/M54455EVB_stm33_defconfig | 2 ++ configs/M5475BFE_defconfig | 2 ++ configs/M5475CFE_defconfig | 2 ++ configs/M5475DFE_defconfig | 2 ++ configs/M5475EFE_defconfig | 2 ++ configs/M5475FFE_defconfig | 2 ++ configs/M5475GFE_defconfig | 2 ++ configs/M5485AFE_defconfig | 2 ++ configs/M5485BFE_defconfig | 2 ++ configs/M5485CFE_defconfig | 2 ++ configs/M5485DFE_defconfig | 2 ++ configs/M5485EFE_defconfig | 2 ++ configs/M5485FFE_defconfig | 2 ++ configs/M5485GFE_defconfig | 2 ++ configs/M5485HFE_defconfig | 2 ++ configs/amcore_defconfig | 2 ++ configs/astro_mcf5373l_defconfig | 2 ++ configs/cobra5272_defconfig | 2 ++ configs/eb_cpu5282_defconfig | 2 ++ configs/eb_cpu5282_internal_defconfig | 2 ++ configs/stmark2_defconfig | 2 ++ 47 files changed, 95 insertions(+)
diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 920476042d..69f44dface 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M5208EVBE=y +CONFIG_DEFAULT_DEVICE_TREE="M5208EVBE" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index 233e258a61..b41209ab6f 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M52277EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M52277EVB" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_SPANSION_BOOT" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index 573cea9655..d1a3e7db3c 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x43E00000 CONFIG_TARGET_M52277EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M52277EVB_stmicro" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT" CONFIG_BOOTDELAY=3 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 7d3b6d8581..1ae7ed5114 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFC00000 CONFIG_TARGET_M5235EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5235EVB_Flash32" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="NORFLASH_PS32BIT" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 78d8ddc130..5ecdcaccf4 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5235EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5235EVB" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index 8478136c6b..6c3cb549a9 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5249EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5249EVB" +CONFIG_OF_EMBED=y CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index 4685c4eb83..cdfe53c367 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5253DEMO=y +CONFIG_DEFAULT_DEVICE_TREE="M5253DEMO" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 7a4e1d4346..9d3f01aa20 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5272C3=y +CONFIG_DEFAULT_DEVICE_TREE="M5272C3" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 8619c89996..18ee897bec 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5275EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5275EVB" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set @@ -17,3 +19,4 @@ CONFIG_CMD_PING=y CONFIG_CMD_CACHE=y CONFIG_MTD_NOR_FLASH=y CONFIG_MII=y +CONFIG_DM_SERIAL=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 3f10c15a83..b0965f300f 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_M5282EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5282EVB" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 5b0430f3ef..65d19ad2aa 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M53017EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M53017EVB" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock3 rw rootfstype=jffs2" diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 0b66da2645..c7545f2fc4 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M5329EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5329AFEE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=0" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index b2c97b8485..12eea5713d 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M5329EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5329BFEE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index 38641f42e5..bb29b88961 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M5373EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5373EVB" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="NANDFLASH_SIZE=16" CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index f69f405d5a..20fec8a9a7 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index 04ca3a8114..b7cf5eca66 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_mii" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=25000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index f6acf6019d..fa40036a04 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 6b631d6d4b..95fbb8af7a 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_nand_rmii_lowfreq" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BOOT,LOW_MCFCLK,SYS_INPUT_CLKSRC=50000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock2 rw rootfstype=jffs2 mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro,-(jffs2) console=ttyS0,115200" diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index b2266a0577..39912675c7 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_mii" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=25000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index f69f405d5a..6635133652 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54418TWR=y +CONFIG_DEFAULT_DEVICE_TREE="M54418TWR_serial_rmii" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=50000000" CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=192.168.1.1:/tftpboot/192.168.1.2 ip=192.168.1.2:192.168.1.1:192.168.1.1: 255.255.255.0::eth0:off:rw console=ttyS0,115200" diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index 070c4e7392..81797cbaef 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M54451EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54451EVB" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_INPUT_CLKSRC=24000000" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index d819ad4112..a4f12c0dfd 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_M54451EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54451EVB_stmicro" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_STMICRO_BOOT,SYS_INPUT_CLKSRC=24000000" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index 75d85de27a..26bcab9799 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_TARGET_M54455EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_a66" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=66666666" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 84303f11c2..7a18ee01a9 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_TARGET_M54455EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54455EVB" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_ATMEL_BOOT,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index ec5d69ae9f..61256211c3 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M54455EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_i66" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=66666666" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index 7019cd66d9..ce3d3f0093 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x0 CONFIG_TARGET_M54455EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_intel" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_INTEL_BOOT,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index 62e9d26fa6..0ab2c6bcd8 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x4FE00000 CONFIG_TARGET_M54455EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M54455EVB_stm33" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_STMICRO_BOOT,CF_SBF,SYS_INPUT_CLKSRC=33333333" CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M5475BFE_defconfig b/configs/M5475BFE_defconfig index 29977f30a1..3a1194d9c5 100644 --- a/configs/M5475BFE_defconfig +++ b/configs/M5475BFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475BFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5475CFE_defconfig b/configs/M5475CFE_defconfig index 14f29469cc..6768b88e15 100644 --- a/configs/M5475CFE_defconfig +++ b/configs/M5475CFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475CFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5475DFE_defconfig b/configs/M5475DFE_defconfig index ee7e45648e..a674cbdf74 100644 --- a/configs/M5475DFE_defconfig +++ b/configs/M5475DFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475DFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5475EFE_defconfig b/configs/M5475EFE_defconfig index 302651f964..fa652b7780 100644 --- a/configs/M5475EFE_defconfig +++ b/configs/M5475EFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475EFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5475FFE_defconfig b/configs/M5475FFE_defconfig index a3f418862c..bdd2f695d5 100644 --- a/configs/M5475FFE_defconfig +++ b/configs/M5475FFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475FFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5475GFE_defconfig b/configs/M5475GFE_defconfig index 39d3409409..bb97851aab 100644 --- a/configs/M5475GFE_defconfig +++ b/configs/M5475GFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475GFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485AFE_defconfig b/configs/M5485AFE_defconfig index 496db41e34..ca0e186237 100644 --- a/configs/M5485AFE_defconfig +++ b/configs/M5485AFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485AFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485BFE_defconfig b/configs/M5485BFE_defconfig index b5b5153199..2b2999bed7 100644 --- a/configs/M5485BFE_defconfig +++ b/configs/M5485BFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485BFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485CFE_defconfig b/configs/M5485CFE_defconfig index a0446feac0..6c6752c6c3 100644 --- a/configs/M5485CFE_defconfig +++ b/configs/M5485CFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485CFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485DFE_defconfig b/configs/M5485DFE_defconfig index ba4f03c5bf..d351622538 100644 --- a/configs/M5485DFE_defconfig +++ b/configs/M5485DFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485DFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485EFE_defconfig b/configs/M5485EFE_defconfig index 0c24ab7b30..8c3ea2b22f 100644 --- a/configs/M5485EFE_defconfig +++ b/configs/M5485EFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485EFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_VIDEO,SYS_USBCTRL" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485FFE_defconfig b/configs/M5485FFE_defconfig index 1399d91b35..218d708a4e 100644 --- a/configs/M5485FFE_defconfig +++ b/configs/M5485FFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485FFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=32,SYS_VIDEO,SYS_USBCTRL,SYS_DRAMSZ1=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485GFE_defconfig b/configs/M5485GFE_defconfig index 162618b00b..1cc284d226 100644 --- a/configs/M5485GFE_defconfig +++ b/configs/M5485GFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485GFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=4,SYS_DRAMSZ=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/M5485HFE_defconfig b/configs/M5485HFE_defconfig index 201610c65a..eb0f5c36b7 100644 --- a/configs/M5485HFE_defconfig +++ b/configs/M5485HFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5485EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5485HFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=100000000,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index ce61e16c8d..c9e83ea825 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -2,6 +2,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFC00000 CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_TARGET_AMCORE=y +CONFIG_DEFAULT_DEVICE_TREE="amcore" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=1 CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index da6ebe7dcd..2456075cc3 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_TARGET_ASTRO_MCF5373L=y +CONFIG_DEFAULT_DEVICE_TREE="astro_mcf5373l" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS=" console=ttyS2,115200 rootfstype=romfs loaderversion=$loaderversion" diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index fc295af114..a0a3a91523 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFFE00000 CONFIG_TARGET_COBRA5272=y +CONFIG_DEFAULT_DEVICE_TREE="cobra5272" +CONFIG_OF_EMBED=y CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index 08965c9ac4..d5b35536a5 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF000000 CONFIG_TARGET_EB_CPU5282=y +CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xFF000400" CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index aaee4abe44..013e0cb750 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xF0000000 CONFIG_TARGET_EB_CPU5282=y +CONFIG_DEFAULT_DEVICE_TREE="eb_cpu5282_internal" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_MONITOR_BASE=0xF0000418" CONFIG_BOOTDELAY=5 # CONFIG_CONSOLE_MUX is not set diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 48e851d4a4..174a2f0a4e 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0x47E00000 CONFIG_TARGET_STMARK2=y +CONFIG_DEFAULT_DEVICE_TREE="stmark2" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="CF_SBF,SYS_SERIAL_BOOT,SYS_INPUT_CLKSRC=30000000" # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_HUSH_PARSER=y
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
Enable DT usage for all m68k boards. To provide a working single binary, the dts has been kept as embedded.
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- none
configs/M5208EVBE_defconfig | 2 ++ configs/M52277EVB_defconfig | 2 ++ configs/M52277EVB_stmicro_defconfig | 2 ++ configs/M5235EVB_Flash32_defconfig | 2 ++ configs/M5235EVB_defconfig | 2 ++ configs/M5249EVB_defconfig | 2 ++ configs/M5253DEMO_defconfig | 2 ++ configs/M5272C3_defconfig | 2 ++ configs/M5275EVB_defconfig | 3 +++ configs/M5282EVB_defconfig | 2 ++ configs/M53017EVB_defconfig | 2 ++ configs/M5329AFEE_defconfig | 2 ++ configs/M5329BFEE_defconfig | 2 ++ configs/M5373EVB_defconfig | 2 ++ configs/M54418TWR_defconfig | 2 ++ configs/M54418TWR_nand_mii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_defconfig | 2 ++ configs/M54418TWR_nand_rmii_lowfreq_defconfig | 2 ++ configs/M54418TWR_serial_mii_defconfig | 2 ++ configs/M54418TWR_serial_rmii_defconfig | 2 ++ configs/M54451EVB_defconfig | 2 ++ configs/M54451EVB_stmicro_defconfig | 2 ++ configs/M54455EVB_a66_defconfig | 2 ++ configs/M54455EVB_defconfig | 2 ++ configs/M54455EVB_i66_defconfig | 2 ++ configs/M54455EVB_intel_defconfig | 2 ++ configs/M54455EVB_stm33_defconfig | 2 ++ configs/M5475BFE_defconfig | 2 ++ configs/M5475CFE_defconfig | 2 ++ configs/M5475DFE_defconfig | 2 ++ configs/M5475EFE_defconfig | 2 ++ configs/M5475FFE_defconfig | 2 ++ configs/M5475GFE_defconfig | 2 ++ configs/M5485AFE_defconfig | 2 ++ configs/M5485BFE_defconfig | 2 ++ configs/M5485CFE_defconfig | 2 ++ configs/M5485DFE_defconfig | 2 ++ configs/M5485EFE_defconfig | 2 ++ configs/M5485FFE_defconfig | 2 ++ configs/M5485GFE_defconfig | 2 ++ configs/M5485HFE_defconfig | 2 ++ configs/amcore_defconfig | 2 ++ configs/astro_mcf5373l_defconfig | 2 ++ configs/cobra5272_defconfig | 2 ++ configs/eb_cpu5282_defconfig | 2 ++ configs/eb_cpu5282_internal_defconfig | 2 ++ configs/stmark2_defconfig | 2 ++ 47 files changed, 95 insertions(+)
Can you do this in arch/Kconfig?
Also please don't use CONFIG_OF_EMBED - that is just for debugging.
Regards, Simon
This patch adds CONFIG_DM_SPI for all m68k boards using the cf_spi.c driver (DSPI module).
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - none --- configs/M52277EVB_defconfig | 1 + configs/M52277EVB_stmicro_defconfig | 1 + configs/M54418TWR_defconfig | 1 + configs/M54418TWR_nand_mii_defconfig | 1 + configs/M54418TWR_nand_rmii_defconfig | 1 + configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 + configs/M54418TWR_serial_mii_defconfig | 1 + configs/M54418TWR_serial_rmii_defconfig | 1 + configs/M54451EVB_defconfig | 1 + configs/M54451EVB_stmicro_defconfig | 1 + configs/M54455EVB_a66_defconfig | 1 + configs/M54455EVB_defconfig | 1 + configs/M54455EVB_i66_defconfig | 1 + configs/M54455EVB_intel_defconfig | 1 + configs/M54455EVB_stm33_defconfig | 1 + configs/M5475AFE_defconfig | 2 ++ configs/stmark2_defconfig | 2 ++ 17 files changed, 19 insertions(+)
diff --git a/configs/M52277EVB_defconfig b/configs/M52277EVB_defconfig index b41209ab6f..3e67f6643d 100644 --- a/configs/M52277EVB_defconfig +++ b/configs/M52277EVB_defconfig @@ -23,4 +23,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M52277EVB_stmicro_defconfig b/configs/M52277EVB_stmicro_defconfig index d1a3e7db3c..2f3b664b67 100644 --- a/configs/M52277EVB_stmicro_defconfig +++ b/configs/M52277EVB_stmicro_defconfig @@ -22,4 +22,5 @@ CONFIG_MTD_NOR_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_defconfig b/configs/M54418TWR_defconfig index 20fec8a9a7..e57b24ff23 100644 --- a/configs/M54418TWR_defconfig +++ b/configs/M54418TWR_defconfig @@ -27,3 +27,4 @@ CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y CONFIG_CF_SPI=y +CONFIG_DM_SPI=y diff --git a/configs/M54418TWR_nand_mii_defconfig b/configs/M54418TWR_nand_mii_defconfig index b7cf5eca66..dcb1789824 100644 --- a/configs/M54418TWR_nand_mii_defconfig +++ b/configs/M54418TWR_nand_mii_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_defconfig b/configs/M54418TWR_nand_rmii_defconfig index fa40036a04..f483b15258 100644 --- a/configs/M54418TWR_nand_rmii_defconfig +++ b/configs/M54418TWR_nand_rmii_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_nand_rmii_lowfreq_defconfig b/configs/M54418TWR_nand_rmii_lowfreq_defconfig index 95fbb8af7a..848eeca893 100644 --- a/configs/M54418TWR_nand_rmii_lowfreq_defconfig +++ b/configs/M54418TWR_nand_rmii_lowfreq_defconfig @@ -25,4 +25,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_mii_defconfig b/configs/M54418TWR_serial_mii_defconfig index 39912675c7..f3abd72045 100644 --- a/configs/M54418TWR_serial_mii_defconfig +++ b/configs/M54418TWR_serial_mii_defconfig @@ -26,4 +26,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54418TWR_serial_rmii_defconfig b/configs/M54418TWR_serial_rmii_defconfig index 6635133652..d69e5598ff 100644 --- a/configs/M54418TWR_serial_rmii_defconfig +++ b/configs/M54418TWR_serial_rmii_defconfig @@ -26,4 +26,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54451EVB_defconfig b/configs/M54451EVB_defconfig index 81797cbaef..f1a2376231 100644 --- a/configs/M54451EVB_defconfig +++ b/configs/M54451EVB_defconfig @@ -28,4 +28,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54451EVB_stmicro_defconfig b/configs/M54451EVB_stmicro_defconfig index a4f12c0dfd..d3ee1677ca 100644 --- a/configs/M54451EVB_stmicro_defconfig +++ b/configs/M54451EVB_stmicro_defconfig @@ -27,4 +27,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_a66_defconfig b/configs/M54455EVB_a66_defconfig index 26bcab9799..5b6ef04674 100644 --- a/configs/M54455EVB_a66_defconfig +++ b/configs/M54455EVB_a66_defconfig @@ -32,4 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_defconfig b/configs/M54455EVB_defconfig index 7a18ee01a9..cb45fac3de 100644 --- a/configs/M54455EVB_defconfig +++ b/configs/M54455EVB_defconfig @@ -33,4 +33,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_i66_defconfig b/configs/M54455EVB_i66_defconfig index 61256211c3..4ee2aa855e 100644 --- a/configs/M54455EVB_i66_defconfig +++ b/configs/M54455EVB_i66_defconfig @@ -32,4 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_intel_defconfig b/configs/M54455EVB_intel_defconfig index ce3d3f0093..24a7ebbb84 100644 --- a/configs/M54455EVB_intel_defconfig +++ b/configs/M54455EVB_intel_defconfig @@ -32,4 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M54455EVB_stm33_defconfig b/configs/M54455EVB_stm33_defconfig index 0ab2c6bcd8..9e68bd3270 100644 --- a/configs/M54455EVB_stm33_defconfig +++ b/configs/M54455EVB_stm33_defconfig @@ -32,4 +32,5 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_MII=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_CF_SPI=y diff --git a/configs/M5475AFE_defconfig b/configs/M5475AFE_defconfig index 5f18579d52..59cefb11fb 100644 --- a/configs/M5475AFE_defconfig +++ b/configs/M5475AFE_defconfig @@ -1,6 +1,8 @@ CONFIG_M68K=y CONFIG_SYS_TEXT_BASE=0xFF800000 CONFIG_TARGET_M5475EVB=y +CONFIG_DEFAULT_DEVICE_TREE="M5475AFE" +CONFIG_OF_EMBED=y CONFIG_SYS_EXTRA_OPTIONS="SYS_BUSCLK=133333333,SYS_BOOTSZ=2,SYS_DRAMSZ=64" CONFIG_BOOTDELAY=1 # CONFIG_CMDLINE_EDITING is not set diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 174a2f0a4e..247b02da12 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -28,5 +28,7 @@ CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_ISSI=y CONFIG_SPI_FLASH_MTD=y CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y CONFIG_CF_SPI=y CONFIG_REGEX=y
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch adds CONFIG_DM_SPI for all m68k boards using the cf_spi.c driver (DSPI module).
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- none
configs/M52277EVB_defconfig | 1 + configs/M52277EVB_stmicro_defconfig | 1 + configs/M54418TWR_defconfig | 1 + configs/M54418TWR_nand_mii_defconfig | 1 + configs/M54418TWR_nand_rmii_defconfig | 1 + configs/M54418TWR_nand_rmii_lowfreq_defconfig | 1 + configs/M54418TWR_serial_mii_defconfig | 1 + configs/M54418TWR_serial_rmii_defconfig | 1 + configs/M54451EVB_defconfig | 1 + configs/M54451EVB_stmicro_defconfig | 1 + configs/M54455EVB_a66_defconfig | 1 + configs/M54455EVB_defconfig | 1 + configs/M54455EVB_i66_defconfig | 1 + configs/M54455EVB_intel_defconfig | 1 + configs/M54455EVB_stm33_defconfig | 1 + configs/M5475AFE_defconfig | 2 ++ configs/stmark2_defconfig | 2 ++ 17 files changed, 19 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
This patch removes CONFIG_SYS_DSPI_XX options from include/configs "m68k" .h board files, since CTAR registers are now set with default values in the cf_spi driver initialization, and configurable by devicetree.
Note, these options cannot be totally removed from the whitelist, since still used from boards using fsl_dspi.c (mostly arm-based boards).
Signed-off-by: Angelo Dureghello angelo@sysam.it --- Changes for v2: - new patch Changes for v3: - none --- include/configs/M52277EVB.h | 11 ----------- include/configs/M54418TWR.h | 12 ------------ include/configs/M54451EVB.h | 12 ------------ include/configs/M54455EVB.h | 10 ---------- include/configs/stmark2.h | 11 ----------- 5 files changed, 56 deletions(-)
diff --git a/include/configs/M52277EVB.h b/include/configs/M52277EVB.h index 1f79c1505a..07e89c9465 100644 --- a/include/configs/M52277EVB.h +++ b/include/configs/M52277EVB.h @@ -104,17 +104,6 @@ #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 -#ifdef CONFIG_CMD_SPI -# define CONFIG_SYS_DSPI_CS2 - -# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ - DSPI_CTAR_PCSSCK_1CLK | \ - DSPI_CTAR_PASC(0) | \ - DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | \ - DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(1)) -#endif
/* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h index 0d829b4e74..1bf21be734 100644 --- a/include/configs/M54418TWR.h +++ b/include/configs/M54418TWR.h @@ -153,18 +153,6 @@ #define CONFIG_SERIAL_FLASH #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 -#ifdef CONFIG_CMD_SPI - -# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ - DSPI_CTAR_PCSSCK_1CLK | \ - DSPI_CTAR_PASC(0) | \ - DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | \ - DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(1)) -# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) -# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) -#endif
/* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK diff --git a/include/configs/M54451EVB.h b/include/configs/M54451EVB.h index 5bd1d4f240..15635b33b5 100644 --- a/include/configs/M54451EVB.h +++ b/include/configs/M54451EVB.h @@ -118,18 +118,6 @@ #define CONFIG_SERIAL_FLASH #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x7 -#ifdef CONFIG_CMD_SPI - -# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ - DSPI_CTAR_PCSSCK_1CLK | \ - DSPI_CTAR_PASC(0) | \ - DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | \ - DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(1)) -# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) -# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) -#endif
/* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index 2de51d91a3..118078db3e 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -144,16 +144,6 @@ #define CONFIG_CF_DSPI #define CONFIG_HARD_SPI #define CONFIG_SYS_SBFHDR_SIZE 0x13 -#ifdef CONFIG_CMD_SPI - -# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ - DSPI_CTAR_PCSSCK_1CLK | \ - DSPI_CTAR_PASC(0) | \ - DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | \ - DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(1)) -#endif
/* PCI */ #ifdef CONFIG_CMD_PCI diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index c408db865e..ed145e1d50 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -72,17 +72,6 @@
#define CONFIG_SYS_SBFHDR_SIZE 0x7
-#define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ - DSPI_CTAR_PCSSCK_1CLK | \ - DSPI_CTAR_PASC(0) | \ - DSPI_CTAR_PDT(0) | \ - DSPI_CTAR_CSSCK(0) | \ - DSPI_CTAR_ASC(0) | \ - DSPI_CTAR_DT(1) | \ - DSPI_CTAR_BR(6)) -#define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) -#define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) - /* Input, PCI, Flexbus, and VCO */ #define CONFIG_EXTRA_CLOCK
On 13 October 2018 at 16:34, Angelo Dureghello angelo@sysam.it wrote:
This patch removes CONFIG_SYS_DSPI_XX options from include/configs "m68k" .h board files, since CTAR registers are now set with default values in the cf_spi driver initialization, and configurable by devicetree.
Note, these options cannot be totally removed from the whitelist, since still used from boards using fsl_dspi.c (mostly arm-based boards).
Signed-off-by: Angelo Dureghello angelo@sysam.it
Changes for v2:
- new patch
Changes for v3:
- none
include/configs/M52277EVB.h | 11 ----------- include/configs/M54418TWR.h | 12 ------------ include/configs/M54451EVB.h | 12 ------------ include/configs/M54455EVB.h | 10 ---------- include/configs/stmark2.h | 11 ----------- 5 files changed, 56 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
participants (3)
-
Angelo Dureghello -
Jagan Teki -
Simon Glass