Hi Kumar Gala

Thanks for ur kind reply.

Till, I am not clear why the resect vector points different address(0xefff_fffc).

From your reply, I understood Text_Base address is 0xeff8_0000, so the

resetvec address points to 0xefff_fffc.

For all 85xx processor except(MPC8572) the resetvec = 0xffff_fffc, Text_Base = 0xfff8_0000 For p4080 the resetvec = 0xefff_fffc,Text_Base = 0xeff8_0000

For p4080 why the resetvec and Text_Base address is different from the other 85xx processor ?.

Kumar Gala-3 wrote:

On Sep 8, 2010, at 8:48 AM, MArunKumar wrote:

...

Hi Im new to u-boot. Right now im in the process of customizing P4080DS(RDB) to my board. My doubt is, for P4080 the reset vec address is 0x0_ffff_fffc.

1. But in the config.mk file it is mentioned as 0xefff_fffc wat it mean?.

This is because the link address is 0xeff80000. We end up running at this address after the initial boot.

• k

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What board? You can basic support for P4080 in the git tree for u-boot.

• k

Thanks Kumar,

Now I am use p4080ds board from freescale, I download U-Boot

2010.06 version.I check the board code for freescale, just

find p2020 directory, no p4080 board.

You said U-Boot has basic support for P4080, can you give

some more detail informaion such as file name or directory

name?

Best Regards, /Tony

Thanks Dave and All,

For that reset address question, I think because p4080ds's FPGA can do this address decode and map 0xefffxxxx to 0xffffxxxx setting by SW7, is it right?

I also has another quesition, if I choose boot from bank0, why RCW should be programmed into address 0xe8000000? is it a rule of chip design?

Regards, /Tony

Liu Dave-R63238 <r63238 <at> freescale.com> writes:

...

For that reset address question, I think because p4080ds's FPGA can do

this address

...

decode and map 0xefffxxxx to 0xffffxxxx setting by SW7, is it right?

No. FPGA doesn't matter with it.

The e500mc core boot start address(0xFFFF_FFFC) will point to the end of CS0 Flash due to OR0[AM]=0. In this phase, the core is using the relative addressing. After you change the BR0,OR0, you can use absolute addressing.

Keep in mind, the bootloader is placed to the end of CS0, and the RCW is placed to the start of CS0.

...

I also has another quesition, if I choose boot from bank0, why RCW

should be

...

programmed into address 0xe8000000? is it a rule of chip design?

Thanks Dave,

It look same as other PQ2/3 which using BR0/OR0 to set boot vecror base address.

just confirm, do you know CPU will read RCW data before it jump to 0xFFFF_FFFC?

/Tony

hi Kindly let me know how the branch instruction is loaded in reset vector address (0xffff_fffc), but i have mapped my boot flash from 0xE000_0000 to EFFF_FFFF in LAW. please clarify me.

Liu Dave-R63238-2 wrote:

...

It look same as other PQ2/3 which using BR0/OR0 to set boot vecror

base address.

...

just confirm, do you know CPU will read RCW data before it jump to

0xFFFF_FFFC?

Yes. CPU reset module must fetch RCW and configure CPU itself. then reset to 0xFFFF_FFFC, it is also same as PQ3.

Thanks, Dave

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