[PATCH 1/2] imx8mm_beacon: Enable QSPI Support
There is a QSPI chip connected to the FSPI. Enable the defconfig to support it.
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 49d5453078..2970e5dc71 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -78,6 +79,14 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -102,7 +111,6 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_SPI_MEM=y CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y
In order to support the QSPI chip on the SOM, the Flexspi bus needs to be configured to talk with the SPI chip. Resync the som device tree with 5.11-rc4
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index b88c3c99b0..d897913537 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */
/ { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; @@ -24,6 +29,18 @@ cpu-supply = <&buck2_reg>; };
+&A53_1 { + cpu-supply = <&buck2_reg>; +}; + +&A53_2 { + cpu-supply = <&buck2_reg>; +}; + +&A53_3 { + cpu-supply = <&buck2_reg>; +}; + &ddrc { operating-points-v2 = <&ddrc_opp_table>;
@@ -63,6 +80,22 @@ }; };
+&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi>; + status = "okay"; + + flash@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <80000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + &i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -78,6 +111,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered;
+ #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "buck1"; @@ -191,7 +228,7 @@ reg = <0x50>; };
- rtc@51 { + rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; }; @@ -258,155 +295,166 @@ };
&iomuxc { - pinctrl_fec1: fec1grp { - fsl,pins = < - MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 - MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 - MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f - MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f - MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f - MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f - MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 - MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 - MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 - MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 - MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f - MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 - MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 - MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 - >; - }; + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19 + >; + };
- pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 - >; - }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 + >; + };
- pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 - >; - }; + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 + >; + };
- pinctrl_pmic: pmicirqgrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 - >; - }; + pinctrl_flexspi: flexspigrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 + >; + };
- pinctrl_uart1: uart1grp { - fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 - MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 - MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 - MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 - MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 - MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 - MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 - MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 - >; - }; + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 + >; + };
- pinctrl_usdhc1_gpio: usdhc1gpiogrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 - >; - }; + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 + MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140 + MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140 + MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19 + MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19 + MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19 + MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 + >; + };
- pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 - >; - }; + pinctrl_usdhc1_gpio: usdhc1gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 + >; + };
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 - >; - }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + >; + };
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 - MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 - MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 - MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 - MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 - MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 - >; - }; + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + >; + };
- pinctrl_usdhc3: usdhc3grp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 - >; - }; + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + >; + };
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 - >; - }; + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190 + >; + };
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { - fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 - MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 - MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 - MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 - MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 - MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 - >; - }; + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194 + >; + };
- pinctrl_wdog: wdoggrp { - fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 - >; - }; + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6 + MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6 + MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6 + MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6 + MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196 + >; + };
- pinctrl_wlan: wlangrp { - fsl,pins = < - MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 - >; - }; + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 + >; + }; + + pinctrl_wlan: wlangrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111 + >; + }; };
Subject: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4
In order to support the QSPI chip on the SOM, the Flexspi bus needs to be configured to talk with the SPI chip. Resync the som device tree with 5.11-rc4
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index b88c3c99b0..d897913537 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */
/ {
- aliases {
rtc0 = &rtc;rtc1 = &snvs_rtc;
Acked-by: Peng Fan peng.fan@nxp.com
Just have a question here, why you have two RTC here?
- };
- usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default";
@@ -24,6 +29,18 @@ cpu-supply = <&buck2_reg>; };
+&A53_1 {
- cpu-supply = <&buck2_reg>;
+};
+&A53_2 {
- cpu-supply = <&buck2_reg>;
+};
+&A53_3 {
- cpu-supply = <&buck2_reg>;
+};
&ddrc { operating-points-v2 = <&ddrc_opp_table>;
@@ -63,6 +80,22 @@ }; };
+&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi>;
- status = "okay";
- flash@0 {
reg = <0>;#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <80000000>;spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;- };
+};
&i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -78,6 +111,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered;
#clock-cells = <0>;clocks = <&osc_32k 0>;clock-output-names = "clk-32k-out";- regulators { buck1_reg: BUCK1 { regulator-name = "buck1";
@@ -191,7 +228,7 @@ reg = <0x50>; };
- rtc@51 {
- rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; };
@@ -258,155 +295,166 @@ };
&iomuxc {
pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91- MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTLMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;};
- pinctrl_fec1: fec1grp {
fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTLMX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTLMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;- };
pinctrl_i2c1: i2c1grp {fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCLMX8MM_IOMUXC_I2C1_SDA_I2C1_SDA>;};
- pinctrl_i2c1: i2c1grp {
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3>;- };
pinctrl_i2c3: i2c3grp {fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCLMX8MM_IOMUXC_I2C3_SDA_I2C3_SDA>;};
- pinctrl_i2c3: i2c3grp {
fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3>;- };
pinctrl_pmic: pmicirqgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;};
- pinctrl_flexspi: flexspigrp {
fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA00x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA10x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA20x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA30x82
>;- };
pinctrl_uart1: uart1grp {fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RXMX8MM_IOMUXC_UART1_TXD_UART1_DCE_TXMX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_BMX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_BMX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K>;};
- pinctrl_pmic: pmicirqgrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;- };
pinctrl_usdhc1_gpio: usdhc1gpiogrp {fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;};
- pinctrl_uart1: uart1grp {
fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_BMX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K>;- };
pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLKMX8MM_IOMUXC_SD1_CMD_USDHC1_CMDMX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3>;};
- pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;- };
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLKMX8MM_IOMUXC_SD1_CMD_USDHC1_CMDMX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3>;};
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>;- };
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLKMX8MM_IOMUXC_SD1_CMD_USDHC1_CMDMX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3>;};
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>;- };
pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLKMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;};
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>;- };
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLKMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;};
- pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;- };
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLKMX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;};
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;- };
pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;};
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMDMX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE>;- };
pinctrl_wlan: wlangrp {fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9>;};
- pinctrl_wdog: wdoggrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B>;- };
- pinctrl_wlan: wlangrp {
fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111>;- };
};
2.25.1
On Mon, Jan 18, 2021 at 7:44 PM Peng Fan peng.fan@nxp.com wrote:
Subject: [PATCH 2/2] arm64: dts: imx8mm-beacon: Resync imx8mm-beacon-som with 5.11-rc4
In order to support the QSPI chip on the SOM, the Flexspi bus needs to be configured to talk with the SPI chip. Resync the som device tree with 5.11-rc4
Signed-off-by: Adam Ford aford173@gmail.com
diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index b88c3c99b0..d897913537 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */
/ {
aliases {rtc0 = &rtc;rtc1 = &snvs_rtc;Acked-by: Peng Fan peng.fan@nxp.com
Just have a question here, why you have two RTC here?
The external one consumes much less power than the internal one. It's used for maintaining time while power is removed. The internal one was kept enabled because while powered, it can still be used for alarms, wake, etc. without losing functionality.
adam
};usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default";@@ -24,6 +29,18 @@ cpu-supply = <&buck2_reg>; };
+&A53_1 {
cpu-supply = <&buck2_reg>;+};
+&A53_2 {
cpu-supply = <&buck2_reg>;+};
+&A53_3 {
cpu-supply = <&buck2_reg>;+};
&ddrc { operating-points-v2 = <&ddrc_opp_table>;
@@ -63,6 +80,22 @@ }; };
+&flexspi {
pinctrl-names = "default";pinctrl-0 = <&pinctrl_flexspi>;status = "okay";flash@0 {reg = <0>;#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <80000000>;spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;};+};
&i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -78,6 +111,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered;
#clock-cells = <0>;clocks = <&osc_32k 0>;clock-output-names = "clk-32k-out";regulators { buck1_reg: BUCK1 { regulator-name = "buck1";@@ -191,7 +228,7 @@ reg = <0x50>; };
rtc@51 {
rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; };@@ -258,155 +295,166 @@ };
&iomuxc {
pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1fMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;};
pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1fMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;};
pinctrl_i2c1: i2c1grp {fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3>;};
pinctrl_i2c1: i2c1grp {fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3>;};
pinctrl_i2c3: i2c3grp {fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3>;};
pinctrl_i2c3: i2c3grp {fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3>;};
pinctrl_pmic: pmicirqgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;};
pinctrl_flexspi: flexspigrp {fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK0x1c2
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B0x82
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA00x82
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA10x82
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA20x82
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA30x82
>;};
pinctrl_uart1: uart1grp {fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141>;};
pinctrl_pmic: pmicirqgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;};
pinctrl_uart1: uart1grp {fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141>;};
pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>;};
pinctrl_usdhc1_gpio: usdhc1gpiogrp {fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>;};
pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>;};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>;};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>;};
pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190>;};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>;};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194>;};
pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190>;};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196>;};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194>;};
pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196>;};
pinctrl_wlan: wlangrp {fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111>;};
pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>;};pinctrl_wlan: wlangrp {fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111>;};};
2.25.1
In order to support the QSPI chip on the SOM, the Flexspi bus needs to be configured to talk with the SPI chip. Resync the som device tree with 5.11-rc4 Signed-off-by: Adam Ford aford173@gmail.com Acked-by: Peng Fan peng.fan@nxp.com diff --git a/arch/arm/dts/imx8mm-beacon-som.dtsi b/arch/arm/dts/imx8mm-beacon-som.dtsi index b88c3c99b0..d897913537 100644 --- a/arch/arm/dts/imx8mm-beacon-som.dtsi +++ b/arch/arm/dts/imx8mm-beacon-som.dtsi @@ -4,6 +4,11 @@ */
/ {
- aliases {
rtc0 = &rtc;rtc1 = &snvs_rtc;- };
- usdhc1_pwrseq: usdhc1_pwrseq { compatible = "mmc-pwrseq-simple"; pinctrl-names = "default";
@@ -24,6 +29,18 @@ cpu-supply = <&buck2_reg>; };
+&A53_1 {
- cpu-supply = <&buck2_reg>;
+};
+&A53_2 {
- cpu-supply = <&buck2_reg>;
+};
+&A53_3 {
- cpu-supply = <&buck2_reg>;
+};
&ddrc { operating-points-v2 = <&ddrc_opp_table>;
@@ -63,6 +80,22 @@ }; };
+&flexspi {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexspi>;
- status = "okay";
- flash@0 {
reg = <0>;#address-cells = <1>;#size-cells = <1>;compatible = "jedec,spi-nor";spi-max-frequency = <80000000>;spi-tx-bus-width = <4>;spi-rx-bus-width = <4>;- };
+};
&i2c1 { clock-frequency = <400000>; pinctrl-names = "default"; @@ -78,6 +111,10 @@ interrupts = <3 IRQ_TYPE_LEVEL_LOW>; rohm,reset-snvs-powered;
#clock-cells = <0>;clocks = <&osc_32k 0>;clock-output-names = "clk-32k-out";- regulators { buck1_reg: BUCK1 { regulator-name = "buck1";
@@ -191,7 +228,7 @@ reg = <0x50>; };
- rtc@51 {
- rtc: rtc@51 { compatible = "nxp,pcf85263"; reg = <0x51>; };
@@ -258,155 +295,166 @@ };
&iomuxc {
pinctrl_fec1: fec1grp {fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1fMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;};
- pinctrl_fec1: fec1grp {
fsl,pins = <MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1fMX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1fMX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1fMX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1fMX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1fMX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1fMX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19>;- };
pinctrl_i2c1: i2c1grp {fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3>;};
- pinctrl_i2c1: i2c1grp {
fsl,pins = <MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3>;- };
pinctrl_i2c3: i2c3grp {fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3>;};
- pinctrl_i2c3: i2c3grp {
fsl,pins = <MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3>;- };
pinctrl_pmic: pmicirqgrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;};
- pinctrl_flexspi: flexspigrp {
fsl,pins = <MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82>;- };
pinctrl_uart1: uart1grp {fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141>;};
- pinctrl_pmic: pmicirqgrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141>;- };
pinctrl_usdhc1_gpio: usdhc1gpiogrp {fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;};
- pinctrl_uart1: uart1grp {
fsl,pins = <MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x19MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x19MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141>;- };
pinctrl_usdhc1: usdhc1grp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>;};
- pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41>;- };
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>;};
- pinctrl_usdhc1: usdhc1grp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0>;- };
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>;};
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4>;- };
pinctrl_usdhc3: usdhc3grp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190>;};
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6>;- };
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194>;};
- pinctrl_usdhc3: usdhc3grp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190>;- };
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196>;};
- pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194>;- };
pinctrl_wdog: wdoggrp {fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6>;};
- pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196>;- };
pinctrl_wlan: wlangrp {fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111>;};
- pinctrl_wdog: wdoggrp {
fsl,pins = <MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166>;- };
- pinctrl_wlan: wlangrp {
fsl,pins = <MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x111>;- };
};
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
Subject: [PATCH 1/2] imx8mm_beacon: Enable QSPI Support
There is a QSPI chip connected to the FSPI. Enable the defconfig to support it.
Signed-off-by: Adam Ford aford173@gmail.com
Reviewed-by: Peng Fan peng.fan@nxp.com
diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 49d5453078..2970e5dc71 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -78,6 +79,14 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -102,7 +111,6 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_SPI_MEM=y CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y -- 2.25.1
There is a QSPI chip connected to the FSPI. Enable the defconfig to support it. Signed-off-by: Adam Ford aford173@gmail.com Reviewed-by: Peng Fan peng.fan@nxp.com diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 49d5453078..2970e5dc71 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_PART=y +CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y CONFIG_CMD_PING=y @@ -78,6 +79,14 @@ CONFIG_MMC_HS400_ES_SUPPORT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_SPL_MMC_HS400_SUPPORT=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=10000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y CONFIG_PHYLIB=y CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y @@ -102,7 +111,6 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_SPI=y CONFIG_DM_SPI=y -CONFIG_SPI_MEM=y CONFIG_NXP_FSPI=y CONFIG_SYSRESET=y CONFIG_SPL_SYSRESET=y
Applied to u-boot-imx, master, thanks !
Best regards, Stefano Babic
participants (3)
-
Adam Ford -
Peng Fan -
sbabic＠denx.de