Hi Tom,

Please pull some riscv updates:

- add DM based reset driver for SiFive SoC's.

Thanks Rick

https://travis-ci.org/github/rickchen36/u-boot-riscv/builds/714339244

The following changes since commit 68941e3b2c217907a49aa66af8bb65729b913397:

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 (2020-08-03 10:25:47 -0400)

are available in the Git repository at:

git@gitlab.denx.de:u-boot/custodians/u-boot-riscv.git

for you to fetch changes up to ed50d3fae49b9dad58674b6609913beeac824e42:

configs: reset: fu540: enable dm reset framework for SiFive (2020-08-04 09:19:41 +0800)

---------------------------------------------------------------- Sagar Shrikant Kadam (5): dt-bindings: prci: add indexes for reset signals available in prci fu540: prci: use common reset indexes defined in binding header fu540: dtsi: add reset producer and consumer entries sifive: reset: add DM based reset driver for SiFive SoC's configs: reset: fu540: enable dm reset framework for SiFive

arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 ++++++++++++ arch/riscv/include/asm/arch-fu540/reset.h | 13 +++++++++++++ configs/sifive_fu540_defconfig | 2 ++ drivers/clk/sifive/fu540-prci.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------------------------- drivers/reset/Kconfig | 9 +++++++++ drivers/reset/Makefile | 1 + drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++++++++++++++++ 8 files changed, 239 insertions(+), 25 deletions(-) create mode 100644 arch/riscv/include/asm/arch-fu540/reset.h create mode 100644 drivers/reset/reset-sifive.c create mode 100644 include/dt-bindings/reset/sifive-fu540-prci.h