From: Siva Durga Prasad Paladugu siva.durga.paladugu@xilinx.com

DDR less systems are possible for configuration like mini qspi and making DDR region as normal memory may cause speculative access which results u-boot hang if DDR is absent. So, this patch fixes the issue by not making DDR memory region entry into MMU table.

Future solution is to prepare MMU table per memory node in dts instead of hard code DDR addresses.

Signed-off-by: Siva Durga Prasad Paladugu sivadur@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/cpu/armv8/zynqmp/Kconfig | 6 ++++++ arch/arm/cpu/armv8/zynqmp/cpu.c | 16 ++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig index 3f922b4097a6..46de13054f26 100644 --- a/arch/arm/cpu/armv8/zynqmp/Kconfig +++ b/arch/arm/cpu/armv8/zynqmp/Kconfig @@ -68,6 +68,12 @@ config PMUFW_INIT_FILE config ZYNQMP_USB bool "Configure ZynqMP USB"

+config ZYNQMP_NO_DDR + bool "Disable DDR MMU mapping" + help + This option configures MMU with no DDR to avoid speculative + access to DDR memory where DDR is not present. + config SYS_MALLOC_F_LEN default 0x600

diff --git a/arch/arm/cpu/armv8/zynqmp/cpu.c b/arch/arm/cpu/armv8/zynqmp/cpu.c index 4596d6bff479..bc77dd03c361 100644 --- a/arch/arm/cpu/armv8/zynqmp/cpu.c +++ b/arch/arm/cpu/armv8/zynqmp/cpu.c @@ -17,20 +17,24 @@ DECLARE_GLOBAL_DATA_PTR;

static struct mm_region zynqmp_mem_map[] = { +#if !defined(CONFIG_ZYNQMP_NO_DDR) { .virt = 0x0UL, .phys = 0x0UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x80000000UL, .phys = 0x80000000UL, .size = 0x70000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, + { .virt = 0xf8000000UL, .phys = 0xf8000000UL, .size = 0x07e00000UL, @@ -52,13 +56,17 @@ static struct mm_region zynqmp_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN - }, { + }, +#if !defined(CONFIG_ZYNQMP_NO_DDR) + { .virt = 0x800000000UL, .phys = 0x800000000UL, .size = 0x800000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE - }, { + }, +#endif + { .virt = 0x1000000000UL, .phys = 0x1000000000UL, .size = 0xf000000000UL,